Abstract: A calculation system includes a variable memory storing a value indicating a state of a variable of a mixed integer quadratic programming problem; a state transition calculation block that calculates the next state of the value indicating the state of the variable; a nonlinear coefficient memory that stores a nonlinear coefficient of the state transition calculation block; a linear coefficient memory that stores a linear coefficient of the state transition calculation block; a weight input line that receives a weight signal of the state transition calculation block; and a temperature input line that receives a temperature signal of the state transition calculation block. The state transition calculation block includes a difference calculation block that calculates a difference calculation by using the weight signal, the nonlinear coefficient, and the linear coefficient. A next state determination block calculates the next state of the variable using the value read from the variable memory.

Abstract: Systems, apparatuses, and methods related to bit string accumulation are described. A method for bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and modifying a quantity of bits of a result of the iteration of the recursive operation, wherein the modified quantity of bits is less than a threshold quantity of bits. The method can further include writing a first value comprising the modified bits indicative of the result of the iteration of the recursive operation to a first register and writing a second value indicative of the factor corresponding to the result of the iteration of the recursive operation to a second register.

Abstract: The invention relates to a method for determining a value of an integer scaling in a linking of input sets to output sets, wherein the linking comprises operators, each of which has operator inputs and operator outputs that are at least partially linked to one another or to the input sets or to the output sets, by using a computer device having a processing unit, a memory unit, and an output unit. Representations of set objects are used to efficiently carry out rescaling operations within the linking, with up to infinitely large resolution sets. This procedure makes it possible to calculate resource-conserving integer scalings for a target system while taking secondary conditions into account.

Abstract: System and computer-implemented method for migrating a tree structure with multiple virtual disks and multiple virtual computing instances from a source computing environment to a destination computing environment involves handling leaf and shared virtual disks of the tree structure differently on a level-by-level basis to produce a replicated tree structure in the destination computing environment. For a leaf virtual disk, the leaf virtual disk and a virtual computing instance attached to the leaf virtual disk are replicated in the destination computing environment. For a shared virtual disk, creating a dummy virtual computing instance is created in the source computing environment and the shared virtual disk and the dummy virtual computing instance are replicated in the destination computing environment. Any dummy virtual computing instances replicated in the destination computing environment for the migration can then be removed.

Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: synchronizing, by one or more processor, first virtual machine(s) with a second virtual machine, the synchronizing comprising mirroring first input events to the first virtual machine(s); and customizing, by the one or more processor, the first virtual machine(s), the customizing comprising suspending the synchronizing and facilitating sending of second input events to the first virtual machine(s). In one embodiment, the synchronizing comprises cloning the second virtual machine to create the first virtual machine(s), the cloning comprising initializing the first virtual machine(s), and copying second virtual machine state information to the first virtual machine(s).

Abstract: A method for multidimensional scaling (MDS) of a data set comprising a plurality of data elements is provided, wherein each data element is identified by its coordinates, the method comprising the steps of: (i) applying an iterative optimization technique, such as SMACOF, a predetermined amount of times on a coordinates vector, said coordinates vector representing the coordinates of a plurality of said data elements, and obtaining a modified coordinates vector; (ii) applying a vector extrapolation technique, such as Minimal Polynomial Extrapolation (MPE) or reduced Rank Extrapolation (RRE) on said modified coordinates vector obtaining a further modified coordinates vector; and (iii) repeating steps (i) and (ii) until one or more predefined conditions are met.

Abstract: A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated.

Abstract: A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated.

Abstract: The invention provides a fractional order series resonance system for wireless electric energy transmission, comprising a high-frequency power source, a transmitting component, a receiving component and a load, the transmitting component comprises a primary-side fractional order capacitance, a primary-side fractional order inductance that are connected in series, the primary-side fractional order inductance has a primary-side resistance; the receiving component comprises a secondary-side fractional order capacitance and a secondary-side factional order inductance that are connected in series, the secondary-side factional order inductance has a secondary-side resistance. The invention employs fractional order elements to realize wireless power transmission, and it adds dimensions for parameter design and is totally different from traditional wireless power transmission system implemented by integer order elements.

Abstract: Technologies are disclosed for mapping documents to candidate duplicate documents in a document corpus. A bitset optimized inverted index is created for a document corpus. A document is received for which candidate duplicate documents in the document corpus are to be identified. The document is tokenized using adaptive tokenization. A determination made as to whether tokens in the document are represented in the bitset optimized inverted index. A list of candidate duplicate documents is created for tokens represented in the optimized inverted index utilizing in-memory bitsets that map tokens to documents that contain the tokens in the document corpus.

Abstract: A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: A method of operating a data processing system to infer demographic information for a user of a wireless communication device comprises processing a plurality of call detail records (CDRs) to generate a plurality of call graphs having different time slices based on time ranges when data in the CDRs was collected, wherein the call graphs comprise nodes that represent individual callers and edges between the nodes that represent bi-directional communication between the individual callers. The method further comprises identifying neighbors of the user that have a high likelihood of sharing a common demographic attribute with the user based on communication features and structural features among the neighbors on one of the call graphs. The method further comprises identifying a most similar neighbor among the neighbors of the user that has a highest likelihood of sharing the common demographic attribute with the user.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

Abstract: A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.

Abstract: A method is disclosed for encoding and decoding integer values ranging over a known gamut of values used by a data system. By noting that a data system may store and/or transmit integer values over a predefined gamut having a minimum and a maximum limit, integer values at or near the maximum may be compressed to a greater degree than in conventional systems without any loss of data resolution.

Abstract: Generation of standardized noise signals that provide mathematically correct noise with no errors and no loss of data, and can generate the noise of specific environments based on the transfer function of that environment are discussed. Various embodiments can generate synthetic data sets based on natural data sets that have similar scaling behavior. Fractional scaling digital filters, containing the fractional scaling characteristics of one or more of the eleven fundamental forms of basic building block transfer functions which incorporate the scaling exponent, can be encoded on FPGA devices or DSP chips for use in digital signal processing. Fractional Scaling Digital Filters allow fractional calculus, and thus fractional filtering (e.g.

Abstract: A circuit and method for accelerating function evaluation. In one embodiment, a processor includes a function accelerator unit configured to evaluate a mathematical function. The function accelerator unit includes a coefficient generator and a polynomial evaluator. The coefficient generator is configured to generate coefficients for a polynomial evaluated to produce a solution to the function. The coefficient generator varies values of the coefficients based on an input value at which the function is to be evaluated. The polynomial evaluator configured to apply the coefficients provided by the coefficient generator to evaluate the polynomial at the input value.

Abstract: Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be grouped, or assigned into levels. The levels may be scaled and applied at unique intervals of calculational steps. A quantum device may have circuitry for applying levels of the operator at the unique intervals.

Abstract: An image processor includes generates a content adaptive kernel from an image block with noise of a luminance component signal with a low resolution. The content adaptive kernel is convolved with the luminance component signal. A noise signal and an extracted texture which excludes noise are generated. The luminance component signal is filtered as function of the noise signal to generate an enhanced luminance component signal. Horizontal and vertical scaling is performed on the enhanced luminance component signal, the extracted texture, and the luminance component signal, with the luminance component signal adaptively scaled as a function of the extracted texture. The horizontally and vertically scaled enhanced luminance component signal, extracted texture and luminance component signal are then combined to generate an output luminance component signal with a high resolution.

Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimize underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.

Abstract: System and method for developing a circuit for QR decomposition with auxiliary functionality. A first function is included in a first program. The first function is configurable to specify an auxiliary function to be performed by a modified QR decomposition circuit in addition to QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt process. A second program is automatically generated based on configuration of the QR decomposition and the first function. The second program includes program code implementing the QR decomposition and the auxiliary function for the first function in the first program. A hardware configuration program (HCP) may be automatically generated based on the first program, including the second program, where the HCP is deployable to hardware, e.g., a programmable hardware element, thereby implementing the modified QR decomposition circuit, including the QR decomposition of the matrix A and the auxiliary function.

Abstract: System and method for computing QR matrix decomposition and inverse matrix R?1. A circuit is configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt (MGS) process. The circuit includes a specified portion dedicated to computing matrix Q. Matrix Q is computed via the specified portion based on first inputs using the MGS process, where the first inputs include the matrix A and possibly a scaling factor ?. The identity matrix may be scaled by the scaling factor ?, thereby generating scaled identity matrix ?I. Scaled matrix ?R?1 (or unscaled R?1) may be computed via the specified portion based on second inputs provided to the portion using the MGS process, where the second inputs include the (possibly scaled) identity matrix. If scaled, the scaled matrix ?R?1 may be unscaled, thereby computing matrix R?1. Matrix R?1 is stored and/or output.

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.

Abstract: Methods for determining the transfer function of a signal-processing system that do not require a known input signal. The methods are based on two representations 1(x) and I2(x) of an object, which the system has produced from differently scaled input signals originating from the object, or from a representation I1(x) of a first object and from a representation I2(x) of an object that is geometrically similar thereto but has been scaled differently. The representations are either given or are produced at the start of the method. According to the invention, the representations are transformed into a working space, and sections that relate to the same region of the object are selected in each case. The quotient of the functions corresponding to these two sections in the working space from which the unknown input signal comes makes it possible to clearly determine the transfer function sought. Various methods are indicated for this determination.

Abstract: A multi-purpose scaler utilizes a vertical scaler module and a moveable horizontal scaler module to resample a video signal either vertically or horizontally according to a selected scaling ratio. The moveable horizontal scaler module resides in one of two slots within the multi-purpose scaler architecture to provide either horizontal reduction or horizontal expansion as desired. The multi-purpose scaler is arranged to scale the video using non-linear 3 zone scaling in both the vertical and horizontal direction when selected. The multi-purpose scaler is arranged to provide vertical keystone correction and vertical height distortion correction when the video is presented through a projector at a non-zero tilt angle. The multi-purpose scaler is also arranged to provide interlacing and de-interlacing of the video frames as necessary.

Abstract: Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

Abstract: A method for multidimensional scaling (MDS) of a data set comprising a plurality of data elements is provided, wherein each data element is identified by its coordinates, the method comprising the steps of: (i) applying an iterative optimization technique, such as SMACOF, a predetermined amount of times on a coordinates vector, said coordinates vector representing the coordinates of a plurality of said data elements, and obtaining a modified coordinates vector; (ii) applying a vector extrapolation technique, such as Minimal Polynomial Extrapolation (MPE) or reduced Rank Extrapolation (RRE) on said modified coordinates vector obtaining a further modified coordinates vector; and (iii) repeating steps (i) and (ii) until one or more predefined conditions are met.

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract: A method for performing decimal division comprises: scaling a unsigned divisor D to a range; calculating multiplies of the scaled unsigned divisor D; storing multiples of the scaled unsigned divisor in a register; predicting a next single-bit quotient using a remainder Ri; and selecting a quotient using the reminder determining if a first number S1 of a remainder of a scaled unsigned dividend B is equal to or greater than 6; calculating B?5D; and storing B?5D as Ri in a remainder register.

Abstract: The present invention provides a security and privacy enhanced method for geolocation. The system works by creating a space called the N?4Tk space on top of the Internet by locating N geographically dispersed servers in the Internet and computing as the coordinate for any computing device on the Internet, its distance to the N servers. The distance is computed as the 4Tk distance which is the time taken by a message of size k to travel between two points at a particular time of day. The system can also be used iteratively where each iteration uses a different set of Slaves in order to close in on the user with finer granularity. Interesting benefits of the system include the difficulty for an attacker to misrepresent the location, and also while the system can hone in on a locale for the user it does not violate the user's privacy.

Abstract: A transmitter has a portion that sets a parameter about the transmitter itself based on a parameter made to correspond to a condition for selecting a receiver with which the transmitter communicate with, a portion that generates a spread code based on the set parameter, and a sending portion that spreads transmit-data to form a spread signal by the generated spread code, and that sends the spread signal. The receiver has a portion that receives the signal transmitted by the transmitter, a portion that sets a parameter about the receiver itself based on the parameter made to correspond to the condition, a portion that generates a despread code based on the set parameter, a portion that performs a correlation computation of the received signal and the generated despread code, and a portion that selects a transmitter with which the receiver communicates, based on a result of the correlation computation.

Abstract: A scalar multiplication unit references a t-bit sequence representing a random number k one bit at a time from the most significant bit, and upon each referencing, sets in a work variable R[0] a value obtained by doubling a specific point G on an elliptic curve set in a scalar multiplication variable R, and sets in a work variable R[1] a value obtained by adding the specific point G to the work variable R[0]. The scalar multiplication unit 122 sets the work variable R[0] in the scalar multiplication variable R if the value of the referenced bit is 0, and sets the work variable R[1] in the scalar multiplication variable R if the value of the referenced bit is 1. A scalar multiple point output unit 123 outputs as a scalar multiple point kG a value obtained by subtracting a constant value 2tG from the scalar multiplication variable R.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: A system and method for parallelization of saturated accumulation is provided. In the method, an input sequence is divided into a plurality of subsequences. For each subsequence, three parallel saturating additions are performed. The local saturation minimum is the saturating addition of the global saturation minimum and the values of the subsequence. The local midpoint is the saturating addition of the values of the subsequence and the local saturation maximum is the saturating addition of the global saturation maximum and the values of the subsequence. In embodiments, the accumulation total for a subsequence is calculated as the saturating addition of the accumulation total for prior subsequences and the local midpoint of the current subsequence, wherein the accumulation total of the last subsequence is the result of the saturated accumulation for the sequence. In another embodiment, the saturated addition of subsequence results are further parallelized before the final result is reached.

Abstract: A method of data processing. The method comprises applying a filter to an input sample set comprising sample values selected from an input sequence of input sample values, so as to generate a corresponding output sample value having an output sample value position with respect to the input sample set, in which the filter has a maximum output range. The method further comprises deriving a permissible output value range from an input group of two or more input sample values in the input sample set which surround the output sample value position, detecting whether the output of the filter is outside the permissible output value range and, if so, limiting the output of the filter to lie within the permissible output value range.

Abstract: In one embodiment, the present invention includes a method for receiving a first and second inputs, calculating a sum/difference of the first and second inputs in parallel with determining a least significant zero (LSZ) vector using the first and second inputs, and determining a shift value based on the LSZ vector, where the shift value is used to perform a shift operation on the sum/difference. Other embodiments are described and claimed.

Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.

Abstract: A mixing system provides both clipping protection and signal level conservation while the system operates in the original width type. The mixing system includes a first input multiplier multiplying a first digital input signal by a first gain value to provide a first scaled signal, a second input multiplier multiplying a second digital input signal by the first gain value to provide a second scaled signal, a combiner combining the first scaled signal and the second scaled signal to provide a combined signal, a soft limiter soft limiting the combined signal by reducing some of the amplitudes of the combined signal to provide a soft limited signal, and an output multiplier multiplying the soft limited signal by a second gain value to provide a mixed output signal, wherein the first gain value is a value that is equal to an inverse value of the second gain value.

Abstract: A method for determining an optimum sampling frequency to be performed by a power analyzer includes the following computer-implemented steps: sampling a time domain signal to obtain a sampling signal according to a predetermined sampling frequency; obtaining two reference sampling signals using higher and lower sampling frequencies compared to the predetermined sampling frequency; transforming the sampling signal and the reference sampling signals to frequency domain signals; computing a sum-of-amplitudes for each of the three frequency domain signals; estimating a minimum sum-of-amplitudes value and a corresponding re-sampling frequency; obtaining a new reference sampling signal using the re-sampling frequency; transforming the new reference sampling signal to a frequency domain signal, and computing a sum-of-amplitudes therefor; and re-estimating the minimum sum-of-amplitudes value and the corresponding re-sampling frequency.

Abstract: A method for deriving a composite tie metric for an edge between nodes of a telecommunication call graph includes receiving descriptive data with original values for descriptive attributes associated with a telecommunication call graph formed by edges between nodes. Each edge relates to two nodes. Each original value relates to an edge and a descriptive attribute forming an edge-attribute pair for the corresponding original value. The descriptive data is stored in a local storage device. Scaling factors for each descriptive attribute are determined taking into account a distribution of the original values for the corresponding descriptive attribute and a common base for the descriptive attributes. Weighting factors are determined for each descriptive attribute. The composite tie metric is computed for an edge based on the original value, scaling factor, and weighting factor for the descriptive attributes.

Abstract: RFID readers, reader systems, and methods are provided that utilize double conversion for received tag response signals. A digitized signal is derived from the tag response signal by first shifting the response signal to about DC. The components of the digitized signal are then up converted and down converted and filtered such that only components around DC remain. The up converted and down converted signals may then be compared and one selected or the two combined after weighting to enhance demodulation and reduce circuit complexity.

Abstract: RFID tags are commanded to generate a pilot tone in their backscatter. When the backscattered pilot tone is received in the reader, the pilot tone is used to estimate the tag period/frequency. Then, the estimate is used to seed and lock a symbol timing recovery loop, which provides a detected signal to one or more correlators for detecting the tag preamble. A delayed version of the received tag signal is compared against a baseline signal threshold established from the received signal to detect the pilot tone.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: The disclosed technology provides a system and a method for scaling parameters in a real-time computation system. A real-time computation system can receive a plurality of input data. The real-time computation system can determine a scaling factor based on an input data, and the scaling factor can be used in connection with a subsequent input data. When a new input data arrives, the real-time computation system can, in parallel, determine a new scaling factor based on the new input data and compute output values based on the existing scaling factor and the new input data. In one aspect of the invention, the real-time computation system can be a statistical signal processing system, which can compute output values, at least in part, using look-up tables.

Abstract: A multi-purpose scaler utilizes a vertical scaler module and a moveable horizontal scaler module to resample a video signal either vertically or horizontally according to a selected scaling ratio. The moveable horizontal scaler module resides in one of two slots within the multi-purpose scaler architecture to provide either horizontal reduction or horizontal expansion as desired. The multi-purpose scaler is arranged to scale the video using non-linear 3 zone scaling in both the vertical and horizontal direction when selected. The multipurpose scaler is arranged to provide vertical keystone correction and vertical height distortion correction when the video is presented through a projector at a non-zero tilt angle. The multi-purpose scaler is also arranged to provide interlacing and de-interlacing of the video frames as necessary.

Abstract: An image processing apparatus includes display means for displaying a zoom image resulting from enlargement of a certain area in an original image to a zoom area; important object determining means for determining whether the absolute value of the difference in pixel value between a pixel on a boundary line, which is the outermost circumference of the zoom area, and the pixel that adjoins the pixel on the boundary line in the direction perpendicular to the boundary line and outward from the zoom area is lower than or equal to a predetermined threshold value to determine whether any important object is across the boundary line; and resetting means for resetting a zoom parameter used for determining the zoom area if the important object determining means determines that any important object is across the boundary line.