Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.

Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimise underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.

Abstract: A method and system to compensate for inaccuracy associated with processing values with finite precision includes a process for selecting a display value whereby an initial value is provided in a first numbering system. The initial value is then converted into an equivalent stored value in a second numbering system. Then a display value in the first numbering system is determined and selected such that the selected display value includes the least number of significant digits that convert from the first numbering system to the second numbering system exactly as the stored value. The selected display value in the first numbering system is then used for display and/or further processing when the stored value in the second numbering system is recalled.

Abstract: A method for displaying images in a display apparatus is provided herein. In the display apparatus, an image is displayed during each frame period of a plurality of contiguous frames. At first, original images are received, and each of the received original images is composed of M number of contiguous image rows. A predetermined amount of frame periods are grouped as a frame group. During each frame period, one of M number of image rows is selected as an initial image row. From the initial image row, N number of image rows are selected from the M number of image rows according to an image row selection rule to constitute an image for displaying. In each frame group, at least two different initial parameters are used within two frame periods in order to output different images.

Abstract: Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of ?1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.

Abstract: There are provided a computation method for scalar multiplication or exponentiation and a scalar multiplication program or an exponentiation program which can compute at high speed. In the computation method for scalar multiplication and the scalar multiplication program for computing scalar multiplication by n of a rational point Q in G with respect to a non-negative integer n using an electronic computer, since ?q(Q)=[q]Q=[t?1]Q holds true with respect to the rational point Q in G, (t?1)-adic expansion of a scalar n is performed and a Frobenius endomorphism ?q with respect to a rational point is used in place of t?1.

Abstract: A method and system for scaled exponential smoothing are provided. Multiple exponentially smoothed values are maintained for items and events occur on one or more of the items. The method maintains a gradually inflated representation of the smoothed values of items, such that the representation at a given time for an item where no event has occurred is not altered. Using a scaling technique enables the smoothed values for the objects on which an event has not occurred to remain the same. This reduces the number of calculations required significantly, enabling the use of the smoothing technique in a wide range of applications.

Abstract: A multi-purpose scaler utilizes a vertical scaler module and a moveable horizontal scaler module to resample a video signal either vertically or horizontally according to a selected scaling ratio. The moveable horizontal scaler module resides in one of two slots within the multi-purpose scaler architecture to provide either horizontal reduction or horizontal expansion as desired. The multi-purpose scaler is arranged to scale the video using non-linear 3 zone scaling in both the vertical and horizontal direction when selected. The multi-purpose scaler is arranged to provide vertical keystone correction and vertical height distortion correction when the video is presented through a projector at a non-zero tilt angle. The multi-purpose scaler is also arranged to provide interlacing and de-interlacing of the video frames as necessary.

Abstract: A computer implemented method for maintaining synchronization between a master computer disk and a clone disk that includes cloning the clone disk from the master computer disk, the clone disk having a customization portion; and customizing the customization portion with information relevant to a clone computer that uses the clone disk.

Abstract: A two-plane rotation (TPR) approach to Gaussian elimination (Jacobi) is used for computational efficiency in determining rotation parameters. A rotation processor is constructed using the TPR approach to perform singular value decomposition (SVD) on two by two matrices yielding both eigenvalues and left and right eigenvectors. The rotation processor can then be replicated and interconnected to achieve higher dimensioned matrices. For higher dimensional matrices, the rotation processors on the diagonal solve the 2×2 rotation angles, broadcast the results to off-diagonal processors, whereby all processors perform matrix rotations in parallel.

Abstract: A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value for K. In a hardware circuit area, the value X is shifted sv digits to the left in the case of multiplication or sv digits to the right in the case of division. The software circuit area calculates a suitable correction factor Kf. The value X is multiplied by the correction factor Kf.

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: A method and method and apparatus for data re-arrangement includes the steps of receiving output pixel coordinates (X, Y) and obtaining an input pixel offset value (?S, ?T), wherein the output pixel coordinate represents a location for a two dimensional matrix. The input pixel offset value is obtained in reference to initial input pixel coordinates (S, T) which may be received with the output pixel coordinates or calculated based on the input and/or output pixel coordinates. The input pixel offset value may be any type of representation that provides for a delta value, for example, (?S, ?T) may represent a shift representation for the offset within a matrix array. The method and apparatus for data re-arrangement further includes retrieving an input pixel based on the initial input pixel coordinates and the offset value.

Abstract: Methods and apparatus, including computer systems and program products, for normalizing computer-represented collections of objects. A first minimum value can be normalized based on a second minimum value of a universal set object that corresponds to the first set object. The second minimum value is both a minimum value supported by a data type (e.g., 1-byte integer) and a minimum value defined to be in the universal set object (e.g., 0 for a universal set of all natural numbers). Similarly, a first maximum value can be normalized based on a second maximum value of the universal set object where the second maximum value is both a maximum value supported by a data type and in the universal set object. Intervals can be normalized, which can involve replacing half-open intervals with equivalent half-closed intervals. Also, a consecutively ordered, uninterrupted, sequence of values of a set object can be normalized.

Abstract: To provide a determination apparatus and a determination method which are capable of determining whether a signal outputted from a testing object is good or not, a Cyclic Redundancy Check (CRC) calculation circuit unit performs calculation on an image signal and a determination circuit unit compares a calculation result obtained by the CRC calculation circuit unit with an expected value stored in an expected value storing unit to determine whether a quality of the image signal is good or not.

Abstract: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.

Abstract: A method, system and computer program product for computationally efficient estimation of the scale factors of one or more frequency bands in an encoder. These scale factors are dependant on a plurality of variables. One of the variables is approximated according to embodiments of the invention. This reduces the complexity of the estimation of scale factors, especially in digital signal processors.

Abstract: An image conversion apparatus for geometrically converting input image data and outputting output image data, includes an inverse coordinate conversion unit configured to inversely convert coordinate values on the coordinate system of the output image data into coordinate values on the coordinate system of the input image data based on the geometric conversion. When a region between neighboring pixels of the coordinate system of the input image data is divided into a plurality of divisions, the inverse coordinate conversion unit changes the inversely converted coordinate values so that coordinate values which belong to an identical division of the inversely converted coordinate values have a random two-dimensional array.

Abstract: The present invention uses a computer analysis system of a fast singular value decomposition to overcome the bottleneck of a traditional singular value decomposition that takes much computing time for decomposing a huge number of objects, and the invention can also process a matrix in any form without being limited to symmetric matrixes only. The decomposition and subgroup concept of the fast singular value decomposition works together with the decomposition of a variance matrix and the adjustment of an average vector of a column vector are used for optimizing the singular value decomposition to improve the overall computing speed of the computer analysis system.

Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.

Abstract: A method is proposed which enables high-resolution raster images to be represented on lower-resolution displays. The method according to the invention selects support points in lines and columns of the original image, which have a smallest possible variation of their distances and approximate the set scaling at least in ranges. Consequently, rational scaling ratios can also be achieved in an advantageous manner. In order to represent fine details of the original image in the scaled image as well, the adjacent pixels of the support points are also incorporated into the calculation of the pixels that are output. Furthermore, a circuit for scaling a raster image in real time is proposed. Moreover, a film scanner having a scaling device in accordance with the method according to the invention is proposed.

Abstract: A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.

Abstract: A review system and method gathers and analyzes data related to ownership of and encumbrances on intellectual property assets from relevant recordation locations. The system and method analyzes the data and interprets the data and the chain of ownership of intellectual property assets.

Abstract: A computer implemented method for at least one of grading, measuring, classifying entities and/or ranking entities, and/or designating a winner among entities, with each entity assigned n grades of an ordered language of evaluation, where n is an integer greater than 1, may comprise sorting the grades assigned each entity according to a first ordering rule to obtain a first list of ordered grades. For i=1, . . . , n, generating for each entity a second list of ordered grades from the first list by assigning all ith grade of the first list to a place in the second list according to a second ordering rule, and at least one of assigning a first grade of an entity's second list to that entity, ranking the entities based on comparisons of the second lists, designating the winner among the entities as the one that is the first in the ranking, and classifying the entities based on the second lists.

Abstract: A data processing apparatus for scaling a digital data source is provided. The data processing apparatus includes a ratio transformation module and a scaling module. The ratio transformation module receives a ratio signal and generates a Look-up Table (LUT). The scaling module connected to the ratio transformation module receives the digital data source, scales the digital data source based on the LUT, and then outputs a processed digital data.

Abstract: A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where a value different from a sign bit first appears, a mantissa obtaining unit obtaining information of 1-bit or a plurality of bits in a position next to the exponent as a mantissa out of the external information, a storage unit storing the exponent and the mantissa and a restoring unit restoring the external information by reading the exponent and the mantissa stored in the storage unit, wherein the element decoding unit performs iteration decoding based on the restored external information is utilized.

Abstract: A system and method for automatically generating a computation mesh for use with an analytical tool, the computation mesh having a plurality of ?-grid lines and ?-grid lines intersecting at grid points positioned with respect to an inner boundary and an outer boundary. The system and method include one or more mesh equations having one or more source terms that include: a grid clustering component based on a Jacobian scaling parameter, a source decay parameter, and one or more first point distance parameters, and a cell shape modifying source component based on one or more source parameters selected from the group consisting of a smoothing source parameter, an area source parameter, an orthagonality source parameter, and any combinations thereof.

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Abstract: A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for converting the 16-bit floating point number into a representative native floating point value. Thereafter, the native microprocessor floating point instruction set may perform operations upon the converted data. Upon completion, the native floating point data representation may be converted back into the 16-bit floating point value.

Abstract: A method for improving precision in FFT calculations. For each iteration in an FFT implementation, a constant normalization multiplier is inserted such that the dynamic ranges of the input and output are the same. The final FFT output is multiplied by a constant normalization factor given by the number of iterations and the constant normalization multiplier.

Abstract: A circuit for computing moment pre-products for statistical analysis reduces data transfer volume for on-chip statistical measurements. The circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from a wafer. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. The circuit can use look-up tables and adder/accumulators to accumulate the contributions of each measurement to each exponentiation, or use a multiplier arrangement to determine the contributions. The multipliers can be implemented in the adder/accumulators by clocking the adder/accumulators by corresponding counts determined from the measurement data and lower-order exponentiations. Ranges of the measurement values are determined by capturing maximum and minimum values using comparators as the measurements are input.

Abstract: A method for image scaling. Specifically, one embodiment of the present invention discloses a method for image scaling that begins by selecting an input pixel from a first image. An input edge characteristic is determined from an input window associated with the input pixel. The input edge characteristic is determined from a plurality of predetermined edge characteristics that are associated with sets of filter coefficient vectors. An output window is generated by filtering the input window with a corresponding set of filter coefficients associated with the input edge characteristic. An output image is generated by repeating the above for a plurality of input pixels associated with the first image.

Abstract: An apparatus which processes a digital image and a method therefor which can reduce an error when calculating an output value obtained by interpolating pixel values of the input digital image. The apparatus includes an interpolation processing unit which interpolates an input digital image, and a controller which measures an interpolation interval of pixel values of the digital image, calculates a coefficient by substituting the interpolation interval for a coefficient equation stored in a register, and calculates an interpolation node for the digital image by substituting the coefficient and an output pixel position value of the digital image for an interpolation node calculation equation. The controller controls the interpolation processing unit so as to interpolate the digital image to the interpolation node. As a result, it is possible to reduce an error between an interpolated output pixel position value and an output pixel position value for the pixel values of the input digital image.

Abstract: In a picture enlarging processing employing a MAP method, the processing volume is to be decreased to obtain a clear picture without producing blocked distortion without deteriorating the picture quality from that in the conventional practice. An energy function of a picture varied in dependence upon the input picture is defined in advance and stored. An input picture is enlarged, that is the number of pixels is increased, and a value which decreases the energy in a pixel of the enlarged picture is calculated. This energy decreasing value is added to the pixel and the pixel value is updated to adjust the picture quality to raise the resolution. The pixel value is updated a number of times to adjust the picture quality to raise the resolution.

Abstract: In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value if the input is within a first input range. The scale and bias unit also includes a processing unit coupled to the preclamping unit and configured to perform a calculation on the input to generate the output value. The processing unit does not perform the calculation if the input is within the first input range.

Abstract: A method, by a processing device, for scaling an M-bit integer input vector containing one or more vector elements. The method comprises receiving a maximum permitted left shift (MLS) value for the input vector, said MLS value being less than or equal to M−2; determining a minimum left shift (NLS_MIN) for scaling said vector element with the largest magnitude; employing said NLS_MIN value to determine whether said input vector is a zero input vector, or a non-zero input vector irrespective of the positive or negative value of the largest element values of said non-zero input vector; if a non-zero input vector is determined, offsetting said NLS_MIN value by said MLS value to obtain an actual number of left shifts (NLS) value for scaling said input vector; and if a zero input vector is determined, offsetting said NLS_MIN value by said MLS value to obtain the NLS value.

Abstract: A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating-point system. Each piece of data of a data group is calculated, the minimum scale factor representative of the calculated data is detected as a group scale factor (GSF), and calculated data is subjected to scaling based on the detected GSFs. These processing are applied to each data group of a data block. The minimum GSF out of the detected GSFs is detected as a block scale factor (BSF). When calculation of the calculated data is performed again, the calculated data of the data group is subjected to scaling according to the GSFs and BSF before the calculation performed again.

Abstract: A method for scaling a signal sample rate includes interpolating between at least two scaling ratios to calculate an arbitrary scaling ratio, using a predetermined interpolation algorithm, and scaling a sample rate for a first portion of the signal using a first scaling ratio, and scaling a sample rate for a second portion of the signal using a second scaling ratio, to form a scaled signal having an average scaling ratio equal to the arbitrary scaling ratio.

Abstract: A technique for identifying the encoding law utilized by a central office codec may be implemented in a receive modem. The encoding law, which is typically dictated by the country in which the central office is located, is employed to generate a plurality of transmission levels during an initialization period associated with the modem system. The receive modem analyzes a number of these transmission levels to determine whether the levels have certain characteristics associated with the particular encoding law followed by the central office codec. When the receive modem detects the codec type, it may transmit a suitable identifier back to the transmit modem.

Abstract: A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central processing unit having a converter unit and a set of conversion registers. The load/store instructions having data requiring conversion include an index field for identifying one of the conversion registers. Each one of the conversion registers includes information on the type of conversion required and any scaling factors to be applied. Upon receiving one of these instructions, the converter uses the identified conversion register to perform the conversion and stores the converted data into the corresponding register or memory location.

Abstract: There is disclosed a resolution conversion apparatus for converting an original digital image into a digital image having a different number of pixels in accordance with an instructed conversion magnification factor. In the apparatus, a determination circuit determines the number of pixels to be interpolated in each block of the original image and positions where they are interpolated in accordance with the conversion magnification factor. The block includes a predetermined number of pixels of the original image. A converted image generation circuit generates pixel data for the interpolation pixels at the positions where they are interpolated in accordance with a predetermined interpolation equation whose coefficients are determined with the positions and data values of the pixels in the block, and combines the pixel data for the digital original image and the generated pixel data to output a converted digital image. The interpolation equation includes spline functions and Bezier functions.

Abstract: Lighting parameters are received as floating-point numbers from a software application via an application programming interface (API). The floating-point numbers are converted to a fixed-point representation having a preselected number of bits. The number of bits is selected in accordance with a predetermined number of bits required by a frame buffer, which thus establishes the number of color values supported by the graphics display system. In order to preserve accuracy to within the number of bits in each value in the frame buffer, the representation in the fixed-point engine includes additional bits relative to the number of bits in the color values sent to the frame buffer. Floating-point values received via the graphics API are converted to fixed-point representations by first prescaling the floating-point values.

Abstract: A method, by a processing device, for scaling an M-bit integer input vector containing one or more vector elements. The method comprises receiving a maximum permitted left shift (MLS) value for the input vector, said MLS value being less than or equal to M−2; determining a minimum left shift (NLS_MIN) for scaling said vector element with the largest magnitude; employing said NLS_MIN value to determine whether said input vector is a zero input vector, or a non-zero input vector irrespective of the positive or negative value of the largest element values of said non-zero input vector; if a non-zero input vector is determined, offsetting said NLS_MIN value by said MLS value to obtain an actual number of left shifts (NLS) value for scaling said input vector; and if a zero input vector is determined, offsetting said NLS_MIN value by said MLS value to obtain the NLS value.

Abstract: A method and a device for high-speed scale conversion wherein a value N within a range of N1 and N2 is converted into a small value M within a range of M1 and M2. The method includes the step of obtaining an approximate value of M by loading the value (N−N1+2p−1) into a multi-bit shift register and right-shifting p bits. A binary search process is then used to determine the error value between the actual value of M and the approximate value of M. By avoiding actual multiplication processes, the conversion can be carried out using low-cost electronic hardware such as a microprocessor or a PROM to carry out the binary search process, a shift-register to obtain the approximate value of M, a multiplexer to receive an analog input data N and an A/D converter to convert the analog input data N into a digital data N.

Abstract: There is disclosed a resolution conversion apparatus for converting an original digital image into a digital image having a different number of pixels in accordance with an instructed conversion magnification factor. In the apparatus, a determination circuit determines the number of pixels to be interpolated in each block of the original image and positions where they are interpolated in accordance with the conversion magnification factor. The block includes a predetermined number of pixels of the original image. A converted image generation circuit generates pixel data for the interpolation pixels at the positions where they are interpolated in accordance with a predetermined interpolation equation whose coefficients are determined with the positions and data values of the pixels in the block, and combines the pixel data for the digital original image and the generated pixel data to output a converted digital image. The interpolation equation includes spline functions and Bezier functions.

Abstract: A method of determining the scaling factor for a signed n bit binary number, where n=2e, includes the steps of dividing the number into a plurality of subgroups of at least two bits each; providing a plurality of subunits holding the respective subgroups of bits; and arranging the subunits in a hierarchical tree structure of units. Each unit of a superior level receives inputs from units of a lower level, and each unit produces first, second and third output signals. The first output signal represents the most significant bit of the units in the associated hierarchy, the second signal indicates whether the bits in the associated hierarchy have the same value, and the third signal is an i-bit number representing the number of places less one that the bits in the associated hierarchy can be shifted. The index i is the same as the associated level in the hierarchy.

Abstract: A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.

Abstract: A comb filter is provided for achieving substantial attenuation of aliasing or imaging bans of a signal to be filtered. The comb filter can perform decimation or interpolation, depending upon its application. Integration can include an integration term with adjustable voltage accumulation at a particular sample point in time. The accumulation factor can be an integer or fractional number and is introduced at a sample count value L within each of M number of samples formed by the rate change switch within the comb filter. The amount of gain being introduced can possibly vary depending on the number of accumulation cycles programmed within configuration registers of the digital signal processor which carries out the comb filter functions. The programmable accumulator avoids having to implement a multiplication operation and the complexities associated therewith.

Abstract: A method for bit-depth increasing digital data represented by a first number of original bits which are sequentially ordered beginning with a start bit and ending with an end bit. To bit-depth increase the data, in an expanded presentation, the original bits are replicated in the sequential order starting with the start bit to form replication bits. The original bits are appended with a second number of the replication bits to form the expanded presentation of the digital data. The appended replication bits start with the start bit and are in the sequential order of the original bits.