Abstract: The present disclosure is directed to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.

Abstract: An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

Abstract: The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.

Abstract: In an embodiment, a method comprises: receiving, by a mechanical offset controller, input data; detecting, by the mechanical offset controller, a waveform command in the input data; responsive to the detecting, generating, by the mechanical offset controller, an unparking command; receiving, by a closed-loop controller, the unparking command; and moving, by the closed-loop controller, a mass in a haptic module from a mechanical resting position to a sensor reference position in accordance with the unparking command. The method further comprises: detecting, by the mechanical offset controller, that the input data does not include the waveform command; responsive to the detecting, generating, by the mechanical offset controller, a parking command; receiving, by a closed-loop controller, the parking command; and moving, by the closed-loop controller, the mass in the haptic module from the sensor reference position to the mechanical resting position in accordance with the parking command.

Abstract: The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.

Abstract: Instructions and logic provide SIMD vector population count functionality. Some embodiments store in each data field of a portion of n data fields of a vector register or memory vector, at least two bits of data. In a processor, a SIMD instruction for a vector population count is executed, such that for that portion of the n data fields in the vector register or memory vector, the occurrences of binary values equal to each of a first one or more predetermined binary values, are counted and the counted occurrences are stored, in a portion of a destination register corresponding to the portion of the n data fields in the vector register or memory vector, as a first one or more counts corresponding to the first one or more predetermined binary values.

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Abstract: A method for transmitting a codeword in a wireless communication system is disclosed. The method includes generating a codeword by encoding an input signal based on a polar code, acquiring a Hamming weight from a bit sequence of at least a part of the codeword, generating Hamming weight information based on the Hamming weight, and transmitting the Hamming weight information and the codeword to a receiver. The Hamming weight information includes a range indicator indicating a range to which the Hamming weight belongs, among a plurality of ranges.

Abstract: The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

Abstract: Instructions and logic provide SIMD vector packed histogram functionality. Some processor embodiments include first and second registers storing, in each of a plurality of data fields of a register lane portion, corresponding elements of a first and of a second data type, respectively. A decode stage decodes an instruction for SIMD vector packed histograms. One or more execution units, compare each element of the first data type, in the first register lane portion, with a range specified by the instruction. For any elements of the first register portion in said range, corresponding elements of the second data type, from the second register portion, are added into one of a plurality data fields of a destination register lane portion, selected according to the value of its corresponding element of the first data type, to generate packed weighted histograms for each destination register lane portion.

Abstract: An apparatus for providing improved data compression may include an encoder comprising a quantizer for encoding input data and a side model. The quantizer may be trained with respect to high priority data among the input data and may be configured to partially encode the input data by encoding the high priority data. The side model may be trained jointly with the training of the quantizer and is configured to model low priority data among the input data.

Abstract: Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.

Abstract: A parallel counter accesses data generated by an application and stored within a register. The register includes different segments that include different portions of the application data. The parallel counter is configured to count the number of values within each segment that have a particular characteristic in a parallel fashion. The parallel counter may then return the individual segment counts to the application, or combine those segment counts and return a register count to the application. Advantageously, applications that rely on population count operations may be accelerated. Further, increasing the number of segments in a given register may reduce the time needed to count the values in that register, thereby providing a scalable solution to population counting. Additionally, the architecture of the parallel counter is sufficiently flexible to allow both register counting and segment counting, thereby combining two separate functionalities into just one hardware unit.

Abstract: The present disclosure describes systems and techniques relating to calculation of array statistics. According to an aspect of the described systems and techniques, a device includes: a memory configured to store a data array and a counter array, wherein the data array includes multiple values, and each of the multiple values is encoded in a respective row of the data array, and wherein the counter array includes multiple counters, respective columns of the counter array correspond to respective ones of the counters, and rows of the counter array correspond with bit significance positions spanning the multiple counters; and processor electronics configured to add up a number bits found in respective columns of the data array using respective ones of the multiple counters.

Abstract: Methods, systems, and computer readable media for selecting numbers from multiple ranges are disclosed. One method includes receiving, information associated with a plurality of ranges, selecting, by a module implemented using a non-transitory computer readable medium, iteratively selecting numbers from within the ranges such that, during a selection iteration, a given number within one of the ranges is not selected more than once and such that a sequence of numbers selected during the selection iteration appears to be random, and utilizing the numbers selected during the selection iteration to control at least one aspect of testing a network or storage device.

Abstract: A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string.

Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M?N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

Abstract: Counting the number of set and unset bits in an n-bit data word or stream of data is most efficient in applications where the data can be characterized as sparsely populated (bits mostly or all unset/0) and/or heavily populated (bits mostly or all set/1). In these populations, processing can be linearly proportional to the smaller number of differing bit values resulting in compute time and resource savings. In any population, the operations of the bit counting methods, systems, apparata and computer program products described are bounded by the number of bits counted in the data word/stream. The described operations can be used for determining whether further processing of the data stream is required as well as the extent of that processing.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: A random number generator device that utilizes a magnetic tunnel junction. An AC current source is in electrical connection to the magnetic tunnel junction to provide an AC current having an amplitude and a frequency through the free layer of the magnetic tunnel junction, the AC current configured to switch the magnetization orientation of the free layer via thermal magnetization. A read circuit is used to determine the relative orientation of the free layer magnetization in relation to the reference layer magnetization orientation.

Abstract: In one embodiment, the present invention includes a method for receiving a first and second inputs, calculating a sum/difference of the first and second inputs in parallel with determining a least significant zero (LSZ) vector using the first and second inputs, and determining a shift value based on the LSZ vector, where the shift value is used to perform a shift operation on the sum/difference. Other embodiments are described and claimed.

Abstract: An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector.

Abstract: A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).

Abstract: The present invention provides method and apparatus of a fast DCT implementation. DCT calculation is combined with quantization scales by a procedure of pre-processing. During DCT coefficient calculation, only non-zero coefficients are calculated. If pixel variance range is smaller than a first predetermined threshold, a predetermined lookup table is compared to decide the DCT coefficients. When a pixel variance range of a block pixels is within the second threshold, coupled with the quantization scales, the pre-processing determines the amount of non-zero DCT coefficients need to be calculated. Only a limited amount of LSB bits within a block is applied in the calculation of DCT coefficients. A previously saved pixel with equal or closest pixel value is used to replace the operation of current pixel's multiplication.

Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N?1:0] and a second N-bit vector B[N?1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N?1:0] & ˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N?1:0]^˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. The difference between the first N-bit vector A[N?1:0] and the second N-bit vector B[N?1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m<n) based on bit patterns in the third N-bit vector and the fourth N-bit vector.

Abstract: Counting the number of set and unset bits in an n-bit data word or stream of data is most efficient in applications where the data can be characterized as sparsely populated (bits mostly or all unset/0) and/or heavily populated (bits mostly or all set/1). In these populations, processing can be linearly proportional to the smaller number of differing bit values resulting in compute time and resource savings. In any population, the operations of the bit counting methods, systems, apparata and computer program products described are bounded by the number of bits counted in the data word/stream. The described operations can be used for determining whether further processing of the data stream is required as well as the extent of that processing.

Abstract: In one embodiment, a state determiner comprises a plurality of logic circuits and a second logic circuit. Each logic circuit corresponds to a respective bit position of a result of an adder. A first logic circuit corresponds to a least significant bit of the result and is coupled to receive a least significant bit of each operand of the adder and a carry-in input to the adder. Each remaining logic circuit is coupled to receive a bit from the respective bit position of each operand and a less significant bit adjacent to the bit of each operand. Each logic circuit generates an output signal indicative of whether or not a specific result occurs in the respective bit position of the result. Coupled to receive the output signals second logic circuit is configured to generate a sum signal indicative, when asserted, that the specific result occurs.

Abstract: An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data input terminals, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A DBI determining unit determines a logic value of each of the data according to the sums and the carries that are transmitted from the full adder and the half adder, thereby outputting a DBI signal.

Abstract: A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits.

Abstract: A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.

Abstract: A circuit includes a plurality of selection circuits. Each of the plurality of selection circuits has a first input, a second input, a control input, and an output. Each of the first inputs receives one of a plurality of correlated signals. Each of the second inputs receives one of a plurality of uncorrelated signals. Each of the control inputs receives a correlation mode control signal, and each of the outputs provides the one of the plurality of correlated signals or the one of the plurality of uncorrelated signals based on the correlation mode control signal. The circuit further includes a population count circuit having a plurality of data inputs coupled to receive the outputs of the plurality of selection circuits. The population count circuit provides a population count for the plurality of data inputs. The population count may be an approximate count or an accurate count.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: The present application addresses a fundamental problem in the design of computing systems, that of minimising the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.

Abstract: A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).

Abstract: Generating a number based on mask and range constraints. For example, a method of generating a pseudo random number satisfying a range constraint and a mask constraint may include determining a number of possible solutions satisfying the range constraint and the mask constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo random number based on the index. Other embodiments are described and claimed.

Abstract: For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

Abstract: Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order.

Abstract: A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits.

Abstract: A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.

Abstract: Under block-aware encoding, a bitmap represented by atoms comprises a series of bitmaps for each data block in a database. Each bitmap in the series is referred to herein as a block bitmap. Each block bitmap may have a different number of bytes or bits. Gaps are represented in atoms using a pair of numbers referred to as a gap code. A gap code includes a block-skip code and slot-skip code. A block-skip code represents how many block bitmaps to advance to reach a subsequent block bitmap; a slot-skip code represents how many bytes to advance within the block bitmap to reach a byte with at least one bit set. A gap code is represented by bit positions within a byte, with some bit positions allocated to represent the block-skip code and some to represent the slot-skip code. The allocation is adjusted dynamically during encoding and decoding.

Abstract: A method of dividing an information bit string by a generator polynomial includes dividing the information bit string into a plurality of sub-bit strings A1 through AN, multiplying a remainder value by each bit of a sub-bit string Ai (1?i?N) successively with a most significant bit first so as to produce a multiplication result corresponding to the sub-bit string Ai, the remainder value being obtained by dividing a polynomial representation by the generator polynomial wherein the polynomial representation represents a bit string in which a bit position in the information bit string corresponding to a least significant bit of the sub-bit string Ai is set to “1” and remaining bit positions are set to “0”, and dividing, by the generator polynomial, a polynomial representing a bit string obtained by performing modulo-2 addition that adds up multiplication results corresponding to the sub-bit strings A1 through AN.

Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: Methods and apparatus for finding a match between a target bit pattern and multiple filter bit patterns. A filter array is created from the filter bit patterns and at least one intermediate array is generated from the filter array. Specific columns of the intermediate arrays are then extracted based on bit values of the target bit pattern. A row by row AND operation is performed on these columns to arrive at a match vector. the match vector identifies which of the filter bit patterns in the filter array match the target bit pattern. The method is implemented by using multiple classifier elements operating in parallel with each classifier element handling multiple filter bit patterns.

Abstract: A method and system for identifying a bit pattern in a data stream including a plurality of bits each having a first or second state, the method includes identifying a number of mismatching bits, within a subset of the plurality of bits, having the first state and corresponding to a bit having the second state within the pattern; identifying a number of bits in the subset having the first state; and, identifying a number of bits in the pattern having the second state. A number of matches of between the subset and the pattern is dependent on the identified number of mismatching bits, the identified number of bits in the subset having the first state and the identified number of bits in the pattern having the second state.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.

Abstract: One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.