Abstract: Systems and methods are described for controlling or monitoring a wide variety of target hardware, which may use various interfaces and protocols, via non-customized software, without requiring additional software to interface between the non-customized software and the target hardware. An application repository can include a variety of software applications available to end users. An end user may request one or more such applications, and specify target hardware controlled or monitored by the applications. The app repository can then generate a hardware configuration template, corresponding to a configuration of a field-programmable hardware layer on a bridge device of the end user, which routes data between inputs and outputs of the target hardware and a memory on the bridge device. The template and applications can then be provisioned on the bridge device, such that the applications can execute to control and monitor the target hardware via interaction with the memory.

Abstract: Methods, systems and apparatus for performing indexed operations using a unary iteration quantum circuit. In one aspect, a method includes encoding an index value in an index register comprising index qubits; encoding the index value in a control register comprising multiple control qubits; and repeatedly computing and uncomputing the control qubits to perform, conditioned on the state of the control qubits, the operation on one or more target qubits corresponding to the index value, wherein during the encoding, computing and uncomputing: the multiple control qubits are made available in sequence, and the multiple control qubits correspond to a one-hot encoding of the encoded index value.

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements.

Abstract: Methods, systems and apparatus for performing indexed operations using a unary iteration quantum circuit. In one aspect, a method includes encoding an index value in an index register comprising index qubits; encoding the index value in a control register comprising multiple control qubits; and repeatedly computing and uncomputing the control qubits to perform, conditioned on the state of the control qubits, the operation on one or more target qubits corresponding to the index value, wherein during the encoding, computing and uncomputing: the multiple control qubits are made available in sequence, and the multiple control qubits correspond to a one-hot encoding of the encoded index value.

Abstract: Mapping of logical qubits to physical qubits is provided. In various embodiments, a first candidate subgraph is selected from a hardware graph. The hardware graph represents a physical quantum circuit. The hardware graph comprises a plurality of nodes corresponding to physical qubits and a plurality of edges corresponding to coupling among the plurality of qubits.

Abstract: A microcontroller is capable of executing a process that is parameterizable by at least one parameter. The microcontroller includes a processor and a hardware module coupled to the processor. The hardware module is configured to hardware execute the process and the processor is configured to deliver the at least one parameter to the hardware module.

Abstract: A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent operations. Where the hints are more likely than not to be correct, the processing unit operates more efficiently. For example, in an embodiment, the processing unit consumes less power. In another embodiment, subsequent operations are performed more quickly because the processing unit is prepared to efficiently handle the subsequent operations.

Abstract: A first evaluation function calculation unit and a second evaluation function calculation unit calculate a cost function term Ei and a penalty function term Pi in an evaluation function, respectively. A transition control unit stochastically determines whether to accept any of state transitions, based on a product of a ratio between an inverse temperature ?i and a penalty factor ?i and Pi and Ei. An exchange control unit supplies ?i and ?i to each annealing unit, ?i and ?i having been set such that each annealing unit has a different ratio between ?i and ?i, receives Ei and Pi from each annealing unit, and exchanges ?i between first and second annealing units among the plurality of annealing units and ?i between the first and second annealing units, in accordance with a probability based on ?i, ?i, Ei, and Pi of the first and second annealing units.

Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Abstract: Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits matrix decomposition operations into parallel operation circuits and serial operation circuits, and joins the parallel and serial operation circuits using specific dependency handling logic for efficient parallel execution. This provides fast matrix decomposition with low power consumption, reduced memory footprint, and reduced memory bandwidth.

Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

Abstract: Methods and circuits are disclosed for configuring an integrated circuit (IC) to implement a system design. In an example implementation, boot ROM code is executed on the processor circuit. The execution of the boot ROM code causes the processor circuit to determine settings used by the system design for communicating data via a communication circuit on the IC. The communication circuit is configured by the processor circuit according to the determined settings. In response to receiving one or more boot images by the processor circuit, via the configured communication circuit configured according to the determined settings, boot images are executed by the processor circuit. The execution of the boot images causes the processor circuit to configure the IC to implement the system design. During operation of the system design on the IC, data is communicated via the communication circuit configured according to the determined settings.

Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline includes an instruction fetch stage to fetch an instruction. The instruction format of the instruction specifies a first input vector, a second input vector and a third input operand. The instruction execution pipeline comprises an instruction decode stage to decode the instruction. The instruction execution pipeline includes a functional unit to execute the instruction. The functional unit includes a routing network to route a first contiguous group of elements from a first end of one of the input vectors to a second end of the instruction's resultant vector, and, route a second contiguous group of elements from a second end of the other of the input vectors to a first end of the instruction's resultant vector. The first and second ends are opposite vector ends. The first and second groups of contiguous elements are defined from the third input operand.

Abstract: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: A method determines a schedule indicator value for each of a plurality of schedule data entries based on whether each of a set of recorded tasks has been allocated to one or more identifier data names in one or more of a set of time periods in accordance with the first schedule data to generate schedule portion data. A hard constraint indicator value is determined for each of a plurality of hard constraint data entries based on whether at least one hard constraint has been violated by the allocation of the set of recorded tasks to one or more of the identifier data names in one or more of the time periods in accordance with the schedule data to generate hard constraint portion data. The data structure is generated based on the determined schedule portion and hard constraint portion data encoding the schedule data into a data structure.

Abstract: An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.

Abstract: Example apparatus and methods selectively generate and store erasure codes differently based on priorities associated with the erasure codes or based on conditions in a data storage system (DSS) that protects messages using erasure codes. Producing a systematic erasure code (EC) may be prioritized over producing a non-systematic EC. Producing an EC associated with correcting X erasures may be prioritized over producing an EC associated with correcting Y erasures, X and Y being numbers, X<Y. The priorities may depend on conditions in the DSS including an erasure code A/B policy, numbers of errors experienced by the DSS, types of errors experienced by the DSS, frequency of errors, an amount of power required to store or retrieve an EC in the DSS, or a network bandwidth required to store or retrieve an EC in the DSS. The priorities may be user configurable or self-adapting.

Abstract: A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed.

Abstract: The present invention relates to technical solutions for allocating FPGA resources in a resource pool. In an embodiment, the technical solution includes: receiving resource request for FPGA resources in the resource pool from a client; performing resource allocation operation based on resource pool state information record in response to the resource request, said resource pool state information record including utilization state information of the FPGA in said resource pool; and updating said resource pool state information record based on the result of said resource allocation operation. FPGA resource allocation can be implemented with the adoption of the technical solution of the application.

Abstract: Provided are an apparatus and method for performing a complex number operation using a Single Instruction Multiple Data (SIMD) architecture. A SIMD operation apparatus may perform, in parallel, a real part operation and an imaginary part operation of a plurality of complex numbers. The real part operation and the imaginary part operation may be performed sequentially, or in parallel.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/von Neumann Paradigm in which data are provided to circuitry that would operate on those data is reversed by structuring the desired circuits at the site(s) of the data, thereby to eliminate the von Neumann bottleneck and substantially increase the computing power of the device, with the apparatus conducting only non-stop Information Processing on a steady stream of data and code, with no repetitious Instruction and data transfers as in the normal computer being required. A code is defined that will identify the physical locations of every transistor in the processing space, which code will then enable only selected ones of the pass transistors therein so as to structure the circuits needed for any algorithm sought to be executed.

Abstract: Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, where each of the input operands is of a corresponding precision. The adaptive conversion logic also records the corresponding precision for use in subsequent floating point operations. The tagged register file is coupled to the adaptive conversion logic. The tagged register file stores the each of the input operands, and stores the corresponding precision and furthermore associates the corresponding precision with the each of the input operands. The subsequent floating point operations are performed at a precision level according to the corresponding precision.

Abstract: A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|(rs2 [0]<<63) and a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? 1.0: rs1)?(rs2 [1]<<63), or a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|((˜rs2 [0]<<63) and a fourth trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? rs1: 1.0)?((rs2 [1]?rs2 [0])<<63)).

Abstract: A method and apparatus for decoding digital quadrature phase shift keying data includes converting and intermediate frequency signal from an analog signal to a digital signal and digitally processing the digital signal to detect and decode the digital quadrature phase shift keying and extract encoded data.

Abstract: A microprocessor has an instruction decode portion, a register file, a complex operation unit, and a data storage position determining mechanism. The complex operation unit performs complex operation, including complex multiplication, using first and second complex number data supplied from the register file based on an instruction decoded by the instruction decode portion, and outputs the result of the complex operation toward the register file. Furthermore, the data storage position determining mechanism determines the storage positions of the real part and imaginary part of output data of the complex operation unit in the register file such that the storage order of the real part and imaginary part of the output data in the register file is consistent with the storage orders of the real parts and imaginary parts of the first and second complex number data.

Abstract: The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and execution logic. The cryptographic instruction is received by logic within a processor, wherein said cryptographic instruction prescribes one of the cryptographic operations. The execution logic is coupled to said logic. The execution logic performs the one of the cryptographic operations.

Abstract: A system (20) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array (10) having a programmable fabric (12). The system can include a predefined interface (42) between an embedded microprocessor and the programmable fabric as well as a translator (25) enabling a single hardware description language to define the system including both the microprocessor and the programmable fabric.

Abstract: A computer system comprising mass storage, a system bus connected to the mass storage, and a processor unit connected to the system bus. A library of standard functions is stored in the mass storage. Each library function is stored in at least one of two versions. The first version is obtained from compilation of firmware code, as is conventional. The second version is obtained from compilation of firmware code and comprises a set of configuration data for loading into a field programmable gate array (FPGA). The computer system is provided with a FPGA connected to the system bus which can be configured by the second versions of the library functions so that these can be performed in the FPGA, instead of in the processor. The apparatus and method are well suited to libraries of database search engine functions. Performance advantages can be obtained by executing function calls in the FPGA.

Abstract: A digital signal process of a plurality of functions is enabled by a common hardware constructed on one chip having input terminals t1, t2 and t2'; output terminals t3 and t4; and a control signal input terminal t5. The chip is constructed to include class sorting circuits 111a and 111b; delay and selecting circuits 112a and 112b; switching circuits 113a and 113b; switching circuits 114a and 114b; coefficient memories 115a and 115b; filter operating circuits 116a and 116b; a line delay circuit 117; a product sum operating circuit 118; and a switching circuit 119. Signal flow and circuit functions are selectively controlled by control signals. The functions of the chip can be consequently switched and a plurality of signal processes are realized by one chip.

Abstract: A system and a method using a computer for performing a boolean operation on bit strings to form a resultant bit string. Each such bit string is divided into input bit slices. The resultant bit string is divided into a resultant bit slices. An action is determined according to the boolean operation based on a first such input bit slice from a first such bit string and on a second such input bit slice from a second such bit string. The input bit slice with a longer bit length is selected from between the first input bit slice and the second input bit slice. The longer input bit slice and a plurality of the input bit slices in the bit string having the input bit slice with a shorter bit length are processed according to the determined action for up to a number of bits in at least one such bit string equaling the longer bit length to form at least one such resultant bit slice.

Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers ("GPRs" 102) and an arithmetic logic unit ("ALU" 104), capable of performing arithmetic operations and comparison operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN) capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.