Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: The present disclosure belongs to the technical field of information, provides a short-term interval prediction method for photovoltaic power output, and is a short-term interval prediction method for photovoltaic power output based on a combination of a multi-objective optimization algorithm and a least square support vector machine. The present disclosure firstly proposes a similar day classification method considering both numerical value and pattern similarity to enhance the regularity of samples, then constructs an adaptive proportional interval estimation model based on dual-LSSVM model, and optimizes model parameters by using NSGA-II algorithms to realize the interval prediction of photovoltaic power output. Results obtained by the method have high accuracy, and computation efficiency meets actual application requirements. The method can also be popularized and applied in the fields of grid connection and scheduling of renewable energy sources.

Abstract: In one embodiment, an apparatus comprises a plurality of bitwise multipliers, a bitwise multiplier of the plurality of bitwise multipliers to multiply a binary synapse weight value of a neural network by a binary activation state value of a neuron of the neural network. The apparatus further comprises a plurality of majority voters, a majority voter of the plurality of majority voters to receive outputs of a first group of bitwise multipliers and to generate a majority result to indicate whether a majority of outputs of the first group of bitwise multipliers are set to a first binary value or a second binary value. The apparatus also comprises a first plurality of reconfigurable connections coupled to outputs of the plurality of bitwise multipliers and inputs of the plurality of majority voters.

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

Abstract: For example, the present techniques may provide an energy-efficient multipurpose encryption engine capable of processing both AES and CRC algorithms using a shared Galois Field Computation Unit (GFCU). In an embodiment, an apparatus may comprise computation circuitry adapted to perform Galois Field computations and control circuitry adapted to control the computation circuitry so as to selectively compute either an Advanced Encryption Standard cipher or a Cyclic Redundancy Check.

Abstract: A storage unit stores hyperplane information indicating a first hyperplane, and second and third hyperplanes parallel to the first hyperplane. A computing unit generates a first binary value based on whether the position of a first feature vector is in the direction of a normal vector relative to the second hyperplane, a second binary value based on whether the position of the first feature vector is in the direction of the normal vector relative to the third hyperplane, and a third binary value based on whether the position of a second feature vector is in the direction of the normal vector relative to the first hyperplane, and determines a degree of similarity between the pieces of comparison data, based on a result of multiplying the exclusive OR result of the first and third binary values and the exclusive OR result of the second and third binary values.

Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

Abstract: In some examples, a communications device includes a magnetic memory accessible by both a central processing unit and a digital signal processor to enable the central processing unit to assist the digital signal processor in establishing and maintaining a communication channel. The communication device is configured to re-establish communications in the event of an interruption in the communication channel or if the communication device experiences a power loss event.

Abstract: In a general aspect, a method for executing a target operation combining a first input data with a second input data, and providing an output data can include generating at least two pairs of input words each comprising a first input word and a second input word and applying to each pair of input words a same derived operation providing an output word including a part of the output data resulting from the application of the target operation to first and second input data parts present in the pair of input words, and a binary one's complement of the output data part.

Abstract: A parallel computer system includes a plurality of processing apparatuses that perform an arithmetic operation on elements of an array in parallel, wherein each of the plurality of processing apparatuses performs an arithmetic operation in a first axial direction on a first predetermined number of elements among elements disposed in the processing apparatus by different processing apparatuses, and stores the first predetermined number of elements having been subjected to the arithmetic operation in a storage device of the processing apparatus, and wherein at least some of the plurality of processing apparatuses acquire elements other than the first predetermined number of elements from each of the plurality of processing apparatuses, perform an arithmetic operation in the first axial direction on the acquired elements, and dispose a second predetermined number of elements having been subjected to the arithmetic operation in each of the plurality of processing apparatuses.

Abstract: A method for computing trigonometric functions, performed by an ALU (Arithmetic Logic Unit) in coordination with an SFU (Special Function Unit), is introduced to contain at least the following steps. The ALU computes a remainder r and a reduction value x* corresponding to an input parameter x. The SFU computes an intermediate function f(x*) corresponding to the reduction value x*. The ALU computes a multiplication of the reduction value x* by the intermediate function f(x*) as the computation result of a trigonometric function.

Abstract: A method is disclosed for performing calculations for an inclinometer device, as is a digital circuitry for performing such calculations. The circuitry comprises an interface for receiving detection signals from a sensor device and a CORDIC unit for performing calculation of inclinometer output values characterizing a resultant vector. The CORDIC calculation unit is configured to perform a calculation for resolving the angle between a resultant vector and a programmable reference value using hyperbolic CORDIC calculation. Pre-rotation may be performed for a vector before hyperbolic CORDIC arctangent calculation phases.

Abstract: A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

Abstract: According to some embodiments, the present disclosure may include a method of analyzing solar power forecasts that may include obtaining a test dataset of historical irradiance at a location of a solar power generating system, and normalizing the test dataset based on a clear sky model at the location. The method may also include clustering the test dataset into multiple weather classes that each include a set of characteristics, obtaining a forecast of irradiance at the solar power generating system, and classifying the forecast into one of the weather classes, and determining confidence intervals of the forecast based on the set of characteristics of the one of the plurality of weather classes. The method may additionally include, based on the confidence intervals of the forecast, performing one of increasing output or decreasing output of a source of energy alternative to solar energy.

Abstract: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for producing programmable probability distribution function of pseudo-random numbers that can be utilized for filtering (dropping and passing) neuron spikes. The present disclosure provides a simpler, smaller, and lower-power circuit than that typically used. It can be programmed to produce any of a variety of non-uniformly distributed sequences of numbers. These sequences can approximate true probabilistic distributions, but maintain sufficient pseudo-randomness to still be considered random in a probabilistic sense. This circuit can be an integral part of a filter block within an ASIC chip emulating an artificial nervous system.

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract: Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

Abstract: A computer system is operable to identify subfields that differ in two data elements using a bit matrix compare function between a first matrix filled with pattern elements and a reference pattern.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.

Abstract: Circuitry for adding together three long numbers may include the formation of redundant form sum bit signals and redundant form carry bit signals. These signals may be finally combined in a ripple carry adder chain that produces sum bit output signals and ripple carry bit signals. Both a ripple carry bit signal and a redundant form carry bit signal must be passed from the circuitry performing each place of the addition to the circuitry performing the next-more-significant place of the addition. Various techniques are disclosed for facilitating subdividing long chains of such circuitry, as well as possibly including (between such subdivisions) “pipeline” registers for both ripple and redundant form carry bit signals.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.

Abstract: An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithmetic operation on the operands, obtains a result of the arithmetic operation and that transmits the result to a result register. The arithmetic logic unit includes a signal propagation path that includes no greater than two routing paths that connect non-immediately adjacent logic elements.

Abstract: A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.

Abstract: A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent, and adding the first mantissa to a second mantissa associated with the second floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent. Embodiments of a corresponding computer-readable medium and device are also provided.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.

Abstract: A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation.

Abstract: Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.

Abstract: Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathematical operation when at least one operand has n bits, the reconfigurable circuits performs a first sub-operation on m of n bits in a first reconfiguration cycle, and a second sub-operation on p of n bits in a second reconfiguration cycle. The reconfigurable IC also includes at least one storage element for storing at least a portion of the results of the first sub-operation for use during the second reconfiguration cycle in the second sub-operation.

Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m?1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.

Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Abstract: In a determination as to similarity on parts of a piece of data, high-speed processing is performed without the need for a database. Division signal lines (L1 to Lk) that transmit signals corresponding to division data are used.

Abstract: Disclosed are methods and apparatuses to generate a forecast based on generalized differentiation or integration, including but not limited to non-integer or variable order differentiation or integration.

Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.

Abstract: According to an embodiment, a semiconductor device includes an arithmetic device that includes a first storage unit that stores first device-control information for deciding an arithmetic processing to be executed next to an arithmetic processing currently being executed by an arithmetic device and a timing at which the arithmetic processing to be executed next to the arithmetic processing currently being executed by the arithmetic device is executed; and the arithmetic device that includes a second storage unit that stores second device-control information for deciding a content of an operation contained in an arithmetic processing.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: A configurable integrated circuit (“IC”) that includes several configurable tiles, each of which has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. The configurable IC provides a set of associated configurable logic circuits for performing a particular portion of a larger arithmetic operation. The configurable IC provides a carry circuit for generating a carry out signal for the particular portion of the larger arithmetic operation. A configurable storage element is for configurably storing the carry out signal and for providing the stored carry out signal to the carry circuit for performing a subsequent portion of the larger arithmetic operation. The configurable IC provides a configurable interconnect/storage element for configurably routing a carry signal from a first carry chain to a second carry chain and for storing the routed carry signal.

Abstract: A system includes a “found two” module configured to receive an n-bit vector and to generate a “found two” signal indicating whether there are at least two bits of the n-bit vector in a predetermined state. The system also includes a “one's hot” module coupled to the “found two” module. The “one's hot” module is configured to generate, concurrently with the “found two” module, a first one's hot vector (OHV) based on the received n-bit vector. In one embodiment, the system and method indicate whether an input n-bit vector contains at least two high bits.

Abstract: Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products.

Abstract: The present invention provides a method and device for generating a filter coefficient in real time. The method includes: looking up a converted window function value in a converted window function table based on a current coefficient index; generating a current cut-off angular frequency; generating a look-up table address based on the current coefficient index, the filter order and the current cut-off angular frequency and looking up a sine value in a sine table based on the look-up table address; and multiplying the converted window function value by the sine value to obtain the filter coefficient. The device includes a first memory, a second memory, a look-up table address generation module and a first multiplier. The present invention is easily implemented with low hardware resource consumption and high flexibility, and is particularly applicable for the hardware implementation of high-order finite impulse response filters.

Abstract: An apparatus and method for processing a division of a binary polynomial are provided. The apparatus includes a plurality of exclusive OR (XOR) operators that may perform a selective XOR operation with respect to a conditional bit of a dividend polynomial. The plurality of XOR operators may perform selective XOR operations in parallel and accordingly, a division of a binary polynomial may be rapidly performed.

Abstract: Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.