Array Of Elements (e.g., And/or Array, Etc.) Patents (Class 708/232)
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Patent number: 12292946Abstract: A method for implementing formal verification of an optimized multiplier via symbolic computer algebra (SCA)-satisfiability (SAT) synergy includes: systematically recovering, by a reverse engineering algorithm, an adder tree from an optimized multiplier; 2) generating, by a constraint satisfaction algorithm, a reference multiplier only by using an adder based on a constraint condition; and 3) combining, by an SCA-based and SAT-based verification method, complementary advantages of SCA and SAT. In the verification framework, the method introduces a reference multiplier generator for generating a correct reference multiplier. The correct reference multiplier has both a structure similar to a structure of the optimized multiplier and a clear adder boundary. The clear adder boundary allows proving correctness of the correct reference multiplier through SCA-based verification.Type: GrantFiled: December 4, 2024Date of Patent: May 6, 2025Assignee: SHANGHAITECH UNIVERSITYInventors: Rui Li, Lin Li, Yajun Ha
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Patent number: 11804968Abstract: An area efficient architecture for lattice based key encapsulation and digital signature generation having a co-processor with a polynomial arithmetic submodule configured to process polynomial arithmetic and generate integer values representing polynomial coefficients, a hash submodule operably configured to perform hash operations and to generate pseudorandom numbers, a polynomial format submodule communicatively coupled to the polynomial arithmetic submodule and the hash submodule and operably configured to encode polynomials and decode polynomials, a memory bank communicatively coupled with and operably configured to receive and store temporary values from the polynomial arithmetic submodule, the hash submodule, the polynomial format submodule, and a data interface, and with a control unit operably configured to manage the data interface at selectively controlled time intervals and to utilize the polynomial arithmetic submodule, the hash submodule, and the polynomial format submodule to perform the pluralType: GrantFiled: September 30, 2021Date of Patent: October 31, 2023Assignee: PQSecure Technologies, LLCInventors: Luke Beckwith, Mojtaba Bisheh Niasar
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Patent number: 11157594Abstract: A first group of modulo result matrices corresponding to modulo of elements of a first matrix by each of a plurality of moduli is stored. A second group of modulo result matrices corresponding to modulo of elements of a second matrix by each of the plurality of moduli is stored. It is determined whether an element operation of a multiplication of the first matrix with the second matrix can be performed using a first hardware multiplication module rather than a second hardware multiplication module. In response to a determination that the element operation can be performed using the first hardware multiplication module, the element operation is performed using the first hardware multiplication module including by multiplying one or more corresponding elements from the first group of modulo result matrices with one or more corresponding elements from the second group of modulo result matrices.Type: GrantFiled: July 24, 2019Date of Patent: October 26, 2021Assignee: Facebook, Inc.Inventor: Thomas Mark Ulrich
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Patent number: 11036502Abstract: An apparatus and method are provided for performing a vector rearrangement operation as data elements are moved between memory and vector registers. The apparatus has processing circuitry for performing operations specified by a sequence of program instructions, and a set of vector registers, where each vector register is arranged to store a vector comprising a plurality of data elements. The processing circuitry includes access circuitry to move the data elements between memory and multiple vector registers of the set, and to perform a rearrangement operation as the data elements are moved so that the data elements are arranged in a first organisation in the memory and are arranged in a second, different, organisation in the vector registers. Decode circuitry is arranged to be responsive to a group of rearrangement instructions within the sequence of program instructions to produce control signals to control execution of each rearrangement instruction by the processing circuitry.Type: GrantFiled: June 6, 2017Date of Patent: June 15, 2021Assignee: ARM LimitedInventor: Thomas Christopher Grocutt
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Patent number: 10796220Abstract: A new approach is proposed to support efficient convolution for deep learning by vectorizing multi-dimensional input data for multi-dimensional fast Fourier transform (FFT) and direct memory access (DMA) for data transfer. Specifically, a deep learning processor (DLP) includes a plurality of tensor engines each configured to perform convolution operations by applying one or more kernels on multi-dimensional input data for pattern recognition and classification based on a neural network, wherein each tensor engine includes, among other components, one or more vector processing engines each configured to vectorize the multi-dimensional input data at each layer of the neural network to generate a plurality of vectors and to perform multi-dimensional FFT on the generated vectors and/or the kernels to create output for the convolution operations. Each tensor engine further includes a data engine configured to prefetch the multi-dimensional data and/or the kernels to both on-chip and external memories via DMA.Type: GrantFiled: May 11, 2017Date of Patent: October 6, 2020Assignee: Marvell Asia Pte, Ltd.Inventor: Mehran Nekuii
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Patent number: 10402171Abstract: Implementations of data compilers may include: a physical device including a physical parameter, the physical parameter including at least three states. The data compiler may also include a data stream generated from the physical parameter. The data stream may include a plurality of bits. Each bit may be coded with one of a 0, a 1, and an X; the 0, the 1, and the X may correspond with one of the at least three states of the physical parameter, respectively. The data compiler may also include an exclusive OR (XOR) data processor. The XOR processor may be configured to randomize the at least three states of the data stream and output a randomized output data stream.Type: GrantFiled: January 8, 2019Date of Patent: September 3, 2019Assignee: The Arizona Board of Regents Acting for and on Behalf of Northern Arizona UniversityInventor: Bertrand Cambou
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Patent number: 10395752Abstract: The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.Type: GrantFiled: October 11, 2017Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: John A. Fifield, Eric D. Hunt-Schroeder, Darren L. Anand
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Patent number: 10241791Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.Type: GrantFiled: March 20, 2018Date of Patent: March 26, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Lingam, Seok-Jun Lee, Johann Zipperer, Manish Goel
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Patent number: 9954698Abstract: A data stream processing device including a first tapped delay line which outputs data values received via a first data input on N first taps, wherein N is two or more; a second tapped data delay line which outputs data values received via a second data input on N second taps; a first processing unit including N first delayed data inputs and which generates a first data output based on the N first delayed data inputs; a second processing unit including N second delayed data inputs and which generates a second data output based on the N second delayed data inputs; and control circuitry including a mode selection input, and which is coupled to in response to the mode selection input receiving a signal indicating a first mode, simultaneously couple each of the first taps to a respective one of the first delayed data inputs and couple each of the second taps to a respective one of the second delayed data inputs, and in response to the mode select input not receiving a signal indicating the first mode, simultaneouType: GrantFiled: December 9, 2016Date of Patent: April 24, 2018Assignee: Hughes Network Systems, LLCInventors: Tony Chu Huang, Ninad Kelkar
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Patent number: 9501262Abstract: Embodiments relate to vectorized Galois field multiplication. An aspect includes an input of first and second input operands of equal sizes into a single hardware tree, a calculation of a predicted parity as a parity of the first input operand ANDed with a parity of the second input operand, a comparison of the predicted parity with a parity generated on a final result of a Galois field multiplication of the first and second operands and a raising of an error based on a mismatch between the predicted parity and the generated parity.Type: GrantFiled: May 30, 2014Date of Patent: November 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James R. Cuffney, John G. Rell, Jr., Eric M. Schwarz, Patrick M. West, Jr.
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Patent number: 9471281Abstract: Embodiments relate to vectorized Galois field multiplication. An aspect includes a subdivision of first and second input operands into vector elements of equal sizes with multiple modes defined such that a base mode has a size corresponding to a smallest vector element size, which is a factor of a size of the first and second input operands, and a higher mode has a size that is a multiple of the base mode size. The vector elements of the first input operand are modified with a bit mask based on a size of the vector elements. The modified vector elements of the first input operand and the vector elements of the second input operand are input into a single hardware tree configured for subdivision into staggered subtrees a size of each of which being based on the base mode size.Type: GrantFiled: March 14, 2014Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James R. Cuffney, John G. Rell, Jr., Eric M. Schwarz, Patrick M. West, Jr.
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Patent number: 8880574Abstract: An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.Type: GrantFiled: September 24, 2008Date of Patent: November 4, 2014Assignee: Advantest (Singapore) Pte LtdInventor: Jochen Rivoir
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Patent number: 8856197Abstract: A system and method for processing data utilizes a matrix of processing units using an array of commands stored in memory to process input data words to generate output data words, which can be used in various applications.Type: GrantFiled: October 9, 2009Date of Patent: October 7, 2014Assignee: NXP, B.V.Inventor: Xavier Chabot
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Patent number: 8797062Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.Type: GrantFiled: July 16, 2012Date of Patent: August 5, 2014Assignee: Tabula, Inc.Inventors: Herman Schmit, Jason Redgrave
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Patent number: 8788563Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.Type: GrantFiled: April 2, 2009Date of Patent: July 22, 2014Assignee: SARL Daniel TornoInventor: Daniel Torno
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Patent number: 8650230Abstract: Circuitry for adding together three long numbers may include the formation of redundant form sum bit signals and redundant form carry bit signals. These signals may be finally combined in a ripple carry adder chain that produces sum bit output signals and ripple carry bit signals. Both a ripple carry bit signal and a redundant form carry bit signal must be passed from the circuitry performing each place of the addition to the circuitry performing the next-more-significant place of the addition. Various techniques are disclosed for facilitating subdividing long chains of such circuitry, as well as possibly including (between such subdivisions) “pipeline” registers for both ripple and redundant form carry bit signals.Type: GrantFiled: July 1, 2013Date of Patent: February 11, 2014Assignee: Altera CorporationInventor: Martin Langhammer
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Patent number: 8539011Abstract: A device having programmable logic for implementing arithmetic functions is disclosed. The device comprises an input port coupled to receive a configuration bitstream; a plurality of configurable arithmetic blocks, each configurable arithmetic block comprising configurable circuits for implementing arithmetic functions according to bits of the configuration bitstream; a plurality of input registers coupled to receive multi-bit input words to be processed by the plurality of configurable arithmetic blocks; and an output register enabled to generate an output word. A method of implementing an arithmetic function in a device having programmable logic is also disclosed.Type: GrantFiled: July 19, 2007Date of Patent: September 17, 2013Assignee: Xilinx, Inc.Inventor: Bradley L. Taylor
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Patent number: 8255448Abstract: Division can be performed in a programmable integrated circuit device by computing a relatively small number of bits of the inverse of the divisor, and then programming multipliers in a specialized processing block of the device to perform multiplication of the dividend and the inverted divisor. The specialized processing block is constructed to be able to be programmed to support such asymmetric multiplication by providing programmable shifting of partial products, so that the partial products can be shifted one number of bits for symmetric multiplication and a different number of bits for asymmetric multiplication. The process is performed recursively, by chaining a plurality of the specialized processing blocks, so that the result converges notwithstanding the relatively low precision of the inverted divisor.Type: GrantFiled: October 2, 2008Date of Patent: August 28, 2012Assignee: Altera CorporationInventor: Martin Langhammer
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Patent number: 8248102Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.Type: GrantFiled: May 17, 2010Date of Patent: August 21, 2012Assignee: Tabula, Inc.Inventors: Jason Redgrave, Herman Schmit, Steven Teig, Brad L. Hutchings, Randy R. Huang
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Publication number: 20110231463Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.Type: ApplicationFiled: March 16, 2010Publication date: September 22, 2011Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.Inventors: Manoj Gunwani, Harekrishna Verma
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Publication number: 20110231464Abstract: An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.Type: ApplicationFiled: September 24, 2008Publication date: September 22, 2011Applicant: VERIGY (SINGAPORE) PTE. LTD.Inventor: Jochen Rivoir
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Publication number: 20110131463Abstract: In one embodiment, a forward substitution component performs forward substitution based on a lower-triangular matrix and an input vector to generate an output vector. The forward substitution component has memory, a first permuter, an XOR gate array, and a second permuter. The memory stores output sub-vectors of the output vector. The first permuter permutates one or more previously generated output sub-vectors stored in the memory based on one or more permutation coefficients corresponding to a current block row of the lower-triangular matrix to generate one or more permuted sub-vectors. The XOR gate array performs exclusive disjunction on (i) the one or more permuted sub-vectors and (ii) a current input sub-vector of the input vector to generate an intermediate sub-vector. The second permuter permutates the intermediate sub-vector based on a permutation coefficient corresponding to another block in the current block row to generate a current output sub-vector of the output vector.Type: ApplicationFiled: December 22, 2009Publication date: June 2, 2011Applicant: LSI CORPORATIONInventor: KIRAN GUNNAM
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Publication number: 20110131462Abstract: In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector.Type: ApplicationFiled: December 22, 2009Publication date: June 2, 2011Applicant: LSI CorporationInventor: Kiran Gunnam
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Publication number: 20110106869Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.Type: ApplicationFiled: April 2, 2009Publication date: May 5, 2011Applicant: SARL DANIEL TORNOInventor: Daniel Torno
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Patent number: 7921148Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.Type: GrantFiled: August 9, 2006Date of Patent: April 5, 2011Assignee: Infineon Technologies AGInventor: Thomas Kuenemund
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Patent number: 7917559Abstract: An integrated circuit (IC) is disclosed that includes a set of configurable logic circuits. Each configurable logic circuit configurably performs a set of functions. A particular configurable circuit receives configuration data defining a function for the particular configurable circuit. In some embodiments, one configuration of a configurable circuit is to add two input signals received by the configurable circuit. Also, in some embodiments, one configuration is to subtract two input signals received by a configurable circuit. In some such embodiments, each configurable logic circuit receives a first input signal, a second input signal, and a carry input signal and generates a propagate and generate signal for the add or subtract operation based on the inputs to the configurable circuit and the configuration of the configurable circuit.Type: GrantFiled: March 15, 2005Date of Patent: March 29, 2011Assignee: Tabula, Inc.Inventor: Jason Redgrave
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Patent number: 7853632Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.Type: GrantFiled: May 12, 2006Date of Patent: December 14, 2010Assignee: Xilinx, Inc.Inventors: Alvin Y. Ching, Jennifer Wong, Bernard J. New, James M. Simkins, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
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Publication number: 20100306293Abstract: A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality.Type: ApplicationFiled: May 12, 2010Publication date: December 2, 2010Applicant: International Business Machines CorporationInventors: Yu Fei Li, Yong Lu, Guang Chang Ye, Fan Zhou
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Patent number: 7844352Abstract: A system for embedding real-time Model Predictive Control (MPC) in a System-on-a-Chip (SoC) devices is provided. In the system, a microprocessor is connected to an auxiliary unit or application-specific matrix coprocessor. The microprocessor can control the operation of the MPC algorithm, i.e., carry out the tasks of input/output for the MPC algorithm, initialize and send the appropriate commands to auxiliary unit and receive back the optimal control moves or instructions from auxiliary unit. The auxiliary unit can operate as a matrix coprocessor by executing matrix operations, e.g. addition, multiplication, inversion, etc., required by the MPC algorithm.Type: GrantFiled: October 22, 2007Date of Patent: November 30, 2010Assignee: Lehigh UniversityInventors: Panagiotis Vouzis, Leonidas Bleris, Mark G. Arnold, Mayuresh V. Kothare
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Patent number: 7743085Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.Type: GrantFiled: March 15, 2005Date of Patent: June 22, 2010Assignee: Tabula, Inc.Inventors: Herman Schmit, Jason Redgrave
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Publication number: 20100070548Abstract: An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Sergei B. Gashkov, Alexandre Andreev
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Publication number: 20090136022Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.Type: ApplicationFiled: March 6, 2006Publication date: May 28, 2009Inventors: Peter Langendoerfer, Zoya Dyka, Peter Steffen
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Publication number: 20090106337Abstract: The invention, based on an original addition algorithm for adding two binary numbers, a and b, and disclosed in the body of this application, is a schematic diagram of a serial, synchronous, digital adder, with circuitry which exemplifies an unusual procedure for calculating the carry at any bit pair, ai and bi, and is not based on a recursive function of the carry, ci?1. The operation of “adding” defined in the algorithm is one, in which there is no obvious “addition” at all, as classically defined, and which may or may not eventually become applicable in future or other technologies (besides that of the digital computer), as those technologies develop or come to light. The invention also encompasses designs for modified data registers.Type: ApplicationFiled: April 23, 2006Publication date: April 23, 2009Inventor: Rada Ruth Higgins
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Publication number: 20090077145Abstract: A reconfigurable arithmetic circuit including a matrix having a plurality of partial product mask cells arranged in rows and columns, where rows and columns have incrementing arithmetic weights assigned, each partial product mask cell including a gate implementing a logical AND function of its inputs to provide an output, and a programmable memory cell connected to furnish input to the gate, a plurality of horizontally oriented conductors each connected to furnish input to the gates of the partial product mask cells of a row, and a plurality of diagonally oriented conductors each connected to furnish input to the gates of the partial product mask cells along the diagonal of increasing arithmetic weight of rows and columns, and a compression circuit receiving inputs from the gates of the partial product mask cells of the matrix, and furnishing outputs providing conventional arithmetic compression of its inputs in carry-saved format.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Inventor: Ivo J. Dobbelaere
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Patent number: 7500043Abstract: Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column array. The interconnects and/or data processing elements may be synchronous or asynchronous. The data processing elements may operate in a fixed manner, or they may be programmable, and selectable data processing elements in the array may be bypassed. The interconnects and data processing elements may be configured to handle data in a digit-serial manner, with tags for each digit identifying whether the digit is the first and/or last digit in a data word. The data processing elements may be coupled to a system bus that enables communication of data between the data processing elements and external devices and allows control information to be communicated to and from the data processing elements.Type: GrantFiled: April 21, 2006Date of Patent: March 3, 2009Assignee: Altrix Logic, Inc.Inventor: Paul B. Wood
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Patent number: 7479802Abstract: A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.Type: GrantFiled: December 22, 2007Date of Patent: January 20, 2009Assignee: Quadric, IncInventors: Dean J. Arriens, Paul Short
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Publication number: 20090013146Abstract: A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an original collection of data to a transformed collection of data using a reversible mathematical operator. The original collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands.Type: ApplicationFiled: July 6, 2007Publication date: January 8, 2009Inventors: Chung H. Lam, Bipin Rajendran
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Patent number: 7463678Abstract: A circuit and method is provided for reducing the effect of having potentially different sizes for an Inverse Discrete Fourier Transform (IDFT) at a transmitter and a Discrete Fourier Transform (DFT) at a receiver in a telecommunications system without requiring a change in the DFT's size. The method includes following steps. The first step includes determining whether the IDFT size is greater than, equal to, or less than the DFT size. The second step includes selecting a target impulse response length from a predefined set of impulse response lengths in accordance with a result the previous step. The third step includes training an equalizer at the receiver to the target impulse response length. The circuit comprises hardware and software for implementing the method.Type: GrantFiled: March 10, 2003Date of Patent: December 9, 2008Assignee: CIENA CorporationInventors: Alberto Ginesi, Song Zhang, Andrew Deczky, Duncan Baird, Christian Bourget
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Publication number: 20080195685Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.Type: ApplicationFiled: January 10, 2008Publication date: August 14, 2008Applicant: Analog Devices, Inc.Inventors: Andreas D. Olofsson, Baruch Yanovitch
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Patent number: 7240263Abstract: An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select signals, and the second select register generates a set of complement encoded select signals. Coupled to the first and second select registers, the decoder decodes the set of true encoded select signals and the set of complement encoded signals for controlling the chain of multiplexors. Each multiplexor within the chain of multiplexors is connected to one of the outputs of the decoder. The chain of multiplexors generates a single output value based on the set of select signals.Type: GrantFiled: February 21, 2005Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: John Stanley Bialas, Jr., Ralph D. Kilmoyer
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Patent number: 7205791Abstract: A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also includes a second path connecting a second series of logic elements in the logic array block, where one or more of the logic elements in the second series are not in the first series.Type: GrantFiled: March 12, 2004Date of Patent: April 17, 2007Assignee: Altera CorporationInventors: Andy L. Lee, Ninh Ngo, Vaughn Betz, David Lewis, Bruce Pederson, James Schleicher
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Patent number: 7196541Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.Type: GrantFiled: February 12, 2004Date of Patent: March 27, 2007Assignee: Koninklijke Philips Electronics N.V.Inventor: Katarzyna Nowak-Leijten
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Patent number: 7193433Abstract: A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.Type: GrantFiled: June 14, 2005Date of Patent: March 20, 2007Assignee: Xilinx, Inc.Inventor: Steven P. Young
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Patent number: 7164288Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.Type: GrantFiled: February 12, 2004Date of Patent: January 16, 2007Assignee: Koninklijke Philips Electronics N. V.Inventor: Katarzyna Leijten-Nowak
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Patent number: 7047166Abstract: A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The method uses for every product term of logical equations, expressed as a sum-of-product, three memory words: mask word, product word and function word. The words of all product terms are ranged in a table, which characterize the logical behavior of the circuit. The invention provides the hardware structure of several new types of VSLI circuits, having re-configurable logic behaviors. A first embodiment implements any type of multiple output combinational circuit, a second embodiment implements any synchronous sequential circuit with only clock input and, a third embodiment implements any synchronous sequential circuit s with data inputs and clock input.Type: GrantFiled: June 6, 2001Date of Patent: May 16, 2006Assignee: Ioan DanceaInventor: Ioan Dancea
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Patent number: 7007264Abstract: A system (20) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array (10) having a programmable fabric (12). The system can include a predefined interface (42) between an embedded microprocessor and the programmable fabric as well as a translator (25) enabling a single hardware description language to define the system including both the microprocessor and the programmable fabric.Type: GrantFiled: May 2, 2003Date of Patent: February 28, 2006Assignee: Xilinx, Inc.Inventor: Michael A. Baxter
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Patent number: 6938223Abstract: A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics and signal integrity. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.Type: GrantFiled: February 15, 2002Date of Patent: August 30, 2005Assignee: Zenasis Technologies, Inc.Inventors: Vamsi Boppana, Debashis Bhattacharya
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Patent number: 6873181Abstract: Disclosed is a method of freeing up a non-arithmetic logic block by configuring an LE driving the non-arithmetic logic block to carry out the non-arithmetic logic function of the non-arithmetic logic block. Appropriately configured LEs are identified and the LEs are reconfigured to incorporate or “push back” the non-arithmetic logic into the LE, thus advantageously freeing up the non-arithmetic logic block and allowing it to be used for logic functions driven by other LEs.Type: GrantFiled: August 13, 2003Date of Patent: March 29, 2005Assignee: Altera CorporationInventor: Bruce Pedersen
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Patent number: 6754686Abstract: A method and apparatus for implementing fast sum-of-products logic in a Field Programmable Gate Array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice to output of another slice preceding the first slice.Type: GrantFiled: October 13, 2000Date of Patent: June 22, 2004Assignee: Xilinx, Inc.Inventor: Alireza S. Kaviani
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Patent number: 6732126Abstract: A programmable and configurable datapath unit (DPU) includes a configuration of single-bit multi-function processing units (PUs). The DPU can perform any of a variety of functions depending on the control applied to each PU. Functionality can be increased by utilizing multiplexers to direct data into, out of, and through each DPU dependent on the selected function being performed. Datapath units can also be configured and interconnected to form larger datapath circuits, arrays, and systems so as to increase the data throughput of the datapath system. A configurable and programmable datapath array includes rows of datapath units which can be interconnected to provide DPU circuits having varying input operand widths and functions. A datapath system can be constructed with a plurality of arrays of DPUs to further increase system data throughput.Type: GrantFiled: May 7, 1999Date of Patent: May 4, 2004Assignee: Intel CorporationInventor: Hsinshih Wang