Abstract: Embodiments of the present disclosure propose an Erasing-based Lossless Floating-point compression method, i.e., Elf. The main idea of Elf is to erase the last few bits (i.e., set them to zero) of floating-point values, so the XORed values are supposed to contain many trailing zeros, where the erased bits are determined based on the decimal place count and the digits on the exponent bits.

Abstract: A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing neural network computations using a system configured to implement a neural network on a hardware circuit. The system includes a host that receives a batch of inputs to a neural network layer. Each of the inputs is stored in a memory location identified by an address. The system identifies one or more duplicate addresses in a listing of addresses for one or more inputs. For each duplicate address: the system generates a unique identifier that identifies the duplicate address in the listing of addresses. The system (i) obtains first inputs from memory locations identified by addresses corresponding to the unique identifiers and (ii) generates an output of the layer from the obtained first inputs.

Abstract: A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.

Abstract: A primary interval for convergence of at least one power series in a transcendental function is interpolated, while selecting a number of one or more interpolation points for a truncated expansion of the at least one power series by a selected order of truncation. A function and at least one derivative of the function of the truncated expansion of the selected order of truncation is evaluated at the one or more interpolation points. Each separate value evaluated for the function and each of the at least one derivative is saved in a table, wherein the table is looked up for efficiently computing a result of the truncated expansion of the at least one power series.

Abstract: A configurable processor comprises a memory die and a logic die. The memory die comprises a programmable memory array for storing a look-up table (LUT) for a mathematical function, while the logic die comprises an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.

Abstract: A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.

Abstract: Disclosed is a function masking apparatus in a symmetric cryptographic algorithm for preventing side channel attacks, including: a controller creating lookup tables for one or more internal functions included in a high security and light weight (HIGHT) algorithm, respectively based on a plurality of non-linear functions, a plurality of linear functions, and a plurality of constants which are randomly generated; and a storage unit storing the lookup tables for one or more internal functions included in the generated HIGHT algorithm.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: In an embodiment, hardware implementing a transcendental or other non-linear function is based on a series expansion of the function. For example, a Taylor series expansion may be used as the basis. One or more of the initial terms of the Taylor series may be used, and may be implemented in hardware. In some embodiments, modifications to the Taylor series expansion may be used to increase the accuracy of the result. In one embodiment, a variety of bit widths for the function operands may be acceptable for use in a given implementation. A methodology for building a library of series-approximated components for use in integrated circuit design is provided which synthesizes the acceptable implementations and tests the results for accuracy. A smallest (area-wise) implementation which produces a desired level of accuracy may be selected as the library element.

Abstract: Methods and systems for memory-based computing include combining multiple operations into a single lookup table and combining multiple memory-based operation requests into a single read request. Operation result values are read from a multi-operation lookup table that includes result values for a first operation above a diagonal of the lookup table and includes result values for a second operation below the diagonal. Numerical inputs are used as column and row addresses in the lookup table and the requested operation determines which input corresponds to the column address and which input corresponds to the row address. Multiple operations are combined into a single request by combining respective members from each operation into respective inputs an reading an operation result value from a lookup table to produce a combined result output. The combined result output is separated into a plurality of individual result outputs corresponding to the plurality of requests.

Abstract: Systems for memory-based computing include combining multiple operations into a single lookup table and combining multiple memory-based operation requests into a single read request. Operation result values are read from a multi-operation lookup table that includes result values for a first operation above a diagonal of the lookup table and includes result values for a second operation below the diagonal. Numerical inputs are used as column and row addresses in the lookup table and the requested operation determines which input corresponds to the column address and which input corresponds to the row address. Multiple operations are combined into a single request by combining respective members from each operation into respective inputs an reading an operation result value from a lookup table to produce a combined result output. The combined result output is separated into a plurality of individual result outputs corresponding to the plurality of requests.

Abstract: Circuitry for computing a tangent function of an input value includes first look-up table circuitry that stores pre-calculated tangent values of a limited number of sample values, circuitry for inputting bits of the input value of most significance as inputs to the first look-up table circuitry to look up one of the pre-calculated tangent values as a first intermediate tangent value, circuitry for calculating a second intermediate tangent value from one or more ranges of remaining bits of the input value, and circuitry for combining the first intermediate tangent value and the second intermediate tangent value to yield the tangent function of the input value.

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract: Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first trigonometric function from the respective initial values of the plurality of trigonometric functions. The trigonometric function may be any of sine, cosine and tangent and their inverse functions. The trigonometric identities used allow a computation of a trigonometric function to be broken into pieces that either are easier to perform or can be performed more accurately.

Abstract: Techniques and mechanisms for executing a vector instruction with a processor. In an embodiment, a vector definition instruction is executed to perform operations associated with setting a first vector as a reference vector, the operations resulting in vector multiplication information being stored in a look-up table. In another embodiment, a vector multiplication instruction is subsequently executed to perform a vector multiplication calculation based on the vector multiplication information stored in the look-up table.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.

Abstract: A data processing apparatus is provided with lookup table circuitry for receiving from the processing circuitry an n-bit input data value, and for returning to the processing circuitry an output data value. The lookup table circuitry provides a plurality of entries identifying possible input data values and corresponding output data values, with the plurality of entries being less than 2n. Input interface circuitry receives the n-bit input data value, detects a modification condition if any of a predetermined number of significant bits of the input data value are logic zero values, and performs a shift operation on the input data value if the modification condition is detected, prior to providing the input to the lookup table. Output interface circuitry is then arranged, if the modification condition is detected, to perform an output data value derivation operation on the output data value as received from the lookup table.

Abstract: In an embodiment, hardware implementing a transcendental or other non-linear function is based on a series expansion of the function. For example, a Taylor series expansion may be used as the basis. One or more of the initial terms of the Taylor series may be used, and may be implemented in hardware. In some embodiments, modifications to the Taylor series expansion may be used to increase the accuracy of the result. In one embodiment, a variety of bit widths for the function operands may be acceptable for use in a given implementation. A methodology for building a library of series-approximated components for use in integrated circuit design is provided which synthesizes the acceptable implementations and tests the results for accuracy. A smallest (area-wise) implementation which produces a desired level of accuracy may be selected as the library element.

Abstract: A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

Abstract: Nonlinear compression of high precision image data (e.g., 12-bits per subpixel) conventionally calls for a large sized lookup table (LUT). A smaller sized and tunable circuit that performs compression with piecewise linear compressing segments is disclosed. The piecewise linear data compressing process is organized so that lumping together of plural ‘used’ high precision value points into one corresponding low precision data value point is avoided or at least minimized. In one embodiment, the compressed data is image defining data being processed for display on a nonconventional display screen where the piecewise linearly compressed data can be stored adjacent to other image data in a frame buffer where a composite image is assembled.

Abstract: A device having programmable logic for implementing arithmetic functions is disclosed. The device comprises an input port coupled to receive a configuration bitstream; a plurality of configurable arithmetic blocks, each configurable arithmetic block comprising configurable circuits for implementing arithmetic functions according to bits of the configuration bitstream; a plurality of input registers coupled to receive multi-bit input words to be processed by the plurality of configurable arithmetic blocks; and an output register enabled to generate an output word. A method of implementing an arithmetic function in a device having programmable logic is also disclosed.

Abstract: An algebraic processor as part of a wireless telecommunication system, including pre-computed Look Up Tables (LUT), used for computing a number of different functions using linear interpolation. Preferably, the step of computing is implemented in a multiplier-accumulator having a SIMD structure.

Abstract: A logic circuit has a first logic element (“LE”) including a first lookup table (“LUT”), where the first LUT is operable to produce a carry from a first set of bits of at least two numbers. The logic circuit also has a second LE including a second LUT, where the second LUT is operable to produce a sum from a second set of bits of the at least two numbers. The second LE also includes an adder coupled directly to the first LUT and coupled to the second LUT, where the adder is operable to add the carry and the sum. The at least two numbers may be three numbers, but the logic circuit includes a set of connections operable to programmably interconnect selected inputs so that the logic circuit is operable to add only two numbers. The logic circuit may be incorporated in a programmable logic device.

Abstract: Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathematical operation when at least one operand has n bits, the reconfigurable circuits performs a first sub-operation on m of n bits in a first reconfiguration cycle, and a second sub-operation on p of n bits in a second reconfiguration cycle. The reconfigurable IC also includes at least one storage element for storing at least a portion of the results of the first sub-operation for use during the second reconfiguration cycle in the second sub-operation.

Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.

Abstract: A method and apparatus for fractional digital integration of an input signal is provided, the input signal including a time series of numerical values and the method or apparatus including applying the input signal time series to one input of a two-input summer at a time I, providing an output of the summer to a delay register at time I, providing an output of the delay register from time i?1 to a two-input multiplier, providing an output of the multiplier to the summer at time I, using a resettable counter to determine a value i and index a lookup table with i to provide the indexed value of the lookup table as an input to the multiplier, and obtaining an output signal time series from the output of the summer.

Abstract: Original Pi Estimating Method (PEM) Algorithm is primarily intended for computer application. PEM Algorithm, given in ‘word format’, describes a math process suitable for programming. Using sufficient pi truncations and the set of all real numbers for domain divisions, PEM math process permits a user to specify goal-precisions and to estimate goal-displacements in ALL dimensional-space, domains and ranges, particularly, for ALL infinitesimal space, including beyond quantum values. By use of super-computer, PEM Algorithm can be combined with appropriate interface to control high energy devices for consistent, precise, repeatable values. Uncertainty and probabilities, involved during microscopic, infinitesimal displacements, require precise and repeatable estimates within atomic, sub-atomic, and beyond—domains. Since PEM provides reliable, repeatable, estimates of pi approximations close to actual displacements: probabilities increase and uncertainties lessen.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate pseudo-random sequences in response to a first m-sequence and a second m-sequence, where the first m-sequence is initialized with a pre-calculated constant and the second m-sequence is initialized based on a pre-defined initial sequence and a table of pre-calculated values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store the table of pre-calculated values.

Abstract: A method and apparatus for computing a discrete logarithm using a pre-computation table are provided. The method includes previously generating the pre-computation table consisting of chains of function values obtained by applying an iterating function to a predetermined number of initial values having a generator of the cyclic group as a base and having different exponents; and if a function value obtained by applying the iterating function to a value having a target element as a base and having an exponent is identical to a function value stored in the pre-computation table, computing the discrete logarithm of the target element by using exponent information of the two function values.

Abstract: In a method for the transition from a first masked representation of a value to be kept secret to a second masked representation of the value, according to a first aspect of the invention at least one previously calculated table with a plurality of entries is used, and the calculation is carried out depending on at least one veiling parameter, in order to prevent the value to be kept secret from being spied out. According to a second aspect of the invention, at least one comparison table is used, which, for each table index, provides the result of a comparison between a value dependent on the table index and a value dependent on at least one masking value. A computer program product and a device have corresponding features. The invention provides a technique for protecting the transition between masked representations of a value from being spied out, wherein the masked representations are based on different masking rules.

Abstract: A look-up table (LUT) is arranged as a plurality of rows each indexed by an index value and storing at least a coefficient for each index value for use in processing digital data. The LUT contains repeated sections in which m coefficients stored for successive index values form a cycle. The number m is not an integer power of 2. For example the LUT may be used when converting a digital count to a gain in dB, in which case m may be 6 or 12, the coefficients representing dB or fractional-dB steps in gain. The LUT contains n additional blank rows inserted after every repeated section of m rows storing the cycle of m coefficients, n being 1 or more and (m+n) being an integer power of two (such as 8 or 16). By feeding an initial index value through encoding logic which takes account of the additional rows, it can be ensured that these are never indexed. Thus, a sparse-coded LUT is provided.

Abstract: Discrete cosine transform/inverse discrete cosine transform method and device are provided. The discrete cosine transform/inverse discrete cosine transform method includes: generating a table index for only an input value other than 0 (zero) out of input values of coordinates in an input block; reading one or more partial values corresponding to the table index out of a plurality of table information pieces which are generated and stored in advance so as to include partial values corresponding to a multiplication of a weight value and an index; and adding the read partial value and calculating the resultant value of each coordinate in an output block. Accordingly, it is possible to perform a fast DCT/IDCT operation and to reduce the energy consumption for the transform.

Abstract: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.

Abstract: A terminal is provided, the terminal comprising: a display unit configured to display information that is processed; a user input unit configured to input information on amount of carbon emission; a storage stored with information on the amount of carbon emission inputted through the user input unit and a program for calculating the amount of carbon emission; and a controller configured to calculate the amount of carbon emission based on usage of carbon emission and to display the amount of carbon emission on the display unit.

Abstract: A method and apparatus for providing a traffic information service to a vehicle. Traffic information is broadcast through an external network to the vehicle, wherein the traffic information is based on a first map. Data within the broadcasted traffic information and based on a the first map is compared to a second map provided in a vehicle navigation unit, wherein the second map is different than the first map. A traffic information service is provided to the vehicle navigation unit, wherein the vehicle navigation unit is configured for displaying the traffic information with the second map.

Abstract: One or more expressions are evaluated that represent one or more characteristics of a dataflow graph that includes vertices representing data processing components connected by links representing flows of work elements between the components. A request is received by a computing system to evaluate the one or more expressions that include one or more operations on one or more variables; and the one or more expressions are evaluated by the computing system. The evaluating includes: defining a data structure that includes one or more fields, collecting, during execution of the dataflow graph, tracking information associated with one or more components of the dataflow graph, storing values associated with the tracking information in the one or more fields, and replacing one or more variables of the one or more expressions with the values stored in the one or more fields to compute a result of evaluating the one or more expressions.

Abstract: Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first trigonometric function from the respective initial values of the plurality of trigonometric functions. The trigonometric function may be any of sine, cosine and tangent and their inverse functions. The trigonometric identities used allow a computation of a trigonometric function to be broken into pieces that either are easier to perform or can be performed more accurately.

Abstract: Circuitry for computing a tangent function of an input value includes first look-up table circuitry that stores pre-calculated tangent values of a limited number of sample values, circuitry for inputting bits of the input value of most significance as inputs to the first look-up table circuitry to look up one of the pre-calculated tangent values as a first intermediate tangent value, circuitry for calculating a second intermediate tangent value from one or more ranges of remaining bits of the input value, and circuitry for combining the first intermediate tangent value and the second intermediate tangent value to yield the tangent function of the input value.

Abstract: A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.

Abstract: A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.

Abstract: A reconfigurable processing device comprises one or more reconfigurable processing units. At least one processing unit utilizes a computational unit having a preprocessing module for receiving n input signals, and s1 selection signals, and providing k output signals wherein k<n+s1. The computational unit further comprises an m-output look-up table being addressed by the k output signals of the preprocessing module and an output multiplexer for selecting one of the m output signals of the look-up table under control of s2 further selection signals.

Abstract: An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

Abstract: A method and apparatus for fractional digital integration of an input signal is provided, the input signal including a time series of numerical values and the method or apparatus including applying the input signal time series to one input of a two-input summer at a time I, providing an output of the summer to a delay register at time I, providing an output of the delay register from time i?1 to a two-input multiplier, providing an output of the multiplier to the summer at time I, using a resettable counter to determine a value i and index a lookup table with i to provide the indexed value of the lookup table as an input to the multiplier, and obtaining an output signal time series from the output of the summer.

Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.

Abstract: A method for performing reconstruction using a residue number system includes selecting a set of moduli. A reconstruction coefficient is estimated based on the selected set of moduli. A reconstruction operation is performed using the reconstruction coefficient.

Abstract: A self-contained avionics sensing and flight control system is provided for an unmanned aerial vehicle (UAV). The system includes sensors for sensing flight control parameters and surveillance parameters, and a Global Positioning System (GPS) receiver. Flight control parameters and location signals are processed to generate flight control signals. A Field Programmable Gate Array (FPGA) is configured to provide a look-up table storing sets of values with each set being associated with a servo mechanism mounted on the UAV and with each value in each set indicating a unique duty cycle for the servo mechanism associated therewith. Each value in each set is further indexed to a bit position indicative of a unique percentage of a maximum duty cycle for the servo mechanism associated therewith. The FPGA is further configured to provide a plurality of pulse width modulation (PWM) generators coupled to the look-up table. Each PWM generator is associated with and adapted to be coupled to one of the servo mechanisms.

Abstract: A dynamic filtering device includes a variation detector, a coefficient generator and a filter. The cut-off frequency of the filter is dynamically adjusted according to variations of an input signal. A higher signal-to-noise ratio is obtained when a finger moves in slow motion and its response time is reduced when the finger moves in fast motion, therefore improving the response time and the noise immunity of the filter.

Abstract: The disclosure describes a method for performing a fixed point calculation of a floating point operation (A // B) in a coding device, wherein A // B represents integer division of A divided by B rounded to a nearest integer. The method may comprise selecting an entry from a lookup table (LUT) having entries generated as an inverse function of an index B, wherein B defines a range of values that includes every DC scalar value and every quantization parameter associated with a coding standard, and calculating A // B for coding according to the coding standard based on values A, B1 and B2, wherein B1 and B2 comprise high and low portions of the selected entry of the LUT. The techniques may simplify digital signal processor (DSP) implementations of video coders, and are specifically useful for MPEG-4 coders and possibly others.