Abstract: Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

Abstract: Linear-feedback shift registers (LFSRs) for generating bounded random numbers (e.g., random numbers within a narrower range than those generated by a conventional LFSR of the same width) are described. In one embodiment, a bounded LFSR for generating an n-bit value comprises an m-bit LFSR with a range of 2m random numbers and an n?m bit LFSR with a range of 2n-m?1?k random numbers. The bounded LFSR further comprises logic to skip k values from a repeatable sequence of the n?m bit LFSR, which can, for example, be configured during the design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on the outputs of the m-bit LFSR and the n?m bit LFSR. In one embodiment, the bounded random number generated by the bounded LFSR is used as a random address in a row hammer mitigation system.

Abstract: A method and non-transitory computer-readable medium for performing multiple tests on a device under test (DUT) are provided. The method includes inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

Abstract: Systems and methods for a random number generator including a systolic array to provide a random number output. In one approach, the systolic array can be arranged in two or greater dimensions, and each cell of the array comprises a ring oscillator. Data is read from a random access memory to provide the inputs to the systolic array. A linear feedback shift register receives the random number output as a feedback signal used to address the memory to read data to provide as the inputs to the systolic array.

Abstract: A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

Abstract: A structure for generating sequences. The structure includes a binary shift register; a feedback structure connected to the shift register arranged to define a linear feedback shift register according to a polynomial; a first output arranged to collect one or more state values from a first group of elements of the shift register, the one or more state values from the first group forming a value of a first sequence; and a second output arranged to collect one or more state values from a second group of elements of the shift register, the one or more state values from the second group forming a value of a second sequence. No element of the second group belongs to the first group.

Abstract: A device for providing a random number generator is provided. The device may include a true random number generator, at least one deterministic random number generator, and an exclusive OR logic function. The TRNG has an output and the at least one DRNG has an output. The exclusive OR logic function has a first input coupled to the output of the TRNG and a second input coupled to the output of the at least one DRNG, and an output for providing a random number. The TRNG and the at least one DRNG may include separate and independent entropy sources. A method for generating a random number is also provided.

Abstract: A system and method for generating a composite synchronization sequence in a communication system. In one embodiment, the apparatus is configured to provide a first synchronization sequence and a second synchronization sequence in a first domain, transform the first synchronization sequence and the second synchronization sequence into a second domain, and extend the first synchronization sequence and the second synchronization sequence in the second domain to a common length to produce an extended first synchronization sequence and an extended second synchronization sequence. The apparatus is also configured to transform the extended first synchronization sequence and the extended second synchronization sequence into the first domain, and multiply elementwise the extended first synchronization sequence by the extended second synchronization sequence in the first domain to obtain a composite synchronization sequence.

Abstract: Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third frequency, and a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween. The second frequency is lower than the first frequency, and the third frequency is lower than the second frequency. The true random number generator may further include a D-type flip-flop having a data input connected to an output of the first ring oscillator and having a clock input connected to an output of the third ring oscillator, wherein the D-type flip-flop is configured to generate an output signal representing a sequence of random numbers.

Abstract: A device for generating a random number is suggested, the device comprising at least two shift registers, a transformation function that generates the random number based on at least one cell of each of the at least two shift registers.

Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuitry coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

Abstract: A method for generating M parallel pseudorandom binary sequences (PRBSs), each comprising a 2n?1 sequence of pseudorandom bits, includes loading into the circuit an initial M-bit word, the initial M-bit word comprising M sequential bits selected from a pre-determined PRBS-n sequence, wherein n>1 and M>n. The method includes generating, using a plurality of logic gates of the circuit, a next M-bit word using at least n+1 of the M sequential bits of the initial M-bit word. The method includes repeatedly generating, using the logic gates of the circuit, the next M-bit word from a previous M-bit word using the at least n+1 of M sequential bits of the previous M-bit word, resulting in M parallel sequences of the PRBS-n sequence. The method includes transmitting the generated next M-bit words on an M-bit wide parallel bus.

Abstract: The present disclosure relates to a capsule endoscope transmitter configured to transmit frames including control frames and data frames to a capsule endoscope receiver. The capsule endoscope transmitter includes a preamble generator configured to generate preambles for synchronizing and identifying the control frames used to select a reception electrode pair that receives the frames, and a line sync generator configured to generate a line sync for synchronizing the data frames and identifying a code value of each of the data frames.

Abstract: One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations is disclosed. PUF memory is configured to permanently one-time program an initial randomly generated PUF output from PUF MRAM bit cells accessed in an initial PUF read operation, to the same PUF MRAM bit cells accessed in the initial PUF read operation. In this manner, the initial PUF output is randomly generated due to process variations of the PUF MRAM bit cells to maintain an initial unpredictable memory state, but the PUF output will be reproduced for subsequent PUF read operations to the same PUF MRAM bit cells in the PUF memory array for reproducibility. The OTP of the PUF MRAM bit cells can be accomplished by applying breakdown voltage to the PUF MRAM bit cells during programming.

Abstract: A system and method for deterring malicious network attacks. The system and method is configured to execute instructions on at least one of the processors to generate a plurality of random blocks of data; generate a first XOR result by using the XOR function with the plurality of random blocks of data as the XOR function inputs; generate a tail value by using the XOR function with the first XOR result and a random encryption key as the XOR function inputs; encrypt a designated file using the random encryption key; write the plurality of random blocks and tail value to at least one storage medium; and write the encrypted designated file to at least one storage medium.

Abstract: An apparatus can include at least one test circuit configured to determine if bits sampled at a sample frequency from at least one bit generator are random, and a circuit configured to adjust the sample frequency if the at least one test circuit determines that the sampled bits are not random. The apparatus can be a random number generator. A method may include sampling bits at a first sample frequency, and sampling bits at a second sample frequency if the sampled bits associated with the first sample frequency are not random.

Abstract: A method for detecting a fault injection in a random number generation circuit, wherein a bit pattern is mixed to a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mix.

Abstract: In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal.

Abstract: A random number generator may include an input configured to receive a plurality of entropy bits generated by an entropy source of a random number generator, wherein the random number generator is configured to generate a plurality of random numbers; and an entropy health monitor coupled with the input, wherein the entropy health monitor is configured to perform a corrective action based on the plurality of entropy bits.

Abstract: A random number generating device is provided. The random number generating device includes a first frequency generating circuit, a second frequency generating circuit and a flip-flop. The first frequency generating circuit generates a first frequency signal according to a signal inputted via an input end, and outputs the first frequency signal via an output end. The second frequency generation circuit generates and outputs a clock signal. The flip-flop includes a data input end, a clock input end and a data output end. The data input end and the clock input end are electrically connected to the first frequency generating circuit and the second frequency generating circuit respectively. The flip-flop outputs a random signal via the data output end according to the first frequency signal and the clock signal, and feedbacks the random signal to the first frequency generating circuit to change frequency of the first frequency signal.

Abstract: An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates.

Abstract: Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics.

Abstract: A method for generating multi-level (or multi-bit) pseudo-random sequences is disclosed. This embodiment relates to communication systems, and more particularly to generating multi-level pseudo random symbol sequence. Present day systems do not employ effective mechanisms for generation of multi level PRBS in order to increase the data communication rates. Further, these systems do not cover all the possible transitions for the outputs of the system. The proposed system employs mechanisms in order to generate PRBS signals for producing multi levels signals to the electronic components. The mechanism employs alternate bit tapping techniques. In the alternate bit tapping technique, bits are tapped alternatively to determine the current state and the next state of the system. In addition, the mechanism also covers all the possible states of the output vector with transitions between the output states. This ensures that high data rates are obtained for a given bandwidth of operation.

Abstract: Disclosed is a method for generating a sequence and an apparatus for the same which can satisfy the number M? of sequences sufficiently larger than a length N of a sequence required in a wireless communication system. When the generation of a sequence of the wireless communication system is intended, a first sequence is generated from an mth order primitive polynomial determined according to the length of a required sequence. Then, a second sequence and a third sequence are generated from the first sequence, and a remainder and a quotient is obtained by dividing a particular reference parameter by a number equal to or smaller than 2m+1. Next, a fourth sequence having a desired length N is generated by using the remainder and the quotient. Therefore, it is possible to generate sequences satisfying that the number M? of sequences is sufficiently larger than a length N of the sequence.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for producing programmable probability distribution function of pseudo-random numbers that can be utilized for filtering (dropping and passing) neuron spikes. The present disclosure provides a simpler, smaller, and lower-power circuit than that typically used. It can be programmed to produce any of a variety of non-uniformly distributed sequences of numbers. These sequences can approximate true probabilistic distributions, but maintain sufficient pseudo-randomness to still be considered random in a probabilistic sense. This circuit can be an integral part of a filter block within an ASIC chip emulating an artificial nervous system.

Abstract: A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers.

Abstract: A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.

Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: A method and apparatus for generating a pseudorandom sequence using a hybrid ring generator with low hardware cost. When a primitive polynomial over GF(2) is selected as the characteristic polynomial f(x) to construct a hybrid ring generator, the circuit implementing f(x) will generate a maximum-length sequence (m-sequence). The hybrid ring generator offers unmatched benefits over existing linear feedback shift register (LFSR) based maximum-length sequence generators (MLSGs). Assume k 2-input XOR gates are required in a standard or modular LFSR design. These benefits include requiring only (k+1)/2 2-input XOR gates, having at most one level of a 2-input XOR gate between any pair of flip-flops, enabling the output of each flip-flop to drive at most 2 fanout nodes, and creating a highly regular structure that makes the new design more layout and timing friendly.

Abstract: An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.

Abstract: The random number generator comprises a linear feedback shift register (10), which comprises a series of storage elements (14(1), 14(2), . . . , 14(n)), a first input (11) to receive a clock signal from a clock oscillator (28), a feedback line (20) connecting the output of a last storage element (14(n)) with an input of at least a first storage element (14(1)), a second input (22) coupled with the feedback line (20) via at least one cell (15) and wherein the output of the cell (15) is coupled to an input of at least one of the storage elements (14(1), 14(2), . . . , 14(n)).

Abstract: A device includes a plurality of linear feedback shift registers, a counter having a counter value of a bit length, and a comparator to compare the counter value and an update value including bit values of bit positions of a first linear feedback shift register. The number of bit positions equal to the bit length of the counter value. A second linear feedback shift register to update based on the comparison.

Abstract: A pseudorandom number generating circuit includes: a first generator including a shift register and configured to generate a first pseudorandom number, the shift register including registers, the first pseudorandom number having a plurality of bits corresponding to the registers; a second generator configured to generate a second pseudorandom number; and a selector configured to select a bit that is to be output from the plurality of bits by using the second pseudorandom number.

Abstract: The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).

Abstract: A deterministic random number generator includes a number series generator adapted to generate an infinite Pi series, a summation generator adapted to generate a partial sum of said infinite Pi series, a computer adapted to compute a finite sequence from said partial sum of infinite Pi series, a shuffler adapted to shuffle said computed finite sequence to obtain a shuffled sequence, a masker adapted to mask said shuffled sequence to obtain a masked sequence, a non-linear function processor adapted to process said masked sequence to obtain a non-linear processed sequence, and a linear feedback shift register adapted to receive and shift bits of said non-linear processed sequence in a pre-determined manner to obtain a deterministic random number and a method for generating a deterministic random number for cryptography and watermarking.

Abstract: A mask circuit (2) masks a bit sequence of K bits by a predetermined bit pattern. An EXOR circuit (3) EXORs the masked bit sequence. An inverter (9) controls inversion/non-inversion of values of bits of a bit sequence which includes a bit value indicating the EXOR result in a result obtained by shifting the bit sequence of K bits held in a shift register (1), in accordance with a designated bit value in a pattern table (14). A bit sequence as the control result is output as a random number expressed by K bits.

Abstract: The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).

Abstract: In various embodiments, a pseudo random number generator is provided. The pseudo random number generator may include: a pair of shift registers, wherein a first shift register in the pair is a linear shift register and a second shift register in the pair is a nonlinear shift register, wherein the linear shift register is configured to receive a first output sequence from the nonlinear shift register, and to take the first output sequence as a basis for providing a second output sequence; wherein the pseudo random number generator is configured to take the second output sequence as a basis for providing a pseudo random sequence.

Abstract: A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.

Abstract: A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words, the data words having two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information having a program expression for determining an updated data word of the sequence of data words. Using the predetermined bit position, a sequence length value associated to the predetermined bit position is determined. The program expression is evaluated for a number of loop iterations indicated by the sequence length value, to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations.

Abstract: Maximum length properties of n-state sequences of n-state symbols with n=2 or n>2 are tested. Checkwords are generated from p consecutive n-state symbols in a sequence of n-state symbols which may overlap by (p?1) n-state symbols. If a sequence has np?1 n-state symbols in which 2 consecutive checkwords overlap in (p?1) n-state symbols and each checkword formed in the extended sequence is unique, then the sequence is a maximum length n-state sequence. An n-state feedback shift register based sequence generator with p n-state register elements is tested on the content of the shift register for np?1 cycles. If the shift register content is not repeated the sequence is maximum length. Generation of a sequence is stopped when the content repeats.

Abstract: A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.

Abstract: Spread spectrum clock generators and electronic devices including the same are provided. An electronic device may include a memory and a first circuit block configured to output a first spread spectrum clock signal and a first address for accessing the memory. The electronic device may include a second circuit block configured to operate in response to a second spread spectrum clock signal, and configured to output a second address for accessing the memory. The electronic device may include a spread spectrum clock signal generator configured to receive the first spread spectrum clock signal to generate the second spread spectrum clock signal. The memory may be configured to compare the first and second addresses to each other to output a clock generator control signal corresponding to a difference between the first and second addresses.

Abstract: The present invention is directed to improve leak analysis resistance by improving randomness of a pseudorandom number. A pseudorandom number generator as a representative embodiment of the invention includes a shift resistor obtained by coupling a plurality of flip flop circuits and can generate a pseudorandom number by shifting signals by the shift register synchronously with a clock signal. A shift amount changing circuit capable of changing a shift amount in the shift register in accordance with a control signal supplied from the outside of the pseudorandom number generator is provided. By changing the shift amount in the shift register in accordance with a control signal supplied from the outside of the pseudorandom number generator by the shift amount changing circuit, it becomes difficult to make outputs of the pseudorandom number generator the same. By using such a pseudorandom number generator, leak analysis resistance can be improved.

Abstract: A random number generation system comprising one or more ring oscillators configured to generate entropy due to accumulated phase drift. A random number generator can include a ring oscillator configured to switch between a first state in which a signal of the ring oscillator oscillates between logic levels, and a second state in which the signal at least partially settles to one of the logic levels. The random number generator can also include a counter configured to measure a count of pulses of the signal and a whitener mechanism configured to receive the signal from the ring oscillator, latch a logic level of the signal from the ring oscillator, latch the count of pulses from the counter, and generate a random number based on the logic level and the count of pulses. Corresponding methods may also be performed.

Abstract: The pseudorandom number generating system repeatedly performs simple transformation of a non-secure pseudorandom number sequence that may be generated quickly, and thus may quickly generate a highly secure pseudorandom number sequence having a long period. Furthermore, the encryption system and the decryption system do not generate a large encryption function difficult to be deciphered based on a shared key 122, but prepare multiple functions 126, which perform fast, different types of transformation, and select a combination of functions determined based on information of the shared key 122, and make the selected functions transform a text multiple times, thereby encrypt the text. Each of the functions is fast, and thus transformation by the entire combination is also fast. Furthermore, since the combination of functions and repetitive count can be changed, future improvement in specification is easy. Moreover, security is high since which functions are applied in what order is unknown.

Abstract: A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Abstract: The present invention provides an integrated memory circuit applicable to an S-box of a cryptographic circuit, the integrated memory circuit having a row decoder, a column decoder, and a sense amplifier composed of a domino-RSL circuit, wherein data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines, and the transition probability of a signal line is equalized by input of random-number data supplied from a random-number generating circuit using an arbiter circuit.