Random Number Generation Patents (Class 708/250)
  • Patent number: 11403167
    Abstract: A controller is coupled to a non-volatile memory device and a host. The controller is configured to perform a cyclic redundancy check on map data associated with user data stored in the memory device, generate an encryption code based on a logical address included in the map data, generate encrypted data through a logical operation on the encryption code and the map data, and transmit the encrypted data to the host.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: August 2, 2022
    Assignee: SK hynix Inc.
    Inventor: Joung Young Lee
  • Patent number: 11403514
    Abstract: A computer-implemented method for classification of an input element to an output class in a spiking neural network may be provided. The method comprises receiving an input data set comprising a plurality of elements, identifying a set of features and corresponding feature values for each element of the input data set, and associating each feature to a subset of spiking neurons of a set of input spiking neurons of the spiking neural network. Furthermore, the method comprises also generating, by the input spiking neurons, spikes at pseudo-random time instants depending on a value of the feature for a given input element, and classifying an element into a class depending on a distance measure value between output spiking patterns at output spiking neurons of the spiking neural network and a predefined target pattern related to the class.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: August 2, 2022
    Assignee: International Business Machines Corporation
    Inventors: Giovanni Cherubini, Ana Stanojevic, Abu Sebastian
  • Patent number: 11386234
    Abstract: A system for verifying integrity of content of an integrated circuit's registers, the system being operative in conjunction with an integrated circuit including at least one memory, at least one processor, and a multiplicity of registers, the system comprising register content verification logic configured, when in a first mode aka “Study Mode”, to read at least some of the registers' content, to compute a first hash on the content, and to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in a second mode aka “Verify Mode”, to compute at least one second hash on the content, to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) indicative of whether the reference and second hashes are equal.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 12, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Ilan Margalit
  • Patent number: 11366639
    Abstract: The exemplary embodiments of the present invention provide a quantum random number generation apparatus according to an exemplary embodiment of the present invention including: a space-division semiconductor detector including a plurality of cells, each individually absorbing a plurality of emission particles emitted from a radioactive isotope; and a signal processor that generates a random number based on an absorption event at which the plurality of emission particles are absorbed into the plurality of cells, and thus new type of random number conversion method that combines a spatial randomness and existing temporal randomness of the emission particle can be provided, there is no restriction generated due to the dead time, the random number generation rate can be remarkably increased, and it is possible to generate of a pure random number at high speed, which is required by a computer, a network processor, or an IoT device.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 21, 2022
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KOREA ATOMIC ENERGY RESEARCH INSTITUT
    Inventors: Kyung-Hwan Park, Tae Wook Kang, Jong Bum Kim, Jin Joo Kim, Seong Mo Park, Kwang-Jae Son, Young Rang Uhm, Byounggun Choi, Sang Mu Choi, Jintae Hong
  • Patent number: 11362869
    Abstract: A method of transmitting an On-Off Keying, OOK, signal which includes an ON waveform and an OFF waveform forming a pattern representing transmitted information. The method includes obtaining a basic baseband waveform; scrambling the basic baseband waveform by applying a first binary randomised sequence where one of the binary values cause transformation to a complex conjugate; modulating the information to be transmitted by applying the scrambled basic baseband waveform for the ON waveform and applying no waveform for the OFF waveform; and transmitting the modulated information.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: June 14, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventor: Miguel Lopez
  • Patent number: 11334320
    Abstract: An execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 17, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Godfrey Da Costa
  • Patent number: 11301215
    Abstract: A computer-implemented method for generating one or more random numbers includes configuring a mapper to feed inputs of a random number generation system using a subset of noise sources from multiple noise sources. The random number generation system generates a random number based on the inputs. The method further includes evaluating the subset of noise sources and detecting that a first noise source from the subset of noise sources has degraded in quality. The method further includes evaluating a second noise source from the available noise sources, the second noise source not being in the subset of noise sources. In response to the second noise source satisfying a predetermined threshold criterion, the first noise source is replaced with the second in the subset of noise sources for providing random bit streams to facilitate generating the random number by the random number generation system.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: April 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kirk David Lamb, Nihad Hadzic
  • Patent number: 11284263
    Abstract: A method, performed by a user application, of creating a trusted bond between a hearing device and the user application is disclosed, wherein the method comprises obtaining first authentication material; transmitting a first authentication request comprising a first authentication type identifier and first authentication data to the hearing device; receiving a first authentication response comprising a sound signal from the hearing device; deriving second authentication material based on the sound signal; determining second authentication data based on the second authentication material; transmitting a second authentication request comprising the second authentication data to the hearing device; receiving a second authentication response comprising an authentication key identifier from the hearing device; storing an authentication key and the authentication key identifier, wherein the authentication key is based on the first authentication material; and connecting the user application to the hearing device us
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 22, 2022
    Assignee: GN Hearing A/S
    Inventors: Allan Munk Vendelbo, Brian Dam Pedersen
  • Patent number: 11281963
    Abstract: An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Raghavan Kumar, Gregory K. Chen, Huseyin Ekin Sumbul, Phil Knag
  • Patent number: 11238881
    Abstract: A method of decomposing digital signals using non-negative matrix factorization by generating an initial set of values in a row in the weight matrix from a ratio of a first function of a first signal of a plurality of digital signals divided by a second function of at least two other signals of the plurality of the digital signals, wherein the row in the weight matrix determines a decomposition of the plurality of digital signals into signal components.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: February 1, 2022
    Assignee: ACCUSONUS, INC.
    Inventors: Elias Kokkinis, Alexandros Tsilfidis
  • Patent number: 11226906
    Abstract: Embodiments of the invention provide a computing device comprising one or more processors, each processor comprising one or more processing unit, said one or more processing units being configured to execute at least one program, each program comprising data and/or instructions, the computing device further comprising, for at least some of the processors, a processor cache associated with each processor, the processor cache being configured to access data and/or instructions comprised in the programs executed by the processor, the computing device comprising: an auxiliary cache configured to access metadata associated with the data and/or instructions comprised in said programs; a security verification unit configured to retrieve, from the auxiliary cache, at least a part of the metadata associated with data and/or instructions corresponding to a memory access request sent by a processor (11) to the processor cache (117).
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 18, 2022
    Assignee: SECURE-IC SAS
    Inventors: Michaël Timbert, Sylvain Guilley, Adrien Facon
  • Patent number: 11216251
    Abstract: A photonic random signal generator includes an incoherent optical source configured to generate an optical noise signal, a filter configured to generate a filtered optical noise signal using the optical noise signal, a coupler, a photodetector, a filter, and a limiter. The coupler couples the filtered optical noise signal and a delayed version of the filtered optical noise signal to generate a first coupled signal and a second coupled signal. The photodetector generates an output signal representative of a phase difference between the filtered optical noise signal and the delayed version of the filtered optical noise signal using the first coupled signal and the second coupled signal. The filter filters the output signal representative of the phase difference to generate an analog random signal. The limiter thresholds the analog random signal based on a clock signal, to generate a digital random signal.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 4, 2022
    Assignee: Raytheon Company
    Inventors: Bishara Shamee, Steven R. Wilkinson
  • Patent number: 11216252
    Abstract: The present disclosure provides a high-speed random number generation method and device, comprising an entropy source module and an entropy sampling module. The entropy source module is an autonomous Boolean network formed by digital logic gates, the network is formed by an XNOR gate and (N?1) XOR gates, wherein the value of N is equal to 3n (n is a positive integer), and the entropy source can generate chaotic signals having wide and flat frequency spectrum. The entropy sampling module of the present disclosure is formed by D flip flops used for sampling and quantizing the chaotic signals to generate random number sequences. The random number sequences generated by the present disclosure can pass test standards (NIST and Diehard statistic tests) of random number industry and have excellent random statistic characteristics.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: January 4, 2022
    Assignee: Taiyuan University of Technology
    Inventors: Jianguo Zhang, Qiqi Zhang, Yuncai Wang, Anbang Wang, Pu Li
  • Patent number: 11182129
    Abstract: Multiple random numbers are generated. The multiple random numbers are N different random numbers. N is a positive integer. Generating the multiple random numbers includes generating a random number array including N storage units. The multiple random numbers are shuffled. A random number obtaining instruction is received. A random number is obtained from the multiple random numbers based on the random number obtaining instruction.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 23, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Jiaxiang Wen
  • Patent number: 11157239
    Abstract: A method of verifying randomness of a bitstream is disclosed. The method includes receiving a bitstream consisting of n consecutive bits and dividing the bitstream into a plurality of bit blocks. In this case, n is a natural number of two or greater, each of the bit blocks consists of m consecutive bits, and m is a natural number of two or greater and is smaller than n. Further, the method includes allocating the plurality of bit blocks to a plurality of core groups in a graphics processing unit (GPU), processing the allocated bit blocks in the plurality of core groups in parallel, calculating random number level values of the allocated bit blocks, and determining whether the bitstream has randomness based on the calculated random number level values. Each of the core groups includes a plurality of cores capable of performing identical or similar tasks without separate synchronization.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 26, 2021
    Assignee: HONGIK UNIVERSITY INDUSTRY-ACADEMIA COOPERATION FOUNDATION
    Inventors: HyungGyoon Kim, Hyungmin Cho, Changwoo Pyo
  • Patent number: 11080021
    Abstract: A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 3, 2021
    Assignee: Cambridge Quantum Computing Limited
    Inventors: Fernando Guadalupe dos Santos Lins Brandão, David John Worrall, Simone Severini
  • Patent number: 11050561
    Abstract: Embodiments of a secure multi-party computation method applicable to any computing node deployed in a distributed network are provided. A plurality of computing nodes are deployed in the distributed network. The plurality of computing nodes jointly participate in a secure multi-party computation based on private data respectively held by the computing nodes. The method includes: generating a computing parameter related to private data held by one computing node based on a secure multi-party computation algorithm; transmitting the computing parameter to other computing nodes participating in the secure multi-party computation for the other computing nodes to perform the secure multi-party computation based on collected computing parameters transmitted by the computing nodes participating in the secure multi-party computation; and creating an audit log corresponding to the computing parameter, the audit log recording description information related to the computing parameter.
    Type: Grant
    Filed: October 31, 2020
    Date of Patent: June 29, 2021
    Assignee: ADVANCED NEW TECHNOLOGIES CO., LTD.
    Inventors: Lichun Li, Shan Yin, Huazhong Wang, Wenzhen Lin
  • Patent number: 11038679
    Abstract: Embodiments of a multi-party secure computation method applicable to any one computing node deployed in a distributed network are provided. A plurality of computing nodes are deployed in the distributed network, the plurality of computing nodes jointly participate in a secure multi-party computation based on respectively held private data, and the computing node that performs the method is connected to a trusted random source. The method includes: obtaining a trusted random number from the trusted random source; performing an operation on the held private data based on the obtained trusted random number to obtain an operation result; and transmitting a computing parameter comprising at least the trusted random number to other computing nodes participating in secure multi-party computation, so that the other computing nodes perform the secure multi-party computation based on collected computing parameters transmitted by the computing nodes participating in the secure multi-party computation.
    Type: Grant
    Filed: October 31, 2020
    Date of Patent: June 15, 2021
    Assignee: ADVANCED NEW TECHNOLOGIES CO., LTD.
    Inventors: Lichun Li, Shan Yin, Huazhong Wang, Wenzhen Lin
  • Patent number: 11036472
    Abstract: A random number generator generates a random number by using at least two algorithms. A security device includes the random number generator. The random number generator includes a random seed generator and a post processor. The random seed generator is configured to receive an entropy signal and to generate a random seed of a digital region generated by using the entropy signal. The post processor is configured to generate a random number from the random seed by using a first algorithm and a second algorithm. A bias property represents unbiasedness of a result value, and a bias property of the first algorithm is different from a bias property of the second algorithm.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Kyoung Kim, Joong-Chul Yoon, Seung-Won Lee
  • Patent number: 11023208
    Abstract: A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chitra K. Subramanian, Ghavam G. Shahidi
  • Patent number: 11010067
    Abstract: Embodiments for defending against speculative side-channel analysis on a computer system are disclosed. In embodiments, a processor includes a decoder, a cache, address translation circuitry, a cache controller, and a memory controller. The decoder decodes an instruction. The instruction specifies a first address associated with a data object, the first address having a first memory tag. The address translation circuitry translates the first address to a second address, the second address to identify a memory location of the data object. The comparator compares the first memory tag and a second memory tag associated with the second address. The cache controller detects a cache miss associated with the memory location. The memory controller, in response to the comparator detecting a match between the first memory tag and the second memory tag and the cache controller detecting the cache miss, loads the data object from the memory location into the cache.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventor: David M. Durham
  • Patent number: 10999331
    Abstract: The present disclosure describes methods and systems for an automatic device discovery and connection protocol via a multi-device experience server. The server may register user devices and associate them with a local network. Upon receiving a request from a media device on the local network, the server may trigger a user device to automatically discover and connect to the media device, increasing speed of discovery and connections, reducing required user control and direction, and enhancing connectivity and communications between the devices, providing new channels for interaction.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: May 4, 2021
    Assignee: Google LLC
    Inventors: Julien Marchand, Ramona Bobohalma, Daniel Kaemmerer, Sana Mithani
  • Patent number: 10938557
    Abstract: An example operation may include one or more of generating an initial seed and allocating one or more authorized bits of the initial seed to a plurality of blocks in a distributed ledger, storing the initial seed and an identification of which authorized bits of the initial seed are allocated to each block of the distributed ledger, receiving a final seed value that is partially generated by each of a plurality of nodes configured to access the distributed ledger based on authorized bits of respective blocks updated by each respective node, and generating a random sequence value based on the final seed value and storing the random sequence value in a block of the distributed ledger.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Si Bin Fan, David Kaminsky, Tao Liu, Jing Lu, Xiao Yan Tang, Jun Zhang
  • Patent number: 10929102
    Abstract: A true random number generator is provided. The true random number generator includes an Exclusive-Or (XOR) circuit and multiple random entropy source circuits. One entropy source sampling process is performed at an output terminal of each of at least two inverters in each of the multiple random entropy source circuits, which is performed by a flip-flop corresponding to the inverter. Sampling results are inputted to an XOR unit in the random entropy source circuit and XOR processing is performed on the sampling results. XOR processing results outputted by the multiple of random entropy source circuits are inputted to the XOR circuit, and the XOR processing is performed on the XOR processing results to obtain a random number sequence.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 23, 2021
    Assignee: TONGXIN MICROELECTRONICS CO., LTD.
    Inventors: Jinhuang Huang, Qiulin Xu, Linlin Su, Yuchen Wang, Chao Yue
  • Patent number: 10922052
    Abstract: A method and apparatus is provided for generating pseudorandom numbers in a way that is deterministic (i.e., repeatable), that passes statistical tests, can have multiple instances of objects generating pseudorandom numbers at the same time. Also, the collection of pseudorandom numbers generated by multiple instances have the same statistical properties as numbers generated by a single instance (i.e., randomness). Embodiments described herein generate pseudorandom values by using a plurality of subsidiary linear congruential generators and combining their outputs nonlinearly. According to embodiments, after their outputs have been combined, a mixing function is applied. Embodiments include an on-demand split method in the style of the SplitMix algorithm.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: February 16, 2021
    Assignee: Oracle International Corporation
    Inventor: Guy L. Steele, Jr.
  • Patent number: 10917235
    Abstract: A method for performing privacy-preserving or secure multi-party computations enables multiple parties to collaborate to produce a shared result while preserving the privacy of input data contributed by individual parties. The method can produce a result with a specified high degree of precision or accuracy in relation to an exactly accurate plaintext (non-privacy-preserving) computation of the result, without unduly burdensome amounts of inter-party communication. The multi-party computations can include a Fourier series approximation of a continuous function or an approximation of a continuous function using trigonometric polynomials, for example, in training a machine learning classifier using secret shared input data.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 9, 2021
    Inventors: Nicolas Gama, Jordan Brandt, Dimitar Jetchev, Stanislav Peceny, Alexander Petric
  • Patent number: 10901695
    Abstract: Disclosed herein is a true random number generator (TRNG). The TRNG includes an enclosure defining a cavity and a cap covering the cavity and having a cap surface exposed to the cavity, the cap surface including radioactive nickel. An electronic sensor within a cavity detects electrons from the decay of the nickel and produces a signal for the detected energy. An amplifier is connected to the sensor and is constructed to amplify the signal and then feeds the signal to a filter. A processor connected to the filter generates a true random number based on the signal. This TRNG may be formed on an integrated circuit.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 26, 2021
    Assignee: RANDAEMON SP. Z O.O.
    Inventors: Jan Jakub Tatarkiewicz, Janusz Jerzy Borodzinski, Wieslaw Bohdan Kuzmicz
  • Patent number: 10862591
    Abstract: Disclosed in some examples, are optical devices, systems, and machine-readable mediums that send and receive multiple streams of data across a same optical communication path (e.g., a same fiber optic fiber) with a same wavelength using different light sources transmitting at different power levels—thereby increasing the bandwidth of each optical communication path. Each light source corresponding to each stream transmits at a same frequency and on the same optical communication path using a different power level. The receiver differentiates the data for each stream by applying one or more detection models to the photon counts observed at the receiver to determine likely bit assignments for each stream.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amer Aref Hassan, Wei-Chen Chen
  • Patent number: 10839642
    Abstract: A gambling hybrid game that provides game history validation. The gambling hybrid game includes an entertainment system engine that provides an entertainment game to a user, a real world engine that provides gambling games to users, and a game world engine that monitors the entertainment game and provides gambling games when appropriate. The entertainment system engine stores game history information in response to a trigger event and provides at least a portion of the stored game history information to a game world engine. The game world engine stores received portion of the game history information. When a request for game history verification is received by the game world engine, the game world engine retrieves the game history information from the entertainment system engine and used the portion of the game history information stored by the game world engine to verify the game history information from the entertainment system engine.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 17, 2020
    Inventors: Miles Arnone, Frank Cire, Clifford Kaylin, Scott Shimmin, Eric Meyerhofer
  • Patent number: 10824397
    Abstract: Disclosed is a method of manufacturing a Random Telegraph Noise source for use within true random number generators, comprising: subjecting a single semiconductor device to stress for a given period of time; and conditioning the single semiconductor device for a given period of time. Also disclosed is a true random number generator and a method of generating true random numbers.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 3, 2020
    Assignee: LIVERPOOL JOHN MOORES UNIVERSITY
    Inventors: Zhigang Ji, Jianfu Zhang
  • Patent number: 10784966
    Abstract: Disclosed in some examples, are optical devices, systems, and machine-readable mediums that send and receive multiple streams of data across a same optical communication path (e.g., a same fiber optic fiber) with a same wavelength using different light sources transmitting at different power levels—thereby increasing the bandwidth of each optical communication path. Each light source corresponding to each stream transmits at a same frequency and on the same optical communication path using a different power level. The receiver differentiates the data for each stream by applying one or more detection models to the photon counts observed at the receiver to determine likely bit assignments for each stream.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amer Aref Hassan, Wei-Chen Chen
  • Patent number: 10778407
    Abstract: A multi-word multiplier circuit includes an interface and circuitry. The interface is configured to receive a first parameter X including one or more first words, and a second parameter Y? including multiple second words. The second parameter includes a blinded version of a non-blinded parameter Y that is blinded using a blinding parameter AY so that Y?=Y+AY. The circuitry is configured to calculate a product Z=X·Y by summing multiple sub-products, each of the sub-products is calculated by multiplying a first word of X by a second word of Y?, and subtracting from intermediate temporary sums of the sub-products respective third words of a partial product P=X·BY, BY is a blinding word included in AY.
    Type: Grant
    Filed: March 25, 2018
    Date of Patent: September 15, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Moshe Alon
  • Patent number: 10749695
    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: August 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Shih-Chang Huang
  • Patent number: 10748454
    Abstract: An assigned share which is a proper subset of a subshare set with a plurality of subshares as elements, and meta information indicating values according to the elements of the subshare set or indicating that the elements are concealed values are stored. When a value according to a provided corresponding value according to a subset of the assigned share is not obtained from the meta information, a provided value according to the provided corresponding value obtained from the subset of the assigned share is outputted. When a value according to an acquired corresponding value according to a subset of an external assigned share, which is a proper subset of the subshare set, is not obtained from the meta information, input of an acquired value according to the acquired corresponding value is accepted. When the acquired value is inputted, a secret share value is obtained at least using the acquired value.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 18, 2020
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventor: Dai Ikarashi
  • Patent number: 10740068
    Abstract: A modular reduction device particularly for cryptography on elliptical curves. The device includes a Barrett modular reduction circuit and a cache memory in which the results of some precalculations are carried out. When the result is not present in the cache memory, a binary division circuit makes the precalculation and stores the result in the cache memory.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 11, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Thomas Hiscock
  • Patent number: 10698658
    Abstract: Apparatuses and methods disclosed herein relate to detecting a signal generated by a spin torque oscillator (STO). The signal is outputted, wherein the signal includes a direct current (DC) component, a wide bandwidth noise component, and an STO oscillating radio frequency (RF) component. The signal is filtered, wherein the filtering removes the DC component and the STO oscillating RF component, leaving the wide bandwidth noise component. A value of the wide bandwidth noise component is converted into a binary value, and a bit from the binary value is selected and combined with another bit to form a random number.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 30, 2020
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, Lihong Zhang, WenXiang Xie, Quan Li
  • Patent number: 10685150
    Abstract: An experiment manager is discussed for the design and execution of numerical experiments in composite simulation models, such as those created using the Smarter Planet Platform for Analysis Simulation of Health (Splash). The experiment manager independently elicits experiment-related information from each contributor of a component model, and uses this information to subsequently assist the creator of a composite model in selecting experimental factors, creating experimental designs based on these factors, and executing the experiments. This functionality permits cross-disciplinary modeling, simulation, sensitivity analysis and optimization in the setting of complex systems.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicole C Barberis, Peter J Haas, Paul P Maglio, Piyaphol Phoungphol, Patricia G Selinger, Wang-Chiew Tan, Ignacio G Terrizzano
  • Patent number: 10678511
    Abstract: A method for using cellular automata to generate quality pseudo-random numbers, which may be used in cryptographic and other applications. A cellular automaton is a decentralized computing model that enables the performance of complex computations with the help of only local information. In general, cellular automata comprise a plurality of identical basic memory building blocks that are discrete in time and space, where the structure evolves over time according to a local transition rule. Cellular automata can be used in information security as an alternative for classic Feedback Shift Registers (FSRs) for pseudo-random sequence generation. The outputs of a pair of linear FSRs (LFSRs) act as continuous inputs to the two boundaries of a one-dimensional or two-dimensional elementary cellular automata.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 9, 2020
    Inventor: Karim Salman
  • Patent number: 10656916
    Abstract: Embodiments include apparatuses, methods, and systems for a random number generator that includes an entropy source. The entropy source may be coupled to a deterministic feedback circuit and a stochastic feedback circuit. The deterministic feedback circuit may include detection logic to detect when a bit of the output signal of the entropy source has registered, a pre-delay feedback path to cause the entropy source to power off responsive to the detection, and a post-delay feedback path to cause the entropy source to power on, after the entropy source is powered off, to generate a second bit of the output signal. The post-delay feedback path may include one or more delay cells that are bypassed by the pre-delay feedback path. Other circuits and techniques related to random number generators are also described. Further embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Rachael J. Parker, Calvin Chiem
  • Patent number: 10635401
    Abstract: A method for optimal arrangement of a random generator on an electronic component, which includes a programmable integrated circuit and a basic structure consisting of a plurality of basic blocks, wherein during an initialization phase, starting from a starting configuration for a respective current arrangement of the random generator, the following are performed with a predefined number of repetitions, i.e., a predefined test sequence is performed for the current arrangement of the random generator, a test result is forwarded to a reconfiguration module and the current arrangement on the electronic component is reconfigured via the reconfiguration module, where upon each repetition, the test result of the current arrangement of the random generator is compared with the test result of a previous arrangement, and the current arrangement is saved in the reconfiguration module, if the test result for the current arrangement has a better test result than the previous arrangement.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 28, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Hinterstoisser, Martin Matschnig, Herbert Taucher
  • Patent number: 10637597
    Abstract: A network of computing devices includes a timing reference, a free-run node, and an aggregator. The reference calculates a first communication packet having a reference timestamp and reference data, and transmits the first packet to the free-run node. The free-run node receives the first packet from the timing reference, calculates a second packet having metadata that includes the reference timestamp, a sparse hash value calculated from the reference data, and a free-run node timestamp, and publishes the second packet to the aggregator. The aggregator receives the second packet and calculates a compensation value from the reference timestamp, the sparse hash value, and the free-run node timestamp. Computer-implemented methods include the free-run node receiving the compensation value and updating its local clock based on the compensation value. Other methods include the aggregator determining an optimal packet path through a network of computing devices based on the metadata.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 28, 2020
    Assignee: LUMINOUS CYBER CORPORATION
    Inventors: Charles F. Barry, Nick J. Possley, Brendan P. Keller, Sumanta Saha
  • Patent number: 10635399
    Abstract: A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 28, 2020
    Assignee: CASSY HOLDINGS LLC
    Inventor: Patrick D. Ross
  • Patent number: 10628127
    Abstract: Provided is an Internet protocol (IP) generation method. The method is performed by an IP generation apparatus comprising one or more processors and memory and includes: forming a plurality of initialized partial numbers by dividing a decimal number indicating a count of IP addresses that can be generated; changing the partial numbers according to a predetermined rule; generating an IP decimal number by linking the changed partial numbers; generating a random IP address from the IP decimal number; and generating a plurality of different random IP addresses with improved time efficiency, by sequentially repeating the changing of the partial numbers, the generating of the IP decimal number and the generating of the random IP address.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 21, 2020
    Assignee: KOREA INTERNET & SECURITY AGENCY
    Inventors: Hwan Kuk Kim, Tae Eun Kim, Dae Il Jang, Eun Hye Ko, Jee Soo Jurn, Sa Rang Na, Eun Byul Lee
  • Patent number: 10601711
    Abstract: Certain hash-based operations in network devices and other devices, such as mapping and/or lookup operations, are improved by manipulating a hash key prior to executing a hash function on the hash key and/or by manipulating outputs of a hash function. A device may be configured to manipulate hash keys and/or outputs using manipulation logic based on one or more predefined manipulation values. A similar hash-based operation may be performed by multiple devices within a network of computing devices. Different devices may utilize different predefined manipulation values for their respective implementations of the manipulation logic. For instance, each device may assign itself a random mask value for key transformation logic as part of an initialization process when the device powers up and/or each time the device reboots. In an embodiment, described techniques may increase the entropy of hashing function outputs in certain contexts, thereby increasing the effectiveness of certain hashing functions.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 24, 2020
    Assignee: Innovium, Inc.
    Inventors: William Brad Matthews, Puneet Agarwal
  • Patent number: 10592240
    Abstract: An electronic apparatus includes a permutation circuit and an arbitration circuit. The permutation circuit is configured to apply to an input vector a permutation selected from a plurality of predefined permutations in response to a control word. The arbitration circuit is configured to receive a vector of requests for a resource, to instruct the permutation circuit to apply a randomly-selected permutation to the vector of requests, by configuring the permutation circuit with a corresponding randomly-selected control word so as to produce a permuted vector, to select an element of the permuted vector, to apply to the permuted vector an inverse of the randomly-selected permutation so as to produce an inversely-permuted vector, to identify an element of the inversely-permuted vector to which the selected element of the permuted vector is mapped, and to assign the resource to a client corresponding to the identified element of the inversely-permuted vector.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 17, 2020
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Liron Mula, Gil Levy
  • Patent number: 10578947
    Abstract: A media-defined optical logic circuit composed of a set of light-transmitting polyhedral prisms arranged so that a pair of adjacent prisms can exchange photonic signals through adjacent surfaces. Each prism contains one or more quantum dots that, when excited by a photonic signal received from an adjacent prism, respond by emitting light that becomes an incoming photonic signal for an adjacent prism. Photonic signals are propagated through the circuit in this manner along light-guide paths created by shading certain surfaces to render them fully or partially opaque. The prisms and shading are arranged such that the circuit performs a certain logic function. When the circuit receives a set of photonic input signals representing a binary input value, the circuit responds by emitting a set of photonic output signals that represent a binary output value determined by performing the logic function upon the binary input value.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pablo F. Barquero Garro, Ricardo A. Golcher, Franz F. Liebinger, Meller J. P. Nunez
  • Patent number: 10567419
    Abstract: This document describes, among other things, a computer-implemented method for improving the security of one or more computing systems. The method can include receiving, at a computing system, first code that defines at least a portion of an electronic resource that is to be served to a client computing device. The method can include generating code that defines a challenge to be solved by the client computing device, in which the code is arranged to cause the client computing device to determine values for one or more parameters that comprise a solution to the challenge, and the values for the one or more parameters that comprise the solution to the challenge may be required for the client computing device to make valid requests to initiate one or more web-based transactions. The computing system can determine whether particular values for the parameters comprise a valid solution to the challenge.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: February 18, 2020
    Inventor: Marc R. Hansen
  • Patent number: 10520975
    Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 31, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan
  • Patent number: 10514894
    Abstract: A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 24, 2019
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Hongzhen Fang, Yuejun Zhang
  • Patent number: 10508785
    Abstract: A light system for a fireplace, including a plurality of lights, and a chaos circuit coupled to the plurality of lights. The chaos circuit is configured to provide signals to the plurality of lights to provide naturalistic flame lighting and naturalistic ember lighting.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 17, 2019
    Assignee: HNI Technologies Inc.
    Inventors: Charles Miller, David Lyons, Suman Minnaganti