Abstract: The disclosed computer-implemented method for preparing a secure search index for securely detecting personally identifiable information may include (i) receiving, at a computing device, a dataset including a record, where the record has a field including a value describing personally identifiable information and (ii) performing, at the computing device, a security action. The security action may include (i) generating, using a perfect hash function, a respective hashed key from the value and (ii) adding, to the secure search index (a) the respective hashed key or (b) a subsequent hashed key created from the respective hashed key. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method is disclosed. The method includes receiving, by a computer node in a network including a plurality of computer nodes, a plurality of data values from the plurality of computer nodes. Each computer node can create a data value based on a time that the computer node in the plurality of computer nodes takes to perform a function. The computer node can then provide the data values or derivatives thereof as random values to an entropy pool of random values. The computer node can then select a random value from the entropy pool and initiate use of the random value in an operation.

Abstract: A pseudo-random number generation circuit device includes a pseudo-random number generation circuit including a logic circuit configured based on rule data that generates a next random number value from a current random number value, a cycle detection circuit that detects, based on a seed, an end of a cycle of random numbers, which are generated by the pseudo-random number generation circuit, and a rule data generation circuit that generates new rule data at a first trigger, at which the cycle detection circuit detects the end of the cycle of random numbers, to output the new rule data to the pseudo-random number generation circuit, wherein the cycle detection circuit stores a random number value, which is generated by a new logic circuit configured based on the new rule data, as the seed.

Abstract: An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

Abstract: The technical idea of the present invention relates to a method for forming a virtual private network based on post-quantum cryptography and a virtual private network operating system performing the same. The method for forming a virtual private network performing by a first device to form a virtual private network with a second device according to an embodiment of the present invention comprises the steps of: requesting a handshake for forming the virtual private network; receiving a signature and a public key; authenticating the second device by using the signature; generating a symmetric key by using the public key; and performing virtual private network communication by using the symmetric key, wherein the public key is generated by using at least one key vector corresponding to a grid.

Abstract: A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.

Abstract: Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver.

Abstract: Various embodiments of a distributed numeric sequence generation system and method are described. In particular, some embodiments provide high-scale, high-availability, low-cost and low-maintenance numeric sequence generation in a non-Relational Database Management System (“non-RBMS”) system by sacrificing monotonicity. The distributed numeric sequence generation system comprises a plurality of hosts, wherein individual hosts implement a cache for caching a plurality of numeric sequences. A host can access master numeric sequence data at a separate system to obtain values for numeric sequences to store in its cache. A host can receive a request from a client for values of a numeric sequence, and provide to the client the values for the numeric sequence from its cache. Some embodiments of the distributed numeric sequence generation system and method are also equipped to vend recyclable and bounded numeric sequences.

Abstract: Methods for randomly storing data received at a plurality of silicon-based devices included in a matrix-computer-cluster are provided. The silicon-based devices may be arranged in predetermined rows within the matrix-computer-cluster. The matrix-computer-cluster may include a matrix formation of x, y and z coordinates. Methods may encapsulate a first device in a first quantum case. Methods may receive a data element at the first device. Methods may intercept the data element at the first case. Methods may generate a random number sequence at a first quantum random number generator included in the first case. The random number sequence may identify a set of x, y and z coordinates. Methods may determine a second device located within the matrix-computer-cluster that corresponds to the identified set of x, y and z coordinates. Methods may include transmitting the data element to second device, and storing the data element at the second device.

Abstract: Some embodiments are directed to an electronic cryptographic device arranged to perform a cryptographic operation on input data obtaining output data. The cryptographic device stores an internal state as sets of shares. Fourier coefficients corresponding to the sets of shares satisfy a predetermined relationship among them. The cryptographic operation is performed by repeatedly updating the internal state.

Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.

Abstract: A pseudorandom number is obtained from a pseudorandom number generator. A first register input is created using the pseudorandom number. The first register input is inserted into a shift register which also comprises a second register input. A first digit of the first register input and a second digit of the second register input are selected from the shift register. A seed is created using the first digit and the second digit. The seed is input into the pseudorandom number generator. A newly generated pseudorandom number is obtained from the pseudorandom number generator.

Abstract: Systems and associated methods for highly parallel processing of parameterized simulations are described. Embodiments permit processing of stochastic data-intensive simulations in a highly parallel fashion in order to distribute the intensive workload. Embodiments utilize methods of seeding records in a database with a source of pseudo-random numbers, such as a compressed seed for a pseudo-random number generator, such that seeded records may be processed independently in a highly parallel fashion. Thus, embodiments provide systems and associated methods facilitating quicker data-intensive simulation by enabling highly parallel asynchronous simulations.

Abstract: Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver.

Abstract: A method for opening and/or using at least one vehicle may include receiving, by a mobile terminal, an identifier assigned to a target vehicle. The identifier may be transmitted to a server, and a key data set may be received from the server. The key data set and/or a code based on the key data set may be transmitted as a remote code to the target vehicle. The target vehicle may generate at least one local code after receiving the remote code, and may compare the remote code to the local code(s). The target vehicle may be opened and/or released, or a vehicle command may be executed if at least one of the local codes corresponds to the remote code.

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

Abstract: A building management system comprising an integrated sensor and control system integrated on a single application specific integrated circuit (ASIC). The ASIC combines sensor inputs necessary to monitor ambient light levels, light color, occupation/motion sensors, security sensors, temperature and humidity, barometric pressure, smoke and toxic substance sensors, and a processor to receive the sensor inputs and deliver control output signals to effect changes and make settings to each of the environmental systems that are monitored. The ASIC also provides communication and control security for the building management system, preventing hostile intrusions into the system. The storage, intelligence and processing all reside within the ASIC.

Abstract: A processor unit can rapidly search a string of characters. The processor unit includes vector registers each having M vector elements, each having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each upper diagonal of the matrix of comparators and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. The processor unit result generating logic generates, using the resulting bit vector, an indication of a substring of the target string that matches a fragment of the reference string.

Abstract: A device for controlling a communication network having a plurality of terminals for a data communication is provided. The device comprises a control unit configured to decouple a data plane and a control plane of the data communication and to modify at least one characteristic of the communication network which is visible from the outside of the communication network during a communication session using the decoupled control plane.

Abstract: Apparatus and method for managing entropy in a cryptographic processing system. In some embodiments, a first block of conditioned entropy is generated from at least one entropy source. The first block of conditioned entropy is subjected to a first cryptographic process to generate cryptographically secured entropy which is stored in a memory. The cryptographically secured entropy is subsequently retrieved from the memory and subjected to a second cryptographic process to generate a second block of conditioned entropy, which is thereafter used as an input in a third cryptographic process such as to encrypt or decrypt user data in a data storage device. The first cryptographic process may include an encryption algorithm to generate ciphertext and a hash function to generate a keyed digest value, such as an HMAC value, to detect tampering with the ciphertext by an attacker. The second cryptographic process may decrypt or further encrypt the ciphertext.

Abstract: A random number acquiring unit 15 obtains a first sequence that comprises values of digits of a random number represented by a binary number as elements. A logical product arithmetic unit 16 obtains a third sequence that is results of elementwise logical product operation between the first sequence and a second sequence that comprises values of digits of one or more Mersenne numbers represented by one or more binary numbers and a zero value as elements.

Abstract: Methods and systems are disclosed for generating more random data or ensuring more random data than provided by single sources. Entropy is gathered among multiple random or pseudo-random sources at different frequencies. The entropy is pushed, pulled, or otherwise presented to a pseudo-random number generator when there is enough entropy. The determination of enough entropy can be through a modified Hamming distance. The frequencies of polling for entropy from the entropy sources can be jittered by a random amount.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

Abstract: The method for generating a random bit sample involves a quantum tunneling barrier. The method generally has: generating a current of charges tunneling across said quantum tunneling barrier, the current of the tunneled charges having an instantaneous level varying randomly due to quantum tunneling fluctuations and forming a raw signal; from said raw signal, obtaining a raw bit sample having a first bit number n, the first bit number n being an integer; extracting the randomness out of the raw bit sample into the random bit sample, the random bit sample having a second bit number m being smaller than the first bit number n, said extracting being based on calibration data comprising at least a quantum contribution value of said quantum tunneling fluctuations in said raw bit sample; and on an external contribution value in said raw bit sample.

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

Abstract: Generating non-compressible data streams is disclosed, including: receiving an initialization parameter; determining at least one constrained prime number; generating a sequence comprising a plurality of byte values based at least in part on the initialization parameter and the constrained prime number; determining a rotation value; and rotating a portion of the sequence based on a rotation value to form a rotated sequence, wherein the rotated sequence comprises byte values substantially defeating a predictive compression algorithm.

Abstract: Generating non-compressible data streams is disclosed, including: receiving a sequence comprising a plurality of byte values calculated from an initialization parameter and a constrained prime number; determining a data structure index from a plurality of bits within at least one of the plurality of byte values; retrieving a rotation value from a data structure, wherein the rotation value is stored in the data structure at the data structure index; and rotating a portion of the sequence based on a rotation value to form a rotated sequence, wherein the rotated sequence comprises byte values substantially defeating a predictive compression algorithm.

Abstract: An apparatus for balancing consumption of random data, comprising an entropy manager operable to: responsive to receipt of a request for random data, monitor one or more events associated with a plurality of entities and access one or more rules; determine whether a higher level of entropy associated with the random data is required by analyzing the one or more events in accordance with the one or more rules; responsive to a determination that a higher level of entropy is not required, set an entropy state associated with the entropy to a lower level of entropy and obtain random data from an entropy source having a lower level of entropy; and responsive to a determination that a higher level of entropy is required, switch an entropy state associated with the entropy to a higher level of entropy and obtain random data from an entropy source having a higher level of entropy.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of managing an Application Service Platform (ASP) session. For example, an apparatus may include a first ASP to communicate with a second ASP via a wireless Peer-to-Peer (P2P) connection over a P2P link to manage an ASP-session between a first device including the first ASP and a second device including the second ASP. The first ASP may communicate with the second ASP a message to close the ASP-session, the message including a reason field including an indication of a reason for closing the ASP-session.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of managing an Application Service Platform (ASP) session. For example, an apparatus may include a first ASP to communicate with a second ASP via a wireless Peer-to-Peer (P2P) connection over a P2P link to manage an ASP-session between a first device including the first ASP and a second device including the second ASP. The first ASP may communicate with the second ASP a message to close the ASP-session, the message including a reason field including an indication of a reason for closing the ASP-session.

Abstract: A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.

Abstract: A data processing system includes a module for generating and distributing random masks to a number of cryptographic accelerators while providing for fewer total interconnects among the components generating the random masks. The module segments the tasks associated with generating random masks across a number of modules and blocks such that routing and timing problems can be minimized and layout can be optimized. A method for generating and distributing random masks to a number of cryptographic accelerators is also provided. The random masks are utilized by cryptographic accelerators to protect secret keys, and data associated with those keys, from discovery by unauthorized users.

Abstract: The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

Abstract: In accordance with one or more aspects, an initial output string is generated by a random number generator. The initial output string is sent to a random number service, and an indication of failure is received from the random number service if the initial output string is the same as a previous initial output string received by the random number service. Operation of the device is ceased in response to the indication of failure. Additionally, entropy estimates for hash values of an entropy source can be generated by an entropy estimation service based on hash values of various entropy source values received by the entropy estimation service. The hash values can be incorporated into an entropy pool of the device, and the entropy estimate of the pool being updated based on the estimated entropy of the entropy source.

Abstract: Methods and apparatus are provided for generation of forward secure pseudorandom numbers. A forward secure pseudorandom number is generated by obtaining a first state si corresponding to a current leaf node vi in a hierarchical tree, wherein the current leaf vi produces a first pseudorandom number ri?t and wherein the hierarchical tree comprises at least one chain comprised of a plurality of nodes on a given level of the hierarchical tree; updating the first state si to a second state si+t corresponding to a second leaf node vi+t; and computing a second pseudorandom number ri+t?1 corresponding to the second leaf node vi+t. The variable t may be an integer greater than one. Updating the state does not require generation of all pseudorandom numbers produced by leaf nodes between the current leaf node vi and the second leaf node vi+t.

Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a second operand to be used. The machine instruction is executed, and execution includes obtaining a modifier field of a register associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand; using a 512 bit secure hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in a parameter block.

Abstract: Embodiments of an invention for cryptographic key generation using a stored input value and a stored count value have been described. In one embodiment, a processor includes non-volatile storage storing an input value and a count value, and logic to generate a cryptographic key based on the stored input value and the stored count value.

Abstract: A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

Abstract: A system and method of generating uniform and independent random numbers is given by comprising two distinct odd primes that give an odd integer and an even integer, together with by taking an integer exponent and an integer exponent, by forming the composite modulus by taking a primitive root modulo and a primitive modulo and giving the multiplier modulo by either the system of congruence relations, any of which determines the multiplier modulo uniquely, by taking an initial value coprime. The method generates the sequence of integers by recursive congruence relations and gives an output of uniform and independent random numbers.

Abstract: An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.

Abstract: A random number generation apparatus includes: a random noise generation element comprising a source region and a drain region, a tunnel insulation film, a gate electrode, and a charge trap portion provided between the tunnel insulation film and the gate electrode and being capable of trapping charges, random noise being generated in a drain current flowing between the source region and the drain region on the basis of charges trapped in the charge trap portion; a random number conversion circuit for converting random noise generated from the random noise generation element to a random number; a first test circuit for performing a random number test to test quality of the random number output from the random number conversion circuit; and an initialization circuit for pulling out charges in the charge trap portion of the random noise generation element to the semiconductor substrate through the tunnel insulation film and thereby initializing the charge trap portion.

Abstract: Embodiments of methods and systems for producing random values include a first module that provides a random data request (e.g., a request for an unspecified length of random data) to a random number generator. The random number generator generates random data in response to the random data request, and multiple random values derived from the random data are stored in a buffer. In response to receiving a request for a random value (e.g., an initialization vector), the first module produces the random value based on the multiple random values stored in the buffer. The system also may be configured to receive requests for other types of random values, and to fulfill those requests using random data that is not buffered (e.g., random data that is received directly from the random number generator in response to a request for a specified length of random data).

Abstract: Two or more numerical samples are read from a storage location (or many storage locations) and the samples are compared to generate a single bit of entropy. This method is repeated to populate two arrays which are also compared to generate a single bit. Comparison of the arrays is also repeated to generate a sequence of bits which are formed into computer words. The words are combined with a shift register to generate a seed block array of any length. The seed block array is used to seed a pseudo random number generator. The storage location is a register, accumulator, buffer, clock, address, memory location, etc., that changes periodically. Comparison may be performed by counting the number of certain types of bits in the two values and returning a one or zero depending upon the count.

Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a second operand to be used. The machine instruction is executed, and execution includes obtaining a modifier field of a register associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand; using a 512 bit secure hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in a parameter block.

Abstract: Systems and methods for accelerating AES encryption and decryption operations are provided. Aspects of the method may include time multiplexing a plurality of substitution boxes (S-boxes) for instantaneous key generation and byte substitution operations. Bytes may be substituted in at least a portion of a current security key information and at least a portion of a subsequent security key information within said plurality of S-boxes. The current security key may comprise 128 bits, 192 bits or 256 bits and the portion of the current security key may comprise 32 bits. The substituted portion of the security key information may be communicated to a key generator. The subsequent security key information may be generated utilizing the substituted portion of the current security key information. The current security key information may then be stored.

Abstract: A random number generating method includes sending a signal source for outputting a data sequence and randomly retrieving a segment of data having an operation length as a seed; converting the seed into a first operation value, determining whether a difference between the first operation value and a second operation value is larger than a threshold value, and determining whether a total number of times the first operation value has been inputted into the operation value processing step is larger than a predetermined value. The first operation value is reset by a reset algorithm; otherwise the sample selection step is re-performed. The operation values are converted into a random number. A total number of bits of the random number is calculated. The operation value setting step is performed or a latest random number having a length equal to the operation length is set as the seed.

Abstract: In embodiments of scalable random number generation, a system includes one or more entropy pools that combine entropy data, which is derived from entropy sources based on event data. A root pseudo-random number generator (PRNG) maintains a seeded entropy state that is reseeded by the entropy pools, and a seed version identifier updates to indicate a current seed version of the root PRNG. Processor PRNGs are instantiated one each per logical processor in a kernel of the system, where each processor PRNG maintains a PRNG entropy state that is reseeded from the root PRNG, and a processor PRNG generates a random number from a respective PRNG entropy state when invoked.

Abstract: For generating a random number in a disk drive, a seed is generated from a respective sector number for each of at least one sector of the disk drive. The random number is calculated using the seed. The seed that is generated with enhanced unpredictability and complexity is used to generate the random number for secure data cryptography within the disk drive.