Plural Parallel Outputs Patents (Class 708/256)
  • Patent number: 11256477
    Abstract: A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 22, 2022
    Assignee: Cambridge Quantum Computing Limited
    Inventors: Fernando Guadalupe dos Santos Lins Brandão, David John Worrall, Simone Severini
  • Patent number: 9928036
    Abstract: A processor includes an execution unit to generate a random number. The execution unit includes entropy source circuits, correlation circuits, and an extractor circuit. The entropy source circuits include all-digital components and are to generate an initial randomized bit stream. The correlation circuits are to remove correlations from the initial randomized bit stream to yield an intermediate randomized bit stream. The extractor circuit is to select a subset of the intermediate randomized bit stream as a random output of the execution unit.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, David Johnston, Sudhir K. Satpathy
  • Patent number: 9916132
    Abstract: A random number generation system, comprising: a light source configured to generate light pulses and a driving unit configured to drive said light source such that the phase of each light pulse has a random relationship to the phase of each subsequently generated light pulse, and such that each light pulse is generated with at least two local maxima in the temporal intensity profile.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Zhiliang Yuan, Marco Lucamarini, Andrew James Shields
  • Patent number: 9575726
    Abstract: A bit sequence generator for generating a bit sequence defined by a generating function and an initial state of the generating function comprising a plurality of state machines and a multiplexer. Each state machine of the plurality of state machines generates a time-interleaved bit sequence, wherein a state machine generates a bit of the time-interleaved bit sequence for a current time step based on at least one bit generated by the state machine for a preceding time step, the generating function of the bit sequence to be generated, and the initial state of the generating function and independent from a time-interleaved bit sequence generated by another state machine of the plurality of state machines. Further, a multiplexer selects successively one bit from each generated time-interleaved bit sequence in a repetitive manner to obtain the bit sequence defined by the generating function and the initial state of the generating function.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: February 21, 2017
    Assignee: Advantest Corporation
    Inventor: Jochen Rivoir
  • Patent number: 9157961
    Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 13, 2015
    Assignee: Synopsys, Inc
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Gregory A. Maston
  • Patent number: 9128791
    Abstract: A method of providing random number streams to a process includes determining two or more program contexts within a process. Each of the program contexts may include code that calls for one or more random numbers. For each of at least two of the program contexts, a random number stream is provided to the process. The random number stream for each program context is based on the determined program context and is distinct from the random number stream for the other program contexts in the process.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 8, 2015
    Assignee: Board of Regents of the University of Texas System
    Inventor: Rajendra V. Boppana
  • Publication number: 20150113028
    Abstract: A method of assessing parallel random number streams includes mixing two or more parallel random number streams. Mixing the parallel random number streams may include pairing at least one of the random number streams with other random number streams. For each mixed random number stream, an inter-stream correlation value may be computed based on a correlation among the random number steams used. A quality metric for the parallel random number streams may be determined from inter-stream correlation values for the two or more mixed streams created from the parallel random number streams. A quality metric for a single random number stream may be computed by segmenting the single random number stream into multiple substreams and applying the methods of mixing streams and computing quality metric in the case of parallel streams.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 23, 2015
    Inventors: Rajendra V. Boppana, Ram C. Tripathi
  • Patent number: 8949493
    Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 3, 2015
    Assignee: Altera Corporation
    Inventors: Curt Wortman, Chong H. Lee, Huy Ngo
  • Patent number: 8756264
    Abstract: A method of generating pseudo-random numbers on a parallel processing system comprises generating a plurality of sub-streams of pseudo-random numbers, wherein the sub-streams are generated in parallel by one or more co-processors, and providing the plurality of sub-streams to respective processing elements, wherein the respective processing elements employ the plurality of sub-streams to execute an application.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 17, 2014
    Assignee: Google Inc.
    Inventors: Myles A. Sussman, William Y. Crutchfield, Matthew N. Papakipos
  • Patent number: 8745113
    Abstract: The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 3, 2014
    Assignee: Altera Canada Co.
    Inventor: Junjie Yan
  • Patent number: 8583711
    Abstract: A random number generation system comprising one or more ring oscillators configured to generate entropy due to accumulated phase drift. A random number generator can include a ring oscillator configured to switch between a first state in which a signal of the ring oscillator oscillates between logic levels, and a second state in which the signal at least partially settles to one of the logic levels. The random number generator can also include a counter configured to measure a count of pulses of the signal and a whitener mechanism configured to receive the signal from the ring oscillator, latch a logic level of the signal from the ring oscillator, latch the count of pulses from the counter, and generate a random number based on the logic level and the count of pulses. Corresponding methods may also be performed.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 12, 2013
    Assignee: Seagate Technology LLC
    Inventor: Laszlo Hars
  • Patent number: 8484481
    Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jesse E. Craig, Stanley B. Stanski, Scott T. Vento
  • Patent number: 8443022
    Abstract: A random number generating apparatus and method for generating a metastable state signal by using logic gates include a metastable state generating unit generating and outputting a metastable state signal; an amplifying unit receiving the metastable state signal from the metastable state generating unit, amplifying the received metastable state signal, and outputting the amplified metastable state signal; and a sampling unit receiving the amplified metastable state signal and a sampling clock, and sampling and outputting the amplified metastable state signal according to the sampling clock.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ihor Vasyltsov, Eduard Hambardzumyan, Bohdan Karpinskyy
  • Patent number: 8433740
    Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m?1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 30, 2013
    Assignee: Anritsu Corporation
    Inventors: Takashi Furuya, Masahiro Kuroda, Kazuhiko Ishibe
  • Patent number: 8218760
    Abstract: Method and device for generating factors of a RSA modulus N with a predetermined portion Nh, the RSA modulus comprising at least two factors. A first prime p is generated; a value Nh that forms a part of modulus N is obtained; a second prime q is generated in an interval dependent from p and Nh so that pq is a RSA modulus that shares Nh; and information enabling the calculation of the modulus/V is outputted.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: July 10, 2012
    Assignee: Thomson Licensing
    Inventor: Marc Joye
  • Patent number: 8166086
    Abstract: A random number generator uses the output of a true random generator to alter the behavior of a pseudo-random number generator. The alteration is performed by a mixing logic that builds a random seed for the pseudo-random number generator and includes a generator of an alteration signal, the generation of which exploits the random instant of arrival of the bits outgoing from the true random generator. The alteration signal is obtained by processing the seed by means of the pseudo-random sequence.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: April 24, 2012
    Assignee: Telecom Italia S.p.A.
    Inventors: Giovanni Ghigo, Loris Bollea
  • Patent number: 8037117
    Abstract: Disclosed is a method for deriving random numbers at a higher speed than ever before while maintaining desired randomness without spoiling uniformity of the occurrence frequency of each random number. One pulse included in one of two or more mutually-independent random pulse sequences and one pulse included in one of the remaining random pulse sequences are used, respectively, as a start pulse and a stop pulse. Then a time interval between the start pulse and the stop pulse is measured, and the measured value is output. The pulses temporally occur in a random manner, and therefore the obtained sequence of numerical values becomes random numbers. Specifically, in FIG. 1, time intervals t1 to t4 are measured, and these measured values (in FIG. 1, four values) are derived as random numbers.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: October 11, 2011
    Assignees: Leisure Electronics Technology Co., Ltd., Institute for Advanced Studies Co., Ltd.
    Inventor: Takeshi Saito
  • Patent number: 8023649
    Abstract: A compact apparatus for generation of desired pseudorandom sequences with controllable period. The apparatus includes two-dimensional cellular automata for generating a first sequence, 2-by-L cellular automata for generating a second sequence, adders for performing bit-to-bit mod2 sum of the first sequences and the second sequences, and a buffer for buffering the resultant sequences from the adders.
    Type: Grant
    Filed: September 5, 2005
    Date of Patent: September 20, 2011
    Assignee: Sony Corporation
    Inventors: Miodrag J. Mihaljevic, Jouji Abe
  • Patent number: 7979482
    Abstract: A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: July 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Rainer Goettfert
  • Patent number: 7849122
    Abstract: Various embodiments of the present invention are directed to self-authenticating, quantum random bit generators that can be integrated into an optoelectronic circuit. In one embodiment, a quantum random bit generator comprises a transmission layer that includes an electromagnetic radiation source coupled to a waveguide branching into a first, second, and third waveguides. The radiation source generates pulses of electromagnetic radiation in a first polarization state. Polarization rotators are operably coupled to the second and third waveguides and rotate pulses transmitted in the second waveguide into a second polarization state and rotate pulses transmitted in the third waveguide into a third polarization state. The system control generates a sequence of bits based on polarization basis states of the pulses transmitted in the first waveguide, and tomographically authenticates randomness of the sequence based on polarization basis states of the second and third pulses.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: December 7, 2010
    Assignee: Hewlett-Packard Developmemt Company, L.P.
    Inventors: Marco Fiorentino, Raymond G. Beausoleil, Sean M. Spillane, Robert Newton Bicknell
  • Patent number: 7817707
    Abstract: Disclosed is an apparatus for generating a ranging pseudo noise (PN) code used in a base station of a portable internet system of an orthogonal frequency division multiplexing access scheme, wherein a ranging pseudo noise mask value is generated using a cell ID number, and then the generated ranging pseudo noise mask value is stored in a memory. A final ranging PN code is generated using the stored ranging PN mask value and a status of a pseudo random binary sequence for generating a ranging PN code. With such a structure, the maximal 256-numbered ranging PN code values can be obtained simultaneously with each 144 bit-length.
    Type: Grant
    Filed: November 11, 2005
    Date of Patent: October 19, 2010
    Assignees: Samsung Electronics Co., Ltd., Electronics and Telecommunications Research Institute, KT Corporation, SK Telecom Co., Ltd., KTFreetel Co., Ltd., Hanaro Telecom., Inc.
    Inventors: Kyung-Yeol Sohn, Chang-Wahn Yu, Youn-Ok Park
  • Patent number: 7747020
    Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventor: Wajdi K. Feghali
  • Patent number: 7721086
    Abstract: A cryptographic system (500) includes cryptographic sub-units (510) and associated input buffers (520) connected to a scheduler (530) and a reassembler (540). The scheduler (530) receives packets, where each of the packets includes one or more data blocks, and assigns each of the packets to one of the sub-units (510). The input buffers (520) temporarily store the packets from the scheduler (530). Each of the sub-units (510) performs a cryptographic operation on the data blocks from the associated input buffer (520) to form transformed blocks. The reassembler (540) receives the transformed blocks from the sub-units (510), reassembles the packets from the transformed blocks, and outputs the reassembled packets in a same order in which the packets were received by the scheduler (530).
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 18, 2010
    Assignee: Verizon Corporate Services Group Inc. & BBN Technologies Corp.
    Inventor: Walter Clark Milliken
  • Patent number: 7509361
    Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: March 24, 2009
    Assignee: Pastemak Solutions LLC
    Inventors: Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
  • Publication number: 20080320066
    Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: LSI Logic Corporation
    Inventors: Sergey Gribok, Alexander Andreev
  • Patent number: 7426527
    Abstract: Random number generator having a transistor that generates an analog random telegraph signal (RTS) having a first or second signal state, a RTS detection unit for detecting the RTS generated by the transistor, a RTS sampling unit that supersamples the RTS detected by the RTS detection unit and thus generates a digitized RTS, a signal state duration detection unit that determines, from the digitized RTS, a first time variable representing the time duration of at least one first signal state of the generated RTS and a second time variable representing the time duration of at least one second signal state of the generated RTS, and a random number conversion unit, which is coupled to the signal state duration detection unit, and that generates a random number from the first time variable and the second time variable.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: September 16, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Strum, Guido Stromberg, Ralf Brederlow, Werner Weber
  • Patent number: 7426666
    Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: September 16, 2008
    Assignee: Lucent Technologies Inc.
    Inventors: Raul Benet Ballester, Adriaan J. De Lind Van Wijngaarden, Ralf Dohmen, Bernd Dotterweich, Swen Wunderlich
  • Patent number: 7389316
    Abstract: Method and apparatus for true random number generation is described. One aspect of the invention relates to a digital logic circuit that includes N logic gates, where N is an integer greater than two. For each logic gate in the N logic gates: a first input terminal thereof is coupled to an output terminal thereof; a second input terminal thereof is coupled to an output terminal of a left neighbor thereof; and a third input terminal thereof is coupled to an output terminal of a right neighbor thereof. A sampling logic circuit may be provided to sample the output of the N logic gates to produce N-bit binary numbers. The N-bit binary numbers are true random numbers produced using pure digital logic without using an external source of randomness. A linear hybrid cellular automaton (LHCA) may be provided for scrambling output data of the sampling circuit.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 17, 2008
    Assignee: Xilinx, Inc.
    Inventor: Catalin Baetoniu
  • Patent number: 7379955
    Abstract: A device for and method of generating an uncorrelated pseudo-random bit sequence by first selecting a user-definable value K. Next, factoring K+1 into m prime factors q1, q2, . . . , qm, where q1, q2, . . . , qm are ordered from smallest value q1 to largest value qm. Next, generating m pseudo-random sequences r1, r2, . . . , rm, where each pseudo-random bit sequence ri is uniformly distributed over a range (0, . . . , qi?1), and where i=1, 2, . . . , m. Finally, generating the uncorrelated pseudo-random sequence as R=r1+q1r2+q1q2r3+ . . . +q1q2 . . . qm?1rm.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: May 27, 2008
    Assignee: The United States of America as represented by the Director, National Security Agency
    Inventors: Richard J. Kuehnel, Yuke Wang
  • Patent number: 7356551
    Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: April 8, 2008
    Assignee: NXP B.V.
    Inventor: Laszlo Hars
  • Patent number: 7284024
    Abstract: A quantum noise random number generator system that employs quantum noise from an optical homodyne detection apparatus is disclosed. The system utilizes the quantum noise generated by splitting a laser light signal using a beamsplitter having four ports, one of which receives one of which is receives the laser light signal, one of which is connected to vacuum, and two of which are optically coupled to photodetectors. Processing electronics process the difference signal derived from subtracting the two photodetector signals to create a random number sequence. Because the difference signal associated with the two photodetectors is truly random, the system is a true random number generator.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 16, 2007
    Assignee: MagiQ Technologies, Inc.
    Inventors: Alexei Trifonov, Harry Vig
  • Patent number: 7263540
    Abstract: A device for and method of generating as many as K random bits by generating a first pseudo-random bit, generating a second pseudo-random bit, delaying the second pseudo-random bit a number of times, storing the delayed pseudo-random bits, and combining the first pseudo-random bit with each of the delayed second pseudo-random bits.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: August 28, 2007
    Assignee: The United States of America as represented by the Director National Security Agency
    Inventor: Richard J. Kuehnel
  • Patent number: 7142675
    Abstract: A sequence generator for generating a pseudo random sequence for random number generation or a stream cipher engine includes a plurality of linear feedback shift registers operable to generate a plurality of binary sequences. A plurality of nonlinear functions having the binary sequences as their input and operable to generate a second plurality of binary sequences. There are at least two switches and a controller including a shift register operable to control said first and second switches. The first switch is operative to select one of the second plurality of binary sequences to the first bit of the shift register, and the second switch is operative to select one of said second plurality of binary sequences to the output of the sequence generator.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: November 28, 2006
    Assignee: City University of Hong Kong
    Inventors: Lee Ming Cheng, Chi Kwong Chan
  • Patent number: 7124158
    Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations require(by a polynomial defining the PRBS sequence.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 17, 2006
    Assignee: ECI Telecom Ltd.
    Inventors: Jacob Ruthstein, Lev Litinsky, Ronen Sommer
  • Patent number: 7120248
    Abstract: A process is provided for searching in parallel for a plurality of prime number values simultaneously includes the steps of: randomly generating a plurality of k random odd numbers (wherein k is preferably more than 2, but could also be one or more) expressed as n0,0, n1,0, . . . n((k?1)),0, each number providing a prime number candidate; determining a plurality of y additional odd numbers based on each one of the randomly generated odd numbers n0,0, n1,0, . . .
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: October 10, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: W. Dale Hopkins, Thomas W. Collins, Steven W. Wierenga, Ruth A. Wang
  • Patent number: 7072927
    Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: July 4, 2006
    Inventors: Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
  • Patent number: 7072924
    Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: July 4, 2006
    Inventors: Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
  • Patent number: 6999984
    Abstract: A reconfigurable chip using reconfigurable functional units is modified to better implement linear feedback shift registers. The reconfigurable functional unit has its input multiplexer unit modified so that it can select a combined value. The combined values include some of the bits from the output of the reconfigurable functional unit as well as carry bit from another reconfigurable functional unit. This can significantly reduce the space required to implement linear feedback shift registers which are useful in many digital communication systems.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventor: Peter Shing Fai Lam
  • Patent number: 6892337
    Abstract: A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: May 10, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Brenor L. Brophy, Dinesh Nadavi
  • Patent number: 6735606
    Abstract: Techniques for fast-slewing of multi-sequence based PN generators are disclosed. In one aspect, LFSR states and reference counter states are loaded into their corresponding components such that consistency among the states is maintained. In another aspect, various methods for determining LFSR states and counter values in response to a desired offset in a unique code are disclosed. Among these methods are matrix-multiplication of LFSR states and generation of advanced LFSR states through masking techniques. Other methods are also presented. These aspects have the benefit of decreasing slew time in an efficient manner, which translates to increased acquisition speed, faster finger lock on multi-path signals, increased data throughput, decreased power, and improved overall system capacity.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: May 11, 2004
    Assignee: Qualcomm Incorporated
    Inventors: Daisuke Terasawa, Avneesh Agrawal, Sivarama Venkatesan
  • Patent number: 6707841
    Abstract: A spreading code generator generates a spreading code specified by a matrix order and row number, which are matrix elements.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: March 16, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Atsushi Takasaki
  • Patent number: 6654404
    Abstract: A system for outputting pseudorandom noise sequences comprises a plurality of output apparatuses.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: November 25, 2003
    Inventor: Ken Umeno
  • Patent number: 6594680
    Abstract: Multiple PN sequences are generated in parallel using multiple LFSRs (10) or multiple mask circuits (40) coupled to a single LFSR. The offsets between PN sequences can be individually and independently set, either by setting the initial state in an LFSR (10) or setting a mask vector in a mask circuit (40). The LFSRs can be configured in real time to produce one or more blocks of PN sequence bits or to produce disjoint PN sequence bits. Zero insertion may be automatically generated in the LFSRs without additional mask circuitry. PN generating circuits may use either relative or absolute addressing, and may accommodate two levels of relative addressing. Further, one embodiment provides relative addressing without using masks.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: July 15, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Zhenguo Gu, Yuan Kang Lee
  • Publication number: 20030014451
    Abstract: A method and system for generating a pseudo-random bit series based on a given polynomial of order N, for M parallel communication lines using a machine comprising: N flip-flop machines and logic circuit. The flip-flop machines is initialized according to a given series of N bits. The logic circuit calculates a series of the next M+N tits using the N flip flop machines as function of the current N bit series wherein the function is based on two pre-generated equations. These equations are generated by recursive calculation of matrix array of order N*M according the given polynomial equation.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 16, 2003
    Applicant: OptiX Networks Inc.
    Inventors: Arye Peyser, Itai Katz, Itzlk Felman
  • Patent number: 6389439
    Abstract: A different phase type is specified toward each of a plurality of processors constituting a parallel computer, thereby, in a changeable manner, generating M sequence random numbers having the phase type. An information inputting unit inputs, into a random-number generating process unit, the number of the processors used in a parallel processing, the number of the random numbers to be generated by a single processor, the number of the phase types of the random numbers to be generated, and phase type information for each processor. The random-number generating process unit includes a phase-type management-table creating process unit, an initial-value table generating process unit, and a random-number generating calculation unit.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Saori Mitsunaga, Nobuhiro Ioki
  • Patent number: 6298360
    Abstract: A random number generator, useful in association with a computer system of a computer network, generates a randomly distributed back-off time interval between a collision and the retransmission of the packet, e.g. for Ethernet's collision sense multiple access/collision detect (CSMA/CD) protocol. The random number generator includes a data-based number generator, a timer-based number generator and a number combiner. The combiner is provided the output numbers from data-based and timer-based number generators, and in turn generates a random number. A user selectable initialization number is provided as a seed number for the data-based number generator. Subsequently, a cyclic redundency check (CRC) generator provides numbers for data-based number generator. A free-running timer provides numbers for the timer-based number generator. The user selectable initialization number is also provided as a seed number for the data-based and timer-base generators.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: October 2, 2001
    Assignee: Sun Microsystems, Inc.
    Inventor: Shimon Muller
  • Patent number: 6246970
    Abstract: A method of detecting tampering with an integrated circuit using circuit paths extending in the integrated circuit and carrying signals which are compared to each other, and to thresholds, and providing an output signal in the event that predetermined signal conditions occur. The predetermined signal conditions which occur may be a change of state of an output of a gate which interconnects the two circuit paths, or a change of state of the output of testing circuitry which tests signals in at least one of the circuit paths against a threshold. In a further aspect the invention concerns an integrated circuit chip provided with tamper detecting circuitry.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: June 12, 2001
    Assignee: Silverbrook Research Pty Ltd
    Inventors: Kia Silverbrook, Simon Robert Walmsley