Abstract: Digital data processing circuitry is described that uses combinatorial logic hardware and sequential logic hardware to process one or more inputs. For each input a periodic sequence is generated that is based at least in part on a value of the input and a weight value. A match is determined at an event time when the periodic sequence(s) matches a corresponding arbitrary reference pattern. The digital data processing circuitry may be implemented as an integrated circuit as part of an interconnected network of devices that may be trained and subsequently used for recognition or other complex data processing tasks.

Abstract: Methods and systems for performing hardware computations of mathematical functions are provided. In one example, a system comprises a mapping table that maps each base value of a plurality of base values to parameters related to a mathematical function; a selection module configured to select, based on an input value, a first base value and first parameters mapped to the first base value in the mapping table; and arithmetic circuits configured to: receive, from the mapping table, the first base value and the first plurality of parameters; and compute, based on a relationship between the input value and the first base value, and based on the first parameters, an estimated output value of the mathematical function for the input value.

Abstract: An arithmetic processing device includes a coefficient memory storing coefficients of a Taylor series expansion of a trigonometric function, a multiply-add arithmetic unit, a first bypass path supplying an output of the multiply-add arithmetic unit to a register file, an OR circuit calculating OR of a sign bit of the output of the multiply-add arithmetic unit and a least significant bit of a second input, a first selector selecting either a first input y or a value “1.0” an EOR circuit calculating an EOR of a first bit of the second input and a sign bit of an output of the first selector, and a second bypass path supplying the least significant bit of the second input to a coefficient selector. The multiply-add arithmetic unit executes an auxiliary instruction repeatedly while modifying a coefficient index from a maximum value to a minimum value to calculate sin (x).

Abstract: A reduced COordinate Rotation DIgital Computer (CORDIC) cell in a parallel CORDIC has an xy-path from x and y inputs to x and y outputs, and a z-path from a z-input to a z-output. Bit-shifts in the xy-path are hardwired. The z-path has a shortened adder/subtractor with a built-in or hardwired fixed parameter. Input bits from the z-input are split into most significant and least significant bits. The number of most significant bits equals the shortened adder/subtractor width. The most significant bits are input to the non-inverting inputs of the adder/subtractor for calculating the most significant z-output bits. The least significant bits are connected directly (or via buffers) from the z-input to the z-output.

Abstract: A pulse width modulation (PWM) control method for a five-level inverting circuit is provided. The five-level inverting circuit includes a first capacitor, a second capacitor, a third capacitor and first to eighth switch branches. In this PWM control method, the control logic is set to enable the first and fourth switch branches to be turned on in a complementary manner, the second and fifth switch branches to be turned on in a complementary manner, the third and sixth switch branches to be turned on in a complementary manner, and the seventh and eighth switch branches to be turned on in a complementary manner, and enable the first and second switch branches to be turned on in an interlocking manner, and the sixth and fifth switch branches to be turned on in an interlocking manner.

Abstract: Processor architectures and associated methods provide interruptible, instruction-based trigonometric function computation based on CORDIC iterations, receiving and outputting floating-point values (e.g., 64-bit). The architectures and methods can provide multiple CORDIC-like iterations in as little as a single CPU processing cycle to provide an overall faster execution of trigonometric operations while having zero additional overhead for service of time-critical interrupts. Post interrupt service, a CORDIC operation can be resumed from where it was interrupted.

Abstract: Disclosed is a DPD system. A DPD system provided in an embodiment of the present invention includes a table look-up unit and a DPD processing unit. First to Nth look-up-tables are used to combine two bit sequences of bit sequences obtained according to first to fourth address conversion tables so as to obtain first to Nth table look-up addresses. First to Nth DPD coefficients are found according to the first to Nth table look-up addresses, and one DPD coefficient is obtained via a DPD coefficient combination module, such that the DPD processing unit can perform DPD processing on a signal in first band according to the DPD coefficient. In the embodiment of the present invention, a look-up address is obtained according to four address conversion tables, a DPD coefficient is obtained from a look-up-table according to the look-up address, and then a final DPD coefficient is obtained to perform signal processing.

Abstract: Embodiments relate to an accumulator-based phase memory. An aspect includes a phase correction calculator configured to, based on receipt of a new frequency tuning word on a frequency tuning word input, determine a phase difference between the new frequency tuning word and a current frequency tuning word, and determine a product of the phase difference and a value of a counter. Another aspect includes wherein the accumulator-based phase memory determines a phase offset value based on the product of the phase difference and the value of the counter. Another aspect includes the accumulator-based phase memory further comprising a waveform generator configured to generate a waveform based on the new frequency tuning word and the phase offset value.

Abstract: A high precision, reciprocating bob viscometer is shown that has two coils (A and B) encircling a reciprocating bob. Coil A is energized with a combined sinusoidal and DC signal, while coil B senses the position of the reciprocating bob, then the functions of coils A and B are reversed. By use of a large digitally-generated near resonance frequency sinusoidal signal, noise is reduced because there is no need for amplification. The sensed signal amplitude measurement is in the digital time domain instead of through analog amplitude measurements, which further eliminates signal noise. These advancements provide faster, highly accurate, low noise measurements of bob position and velocity to determine fluid/gas viscosity and related properties using a reciprocating bob viscometer. These related properties include measurements of density, shear sensitivity, yield stress, and other measurements described in prior art patents.

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.

Abstract: A signal generating device includes a first digital filter unit outputting a first interpolated signal by interpolating an input signal, a second digital filter unit outputting a second interpolated signal by interpolating the first interpolated signal, a phase calculation unit calculating a phase of a digital signal, a phase-accuracy conversion unit calculating first phase signal and second phase signal, a first memory storing filter coefficients, a first coefficient readout unit reading filter coefficients from the first memory and switching filter coefficients of the first digital filter unit, a phase-error calculation unit calculating a phase error signal, a second memory storing filter coefficients, a second coefficient readout unit reading filter coefficients from the second memory, and a gain normalization unit normalizing a gain of the filter coefficients to maintain a constant sum of the filter coefficients and switching filter coefficients of the second digital filter unit.

Abstract: An apparatus and method for angle rotation is disclosed to rotate a complex input by the angle ? to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle ?M. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle ?M to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle ?L to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.

Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided, Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

Abstract: A geophysical data acquisition system includes at least one geophysical sensor. The at least one geophysical sensor has associated therewith a signal generator configured to generate a signal corresponding to a type of the at least one geophysical sensor. The system includes at least one signal acquisition unit having a plurality of input channels. The at least one geophysical sensor is in signal communication with one of the plurality of input channels. The plurality of input channels each includes a detector for receiving and identifying the signal generated by the signal generator. The at least one signal acquisition unit includes amplification, filtering and digitizing circuits automatically configurable in response to the type of sensor identified by the detected signal.

Abstract: A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits.

Abstract: A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Abstract: Numerically controlled oscillators and oscillation methods for generating function values in respective clock cycles by using a recurrence equation are provided. The oscillation circuit generates, in each of the clock cycles, a current one of the function values by multiplying, using a multiplier having a latency of k clock cycles, a first one of the function values generated in a first one of the clock cycles that is j cycles before a current one of the clock cycles by a coefficient and adding an output of the multiplier and at least one of the function values generated in previous ones of the clock cycles that are 1 to i?1 cycles before the current one of the clock cycles excluding the first one of the clock cycles, where 2<i, 1<j<i, and 0<k<j.

Abstract: A subtraction section subtracts from a received signal point a replica obtained by reflecting an influence of a propagation path state in a likely transmitted signal point. A calculation section calculates a metric for the received signal point and the replica from a value which the subtraction section calculates by subtracting the replica from the received signal point by the use of a linear interpolation formula obtained by separating a quadratic function at a power of 2.

Abstract: According to the preferred embodiments, a system or method is provided that involves the programming of a computer or other processing device with a software, hardware or firmware configured to create a processing tool (i.e., referred to herein as a tool box) that can be configured to provide one or more operational function based on new mathematical principles described herein for the purposes of, e.g., synthesizing or analyzing shapes and the like.

Abstract: Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUT1 exceeds an upper threshold V90% while a control signal EN_PG is active, and produces an inactive level of PG if EN_PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUT1 is less than a lower threshold V10% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUT1, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer.

Abstract: A circuit is provided with a plurality current cells. The current cells each comprise a main current source and an auxiliary current source coupled in parallel. The main current source supplies a main current to a current output of the current cell, and the auxiliary current source supplies an auxiliary current to the current output of the current cell. The main current sources are weighted according to a first predefined waveform, and the auxiliary current sources are weighted according to a second predefined waveform which is different from the first predefined waveform.

Abstract: High accuracy sin-cos wave and frequency generators, and related systems and methods. In non-limiting embodiments disclosed herein, the sin-cos wave generators can provide highly accurate sin-cos values for sin-cos wave generation with low hardware costs and small lookup table requirements. The embodiments disclosed herein may include a circuit to conduct an arithmetic approximation of a sin-cos curve based on a phase input. The circuit may be in communication with a point lookup table and a correction lookup table. The tables may receive the phase input and match the phase input to main sin-cos endpoints associated with the phase, and to a correction value for the phase. These values which are selected based on the phase input, may be communicated to a converter circuit where the arithmetic functions are applied to the values resulting in a sin-cos curve value.

Abstract: An arctangent calculation apparatus includes a phase angle memory unit in which a phase angle is stored in advance, the phase angle corresponding to a two-dimensional vector value corresponding to in a range of 0° to substantially 22.5°; a vector rotation unit that performs a vector rotation operation on a two-dimensional vector value corresponding to in a range of 0° to 360° and converts the two-dimensional vector value corresponding to in a range of 0° to 360° into a two-dimensional vector value corresponding to in a range of 0° to substantially 2.5°; an arctangent calculation unit that outputs, from the phase angle memory unit, a phase angle that corresponds to the two-dimensional vector value corresponding to in a range of 0° to substantially 22.5°; and a phase angle conversion unit that converts the phase angle into a phase angle in a range of 0° to 360°.

Abstract: The electronic circuit arrangement is used for generating poly-phase sequences as synchronization sequences and/or reference sequences in radio communications systems. It comprises a first adder, a first multiplier, a first register, a second register, a first counter and a trigonometry device. The first adder adds a value (km) formed from the value (k) of the counter to the value (B) of the first register. The first multiplier multiplies the value (A) of the second register by a value (y) formed from the value (B) of the first register and the value (k) of the counter. The trigonometry device forms the real part and the imaginary part of the present value of the poly-phase sequence (ak) from a value formed at least from the output value (wk) of the first multiplier.

Abstract: A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|(rs2 [0]<<63) and a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? 1.0: rs1)^(rs2 [1]<<63), or a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|((˜rs2 [0]<<63) and a fourth trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? rs1: 1.0)^((rs2 [1]^rs2 [0])<<63)).

Abstract: Circuitry for computing on x and y datapaths a trigonometric function of an input on a z datapath includes a comparison element to determine that the input is at or above a threshold, or below the threshold. The circuitry also includes a first left-shifter for shifting the z datapath by a constant when the input is below the threshold, and a second left-shifter for shifting an initialization value of the x datapath when the input is below the threshold. The circuitry further includes a look-up table including inverse tangent values based on negative powers of 2, and based on negative powers of 2-plus-the-constant and shifted by the constant, for adding to/subtracting from the z datapath, shifters for right-shifting elements of the x and y datapaths by amounts incorporating the constant and respective predetermined shift amounts that are adjusted when the input is below the threshold.

Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency.

Abstract: An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index.

Abstract: A unique instruction and exponent adjustment adder selectively shift outputs from multiple execution units, including a plurality of multipliers, in a processor core in order to scale mantissas for related trigonometric functions used in a vector dot product.

Abstract: A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer value from the input value, generating the transcendental value based on the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value, and providing the transcendental value in response to the request. In this fashion, the same circuit area may be used to carry out both trigonometric and power-of-two calculations, leading to greater circuit area savings and performance advantages while not sacrificing significant accuracy.

Abstract: A method (300) for generating a sine and cosine of an input angle (Ø102). The method involves decomposing Ø102 to an octant or quadrant, a coarse angle (A), and a fine angle (B), determining cos(A), and determining sin(A). The method also involves decomposing cos(A) and sin(A) to a most significant word (MSW) and a least significant word (LSW). The method further involves computing an approximation of 1?cos(B), an approximation of sin(B), and a plurality of products (P1, . . . , P4) using the MSWs and approximations. The method involves computing approximations of cos(Ø?102) and sin(Ø?102) using the values for cos(A), sin(A), and P1, . . . , P4. The method involves scaling the approximations of cos(Ø?102) and sin(Ø?102) to a desired resolution.

Abstract: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.

Abstract: A method, computer-readable medium, and apparatus for generating a trigonometric value. The method includes receiving a request to calculate a trigonometric value for an angle value and calculating a fractional value from the angle value. The fractional value corresponds to one of a first quadrant value, a second quadrant value, a third quadrant value, and a fourth quadrant value. The method also includes using the fractional value to determine whether to perform at least one of inverting the fractional value and negating the trigonometric value. The method further includes generating the trigonometric value from the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value and providing the trigonometric value in response to the request.

Abstract: In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition.

Abstract: This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so as to produce a division signal; an adder receives and adds the multiplication signal and the division signal so as to generate an output signal, that is then returned back to the divider. A quarter period of a sinusoidal wave signal is completed by the proceeding of direct calculation two times such that the time for the calculation of a complete sinusoidal wave can be saved and the area of the calculation circuit can be reduced.

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

Abstract: A method for composing a lookup table and searching indexes thereof is provided. The method includes the steps of: a) composing a lookup table using a symmetry of a sine and a cosine function; b) changing and setting a gain of a DCO by reflecting a lookup table size in the DCO; c) transforming an absolute value of a DCO output to an integer value; d) determining a range of the integer value of the DCO output; e) searching indexes of a sine and an cosine function according to the range of the integer value of the DCO output; and f) correcting a sign of a lookup table value corresponding to the searched index of the sine function and a sign of a lookup table value corresponding to the searched index of the cosine function according to the range of integers of the DCO output.

Abstract: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator produces a series of digital values approximating a sine wave. These values are computed, avoiding the need for large memories to store tables representing sine waves. Inaccuracies in the representation of the sine waves do not impact the accuracy of the resultant sine wave because circuitry used to correct for non-linearity errors in a digital-to-analog converter is programmed to also correct for errors introduced by approximating a sine wave with a computed function. A simple parabolic function may be used to compute approximations of a sine wave.

Abstract: The present invention relates to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency and a synthesizing method thereof. The direct digital frequency synthesizer and the synthesizing method thereof are capable of simplifying a configuration for matching output data of a phase accumulator to sine wave amplitude without increase in complexity of a DAC by applying a nonlinear DAC for directly generating a current corresponding to base points with sine weights and a variable sine wave-weighted DAC for generating fine currents to be combined with variable weights based on the base points. Accordingly, it is possible to provide a high quality output, reduce a size and power consumption, and increase a speed.

Abstract: One embodiment relates to a method for generating a periodic function in response to an argument in a digital signal processing system, where the periodic function can be represented as functions of two or more components of the argument. The method may include: obtaining a first operand from one of two or more lookup tables in response to a first component of the argument; obtaining a second operand from one of the lookup tables in response to a second component of the argument; conditionally mirroring the first and second operands in response to a quadrant of the argument; and calculating a value of the periodic function in response to the operands with a linear algebra unit without using conditional code execution.

Abstract: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator includes a look-up table that can, for each phase on sine wave, output two digital values representing an in-phase and a quadrature-phase value of the sine wave. Simple circuitry can be used to address the look-up table to output in-phase and quadrature-phase values. The in-phase and quadrature-phase values can be applied to down-stream circuitry, such as error correction circuitry, that uses an in-phase and a quadrature-phase value to process the sine wave without the need for a relatively complex phase shifter in the down-stream circuitry. A dual-port memory may be used to implement the look-up table so that both an in-phase and a quadrature-phase value may be obtained from a single block of memory that stores a representation of a sine wave.

Abstract: An arctangent calculation apparatus includes a phase angle memory unit in which a phase angle is stored in advance, the phase angle corresponding to a two-dimensional vector value corresponding to in a range of 0° to substantially 22.5°; a vector rotation unit that performs a vector rotation operation on a two-dimensional vector value corresponding to in a range of 0° to 360° and converts the two-dimensional vector value corresponding to in a range of 0° to 360° into a two-dimensional vector value corresponding to in a range of 0° to substantially 22.5°; an arctangent calculation unit that outputs, from the phase angle memory unit, a phase angle that corresponds to the two-dimensional vector value corresponding to in a range of 0° to substantially 22.5°; and a phase angle conversion unit that converts the phase angle into a phase angle in a range of 0° to 360°.

Abstract: A phase calculation apparatus using a binary search is provided. The phase calculation apparatus includes a quarter surface preprocessor determining the bigger one between an absolute value of I component data and an absolute value of Q component data as horizontal component data and the smaller one as perpendicular component data, and detecting information on a phase region indicating an mth (m=1 to 8) phase region (the mth phase region is between (m?1) ?/4 and m ?/4 in which the I/Q component data are located; a phase representative value detector detecting phase representative values x corresponding to the horizontal component data and the perpendicular component data; and a quarter surface postprocessor calculating phase values of the I/Q component data based on the detected information about the phase region and the detected phase representative values x. The phase can be calculated using a limited memory, low complexity of calculation and regardless of the number of bits of I/Q component data.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.

Abstract: A signal processing device includes a converting unit, a filtering unit, a differential computing unit, and a phase difference computing unit. The converting unit samples two alternating signals with a predetermined period and converts the sampled level values into digital alternating signal data. The filtering unit filters the two digital alternating signal data generated by the converting unit so as to abstract digital alternating signal data having a predetermined frequency, and the filtering unit comprises an adaptive digital filter. The differential computing unit computes differentials of the digital alternating signal data generated by the filtering unit. The phase difference computing unit computes phase difference using the two digital alternating signal data generated by the filtering unit, and the two digital alternating signal data generated by the differential computing unit.

Abstract: There are provided a coefficient ROM 1 for storing coefficients representing angular frequencies corresponding to a desired frequency and a sampling frequency, that is, two types of coefficients for a single desired frequency, an accumulated addition calculating portion 2 for using one of the coefficients until an accumulated addition value does not exceed a threshold and using the other coefficient when the accumulated addition value exceeds the threshold, thereby adding coefficient values stored in the coefficient ROM 1 every sampling frequency sequentially to obtain an angular frequency for each sample point, and a CORDIC 3 for calculating an amplitude of a sinusoidal wave corresponding to the angular frequency for each sample point which is obtained by the accumulated addition calculating portion 2, thereby generating a sinusoidal wave signal having a desired frequency, and the sinusoidal wave signal having the desired frequency can be generated by a digital calculation from only the two types of coeffici

Abstract: A cyclic equation setting unit transforms and sets a Taylor series equation for calculating a sine function into a single cyclic equation common to terms of the Taylor series equation, the single cyclic equation having a new known number Q that is defined by multiplying a known number Q and the square of a variable X, shifting the result by a shift number S and then adding a constant K thereto. An adjustment unit adjusts and prepares the shift number S such that within a variation range of the variable X the variable X has a maximum value 1 with the constant K being not greater than 1. A cyclic equation executing unit inputs and converts angle information i to the variable X, and executing the cyclic equation in sequence from higher order term to lower order term for the number of terms of the Taylor series equation to derive a sine function of the angle information i.

Abstract: A method (30°) for generating a sine and cosine of an input angle (Ø102). The method involves decomposing Ø102 to an octant or quadrant, a coarse angle (A), and a fine angle (B), determining cos(A), and determining sin(A). The method also involves decomposing cos(A) and sin(A) to a most significant word (MSW) and a least significant word (LSW). The method further involves computing an approximation of 1?cos(B), an approximation of sin(B), and a plurality of products (P1, . . . , P4) using the MSWs and approximations. The method involves computing approximations of cos(Ø?102) and sin(Ø?102) using the values for cos(A), sin(A), and P1, . . . , P4. The method involves scaling the approximations of cos(Ø?102) and sin(Ø?102) to a desired resolution.

Abstract: A hardware-efficient mapping circuit uses a base decoder to decode the control signal (the most significant bits “MSBs” of the phase angle) to provide a base value. A controller maps the control signal to a segment number to down select signed shift values from the control signal. Shifter blocks shift the data signal (the least significant bits “LSBs” of the phase angle) by the respective shift values. The shifted data signals are added/subtracted from the base value to approximate a sinusoidal amplitude for the phase angle. Down selection by a controller allows the shifter blocks to be implemented with narrow band multiplexers, which conserves both chip space and power.