Function Generation Patents (Class 708/270)

Patent number: 10387116Abstract: A system identification device includes: a direct feedthrough term identification unit that receives an impulse response of a dynamic system; a block Hankel matrix generation unit; a singular value decomposition unit that, by singular value decomposition of the block Hankel matrix, outputs a first orthogonal matrix, a second orthogonal matrix, and a singular value; a system dimension determination unit that, on the basis of the first orthogonal matrix, second orthogonal matrix, singular value, and search range, identifies a system matrix other than a direct feedthrough term, and from a comparison of the actual system characteristics and system characteristics calculated on the basis of the system matrix and direct feedthrough term, determines the system dimension; and a system matrix identification unit that identifies a system matrix other than the direct feedthrough term on the basis of the first orthogonal matrix, second orthogonal matrix, singular value, and system dimension.Type: GrantFiled: November 5, 2014Date of Patent: August 20, 2019Assignee: Mitsubishi Electric CorporationInventors: Mitsunori Saito, Yurika Kanai

Patent number: 10108701Abstract: The invention relates to determining a context of a system so that the system can be controlled or the context information be used in the system. The context of a system is described with tags or words that characterize e.g. the state of the system, the surroundings of the system and the state of the user. These tags are determined at multiple time instances. The tags are collected over a first time span and a second time span, and the two (or more) sets of tags are used to determine the context of the system. If the determination using the two sets gives a different result, that is, there is a large distance between the two derived contexts, it is determined that a change in context has occurred. Detecting the change in context can be used to control the system, e.g. by changing the applications presented to the user on the user interface, or by changing the state and/or priority of applications.Type: GrantFiled: February 22, 2012Date of Patent: October 23, 2018Assignee: NOKIA TECHNOLOGIES OYInventors: Jukka Saarinen, Leo Karkkainen, Mikko Terho, Ilenia Fronza, Andrea Janes, Alberto Sillitti, Giancarlo Succi

Patent number: 10027472Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective response bits of an authentication code in response to a challenge bit string. The PUF cells may include a pair of crosscoupled inverters, the individual inverters including independently selectable pulldown or pullup legs. One of the pullup or pulldown legs of each inverter may be selectively activated based on the challenge bit string. The PUF cells may further include first and second configurable clock delay circuits to pass respective clock signals to precharge transistors of the PUF cell. A dark bit masking circuit may generate a soft dark bit mask for the PUF circuit. Other embodiments may be described and claimed.Type: GrantFiled: September 27, 2016Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: Vikram B. Suresh, Sanu K. Mathew, Sudhir K. Satpathy

Patent number: 10003924Abstract: A method for generating an entityvector associated with a geographical location is disclosed. The entityvector is generated based on data from sensors of userwirelessdevices and user profile associated with userwirelessdevices.Type: GrantFiled: August 10, 2017Date of Patent: June 19, 2018Assignee: YANDEX EUROPE AGInventors: Andrey Borisovich Krasnikov, Alexander Vladimirovich Lukin

Patent number: 9946970Abstract: Embodiments described herein are directed to methods and systems for performing neural network computations on encrypted data. Encrypted data is received from a user. The encrypted data is encrypted with an encryption scheme that allows for computations on the ciphertext to generate encrypted results data. Neural network computations are performed on the encrypted data, using approximations of neural network functions to generate encrypted neural network results data from encrypted data. The approximations of neural network functions can approximate activation functions, where the activation functions are approximated using polynomial expressions. The encrypted neural network results data are communicated to the user associated with the encrypted data such that the user decrypts the encrypted data based on the encryption scheme. The functionality of the neural network system can be provided using a cloud computing platform that supports restricted access to particular neural networks.Type: GrantFiled: November 7, 2014Date of Patent: April 17, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Ran GiladBachrach, Thomas William Finley, Mikhail Bilenko, Pengtao Xie

Patent number: 9904922Abstract: A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.Type: GrantFiled: March 1, 2016Date of Patent: February 27, 2018Assignee: International Business Machines CorporationInventors: Robert J. Blainey, Barnaby Dalton, Louis Ly, James A Sedgwick, Lior Velichover, KaiTing A. Wang

Patent number: 9892411Abstract: A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.Type: GrantFiled: February 27, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Robert J. Blainey, Barnaby Dalton, Louis Ly, James A. Sedgwick, Lior Velichover, KaiTing A. Wang

Patent number: 9864003Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be faultfree, i.e., fully functional.Type: GrantFiled: June 12, 2017Date of Patent: January 9, 2018Assignee: Advanced Testing Technologies, Inc.Inventors: Robert Spinner, Eli Levi, Jim McKenna, William Harold Leippe, William Biagiotti, Richard Engel

Patent number: 9853365Abstract: A Frequency Modulated Continuous Wave (FMCW) radar system is provided that includes a chirp profile storage component configured to store a chirp profile for each chirp of a frame of chirps and a timing engine coupled to the chirp profile storage component to receive each chirp profile in transmission order during transmission of the frame of chirps, in which the timing engine uses each chirp profile to configure a corresponding chirp.Type: GrantFiled: May 5, 2015Date of Patent: December 26, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chethan Kumar Y. B., Saurabh Khanna, Vijay Rentala

Patent number: 9774327Abstract: The present invention discloses a bridge imbalance PUF unit circuit and multi PUF circuits; the bridge imbalance PUF unit circuit comprises a fourarm bridge unit circuit and a contrast output unit circuit; the multi PUF circuits comprise a timing controller, a row decoder, a column decoder, a memory array, a row output circuit and a column output circuit; each memory unit in the memory array comprises a bridge imbalance PUF unit circuit and 4 NMOS tubes; the present invention features in higher randomness that is up to 51.8% at the supply voltage of 1.2V under the temperature of 25° C.Type: GrantFiled: February 24, 2017Date of Patent: September 26, 2017Assignee: Ningbo UniversityInventors: Pengjun Wang, Haoyu Qian, Weiwei Chen

Patent number: 9740235Abstract: An interface adapter for facilitating the data communication among computation modules in a NetworkonChip SoC comprises 1) a FIFO block having certain number of storage cells for temporarily storing the data to be transported between two communicating modules; 2) a TAFDPS clock generator and a multiphase generator attached at the FIFO write side for generating the write clock for FIFO and the driving clock for the transmitter, a TAFDPS clock generator and a multiphase generator attached at the FIFO read side for generating the read clock for FIFO and the driving clock for the receiver; 3) a write pointer controller and a read pointer controller for reading the FIFO status and controlling the TAFDPS clock generators at the write side and at the read side, respectively. A design scheme of using said interface adapters in NetworkonChip SoC design includes a plurality of computation modules, routing modules, said interface adapters, a network of communication link, a network of global clock distribution.Type: GrantFiled: March 5, 2015Date of Patent: August 22, 2017Inventor: Liming Xiu

Patent number: 9646566Abstract: Providing a parameter calculation unit that calculates parameters representing medical functional information for pixel positions of the medical image, wherein the upper and lower limit values of the parameter medically represent the same functional information and whose value changes cyclically between these values, an interpolation parameter calculation unit that obtains, for a pixel position for which the parameter is not calculated, a parameter by interpolation, the unit calculating a parameter obtained by the interpolation using a cyclic function in which the interpolation direction differs according to the difference between the parameters calculated for two pixel positions, a display color group storage unit that includes a color group in which the same color corresponds to the upper and lower limit values of the parameter and whose color changes with the magnitude of the parameter, and a mapping unit that maps the parameters based on the color group.Type: GrantFiled: February 11, 2015Date of Patent: May 9, 2017Assignee: FUJIFILM CorporationInventor: Kenta Yamada

Patent number: 9596081Abstract: An orderpreserving tokenization (OPT) method receives a plaintext and generates a token as the ciphertext which preserves the sort order of the plaintext by using stored legacy plaintexttociphertext mapping data and a tail bounded probability distribution sampler to sample a random order preserving function. More specifically, the OPT method uses a mapping table to store plaintexttociphertext mapping for previously generated ciphertexts. The mapping table enables efficient searching of the ciphertext space as the OPT method only needs to look for ciphertext in the space that most likely will have the desired plaintext. In this manner, the orderpreserving tokenization method of the present invention realizes a fast algorithm that is also more computational efficient. In one embodiment, the OPT method uses a tail bounded hypergeometric distribution sampler as the probability distribution sampler.Type: GrantFiled: March 4, 2015Date of Patent: March 14, 2017Assignee: Skyhigh Networks, Inc.Inventors: Alexandra Boldyreva, Paul Grubbs, Nathan Chenette

Patent number: 9424307Abstract: This invention is a computerized method which unites a multivariate dataset and then performs various operations, including data analytics. The set is stored in a “bipartite synthesis matrix” (BSM), e.g., a rectangular matrix with rows of data objects and columns of variable attributes, defined by a plurality of partitions (each with a numerical range and a characteristic scale). Links within the matrix between data objects and attribute(s) are based on shared correspondences within partitions. The process exploits mode reduction in which shared correspondences of a BSM (or its graph) interrelate data objects by producing an adjacency matrix or its associated graph. The partition scale is repeatedly and incrementally altered, varying the density of shared correspondences within the data, based on partition number and size; therefore, a fully connected and weighted unipartite network may be established.Type: GrantFiled: October 11, 2013Date of Patent: August 23, 2016Inventor: Scott E. Lilienthal

Patent number: 9244106Abstract: A device for measuring the phasenoise spectrum of a pulsed sinusoidal signal generates a pulsed sinusoidal signal, converts the analog pulsed sinusoidal signal into a corresponding digital, pulsed sinusoidal signal and mixes the digital, pulsed sinusoidal signal into the baseband by means of quadrature mixing. Following this, the phase of the pulsed sinusoidal signal in the baseband is determined by means of Fourier transform of the phase of the pulsed sinusoidal signal, the phase spectrum of the pulsed sinusoidal signal is determined, and the phasenoise spectrum of the pulsed sinusoidal signal is determined by removing the spectral lines associated with the sinusoidal signal from the phase spectrum. According to the invention, the pulse pauses are removed from the pulsed sinusoidal signal in the baseband.Type: GrantFiled: January 5, 2012Date of Patent: January 26, 2016Assignee: Rohde & Schwarz GmbH & Co. KGInventors: Hagen Eckert, Martin Weiss, Wolfgang Wendler

Patent number: 9184751Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states.Type: GrantFiled: September 17, 2013Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Dirk Pfeiffer, JeanOlivier Plouchart, Peilin Song

Patent number: 9123128Abstract: Employing a general processing unit as a programmable function unit of a graphics pipeline and a method of manufacturing a graphics processing unit are disclosed. In one embodiment, the graphics pipeline includes: (1) accelerators, (2) an input output interface coupled to each of the accelerators and (3) a general processing unit coupled to the input output interface and configured as a programmable function unit of the graphics pipeline, the general processing unit configured to issue vector instructions via the input output interface to vector data paths for the programmable function unit.Type: GrantFiled: December 21, 2012Date of Patent: September 1, 2015Assignee: Nvidia CorporationInventor: Albert Meixner

Patent number: 9098077Abstract: A trajectory control device controlling a trajectory of a movable portion includes a servosystem responsetrajectory calculation unit that computes a servosystem response trajectory based on a position command of each movable axis, a shapefeature determination unit that outputs a shape feature amount including information of a position of a boundary point in a path shape and a running direction near the boundary point based on a determination from the position command whether the shape of the commanded path is straight or curved line, a positionvector correction unit that corrects a position vector based on the position command, the servosystem response trajectory and the shape feature amount, and outputs a corrected position command, and servo control units that control a motor of each movable axis by outputting a motor drive torque so that a position of each movable axis follows the corrected position command.Type: GrantFiled: July 28, 2011Date of Patent: August 4, 2015Assignee: Mitsubishi Electric CorporationInventor: Kotaro Nagaoka

Publication number: 20150074158Abstract: A method of constructing a set of basis functions is disclosed. The method comprises: receiving a set of data vectors describing a physical object or a physical phenomenon; using a data processor for calculating a set of eigenvalues for an objective matrix defined as a sum of a first matrix corresponding to the set of data vectors and a second matrix corresponding to a LaplaceBeltrami operator, the objective matrix being a positive definite matrix; and constructing the set of basis functions based on at least a subset of the eigenvalues.Type: ApplicationFiled: September 9, 2014Publication date: March 12, 2015Inventors: Ron Kimmel, Yonathan Aflalo

Publication number: 20150074159Abstract: According to various embodiments, a method for determining a result of applying a first function to an input may be provided. The method may include: determining a second function; and applying the second function to a value based on the input to determine a first intermediate value; applying the second function to a value based on the intermediate value to determine the result.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Axel York POSCHMANN, Sebastian Thomas KUTZNER, Ha NGUYEN PHUONG

Patent number: 8949301Abstract: Numerically controlled oscillators and oscillation methods for generating function values in respective clock cycles by using a recurrence equation are provided. The oscillation circuit generates, in each of the clock cycles, a current one of the function values by multiplying, using a multiplier having a latency of k clock cycles, a first one of the function values generated in a first one of the clock cycles that is j cycles before a current one of the clock cycles by a coefficient and adding an output of the multiplier and at least one of the function values generated in previous ones of the clock cycles that are 1 to i?1 cycles before the current one of the clock cycles excluding the first one of the clock cycles, where 2<i, 1<j<i, and 0<k<j.Type: GrantFiled: March 14, 2011Date of Patent: February 3, 2015Assignee: MegaChips CorporationInventor: Ryosuke Mori

Patent number: 8924449Abstract: A method for implementing variable symbol rate, presetting counters M and N, and M=1, N=0, f being the preset output symbol rate, fs being the frequency of input clock, the method comprises: triggering to judge whether N×f is greater than M×fs at the rising edge of the input clock, if it is, letting the counter M add 1 and outputting a clock pulse; else further judging whether the value of the counter N is equal to fs?1; when N=fs?1, letting the counter N return to 0, and waiting for the next rising edge of the input clock; when N?fs?1, waiting for the next rising edge of the input clock after letting the counter N add 1; letting the output clock pulse be the system clock, controlling the data to be output to set the symbol rate output.Type: GrantFiled: December 29, 2009Date of Patent: December 30, 2014Assignee: Shenzhen Coship Electronics Co., Ltd.Inventor: Wei Luo

Publication number: 20140351306Abstract: A method of generating a correlation function, a method of tracking a signal, and a signal tracking apparatus are provided. The method of generating a correlation function involves receiving a CBOC(6,1,1/11) signal, interpreting a subcarrier pulse period of the CBOC(6,1,1/11) signal as a subcarrier pulse period of BOCsin(6,1), combining partial correlation functions constituting an autocorrelation function of CBOC(6,1,1/11) to generate a correlation function, and weightedcombining the correlation function to generate an unambiguous correlation function.Type: ApplicationFiled: May 15, 2014Publication date: November 27, 2014Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Keunhong CHAE, Seokho YOON

Publication number: 20140344322Abstract: Computational techniques for mapping a continuous variable objective function into a discrete variable objective function problem that facilitate determining a solution of the problem via a quantum processor are described. The modified objective function is solved by minimizing the cost of the mapping via an iterative search algorithm.Type: ApplicationFiled: May 16, 2014Publication date: November 20, 2014Applicant: DWave Systems Inc.Inventor: Mani Ranjbar

Publication number: 20140310325Abstract: A model calculation unit for calculating a databased function model in a control unit is provided, the model calculation unit having a processor core which includes: a multiplication unit for carrying out a multiplication on the hardware side; an addition unit for carrying out an addition on the hardware side; an exponential function unit for calculating an exponential function on the hardware side; a memory in the form of a configuration register for storing hyperparameters and node data of the databased function model to be calculated; and a logic circuit for controlling, on the hardware side, the calculation sequence in the multiplication unit, the addition unit, the exponential function unit and the memory in order to ascertain the databased function model.Type: ApplicationFiled: April 7, 2014Publication date: October 16, 2014Applicant: ROBERT BOSCH GMBHInventors: Tobias LANG, Heiner MARKERT, Axel AUE, Wolfgang FISCHER, Ulrich SCHULMEISTER, Nico BANNOW, Felix STREICHERT, Andre GUNTORO, Christian FLECK, Anne Von VIETINGHOFF, Michael SAETZLER, Michael HANSELMANN, Matthias SCHREIBER

Publication number: 20140297705Abstract: A method for digital synthesis of a waveform, wherein: samples of a reference waveform that is divided into a plurality of contiguous time segments are stored in a digital memory; the duration of each time segment is set at a respective desired value; the time segments are scanned in an orderly manner as a function of a clock signal so as to select one time segment at a time; for the time segment selected, a relative time that has elapsed from the start of the time segment is calculated as a function of the clock signal; the memory is addressed as a function of said relative time and of a ratio between the number of the samples and the desired duration of the time segment in order to read at least part of the samples of the time segment; and a digitaltoanalog conversion of the samples read from the memory is carried out.Type: ApplicationFiled: February 18, 2014Publication date: October 2, 2014Inventor: Paolo PELLATI

Publication number: 20140289296Abstract: Systems and methods for generating complex waveforms, including step functions, impulse functions, and gate pulses are provided, as well as methods for generating modulated waveforms employing a number of known and newly developed modulation formats. The systems and methods of the present invention employ a continuous linear function, wherein all output points are defined. Discontinuities and singularities are eliminated, yet pulses having nearly instantaneous transitions may be achieved. Thus, gate pulses step functions, binary waveforms and the like may all be generated from a single function, where they entire output range of the function is defined over a continuous input domain.Type: ApplicationFiled: June 9, 2014Publication date: September 25, 2014Inventors: Robinson Gaudino Caputo, Luiz Gustavo Varella

Patent number: 8832168Abstract: A power function is approximated over an applicable data interval with polynomials determined by means of a Chebyshev minimax approximation technique. In some cases, multiple polynomials may be used to approximate the function over respective ranges of the desirable interval, in a piecewise manner. The appropriate polynomial that approximates the power function over the range of interest is derived and stored. When the power function is to be applied to a particular data value, the data value is first evaluated to determine where it lies within the applicable interval. The constants for the polynomial associated with that range of the interval are then retrieved and used to calculate the power of that data value.Type: GrantFiled: September 15, 2011Date of Patent: September 9, 2014Assignee: Apple Inc.Inventors: Ali Sazegari, Ian Ollmann

Publication number: 20140250161Abstract: Embodiments of techniques and systems for approximating a function are described. In embodiments, a computing device may receive one or more statistical properties associated with application of an approximation function of a function over a target domain. The computing device may formulate one or more constraints on one or more parameters of a functional form of the approximation function, based at least in part on the one or more statistical properties. The computing device may then determine the one or more parameters subject to the constraints and out put results of the determination. In embodiments, the one or more parameters may be determined through application of an optimization procedure. Other embodiments, may be described and claimed.Type: ApplicationFiled: March 28, 2012Publication date: September 4, 2014Inventor: Ping Tak Peter Tang

Patent number: 8819099Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.Type: GrantFiled: September 24, 2007Date of Patent: August 26, 2014Assignee: Qualcomm IncorporatedInventors: Mihai Sima, Daniel Iancu, Hua Ye, Mayan Moudgill

Patent number: 8818771Abstract: According to the preferred embodiments, a system or method is provided that involves the programming of a computer or other processing device with a software, hardware or firmware configured to create a processing tool (i.e., referred to herein as a tool box) that can be configured to provide one or more operational function based on new mathematical principles described herein for the purposes of, e.g., synthesizing or analyzing shapes and the like.Type: GrantFiled: June 21, 2011Date of Patent: August 26, 2014Inventors: Johan Gielis, Diego Caratelli

Patent number: 8805908Abstract: An approximation processing method for approximating a point group using a curve or a surface defined by control points includes a step of forming an approximated curve (surface) using control points that retain features of a shape; a first calculation step of calculating a closest point closest to each of the data points on the approximated curve (surface); a second calculation step of calculating an error vector that joins the closest point, obtained in the first calculation step, to the data point; and a third calculation step of calculating a corrected control point by moving each of the control points based on the error vector obtained by the second calculation step. The step of forming an approximated curve (surface) and the first to third calculation steps are repeated to make the approximated curve (surface) respectively approximate the curve (surface) of an object configured by the data points.Type: GrantFiled: February 24, 2009Date of Patent: August 12, 2014Assignee: National University Corporation Yokohama National UniversityInventors: Takashi Maekawa, Yuu Nishiyama, Masayuki Morioka

Patent number: 8768993Abstract: A direct current compensation method for Sparameter rational functions reads Sparameters f(sk), which are generated at given frequency sk, from a storage unit. An Sparameter, which is generated at frequency sk=0 is supplemented into the Sparameters f(sk), upon the condition that there is no Sparameter which is generated at the frequency sk=0. An Sparameter ration function is generated according to the Sparameters f(sk). A DC level of the Sparameter rational function is compensated to generate a compensated Sparameter rational function.Type: GrantFiled: March 2, 2011Date of Patent: July 1, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: WenLaing Tseng, ShenChun Li, YuChang Pai, ShouKuo Hsu

Patent number: 8762436Abstract: A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)?(D?N)/D), and where N/D<1. An accumulator creates a sum of (D?N) and a count from a previous cycle, and creates a difference between the sum and the denominator. The sum is compared with the denominator, and a first carry bit is generated. The complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a kbit quotient. The kbit quotient is subtracted from (I+1) to generate a divisor.Type: GrantFiled: December 17, 2010Date of Patent: June 24, 2014Assignee: Applied Micro Circuits CorporationInventors: Viet Do, Simon Pang

Patent number: 8751552Abstract: Methods for generating complex waveforms, including step functions, impulse functions, and gate pulses are provided, as well as methods for generating modulated waveforms employing a number of known and newly developed modulation formats. The methods of the present invention employ a continuous linear function, wherein all output points are defined. Discontinuities and singularities are eliminated, yet pulses having nearly instantaneous transitions may be achieved. Thus, gate pulses step functions, binary waveforms and the like may all be generated from a single function, where they entire output range of the function is defined over a continuous input domain.Type: GrantFiled: September 20, 2010Date of Patent: June 10, 2014Assignee: The Pulse Perfect Corporation, Inc.Inventors: Robinson Gaudino Caputo, Luiz Gustavo Varella Figueiredo

Patent number: 8732223Abstract: A function that represents data points is derived by creating a matrix (e.g., a Hankel matrix) of an initial rank, where the matrix contains the data points. Singular values are derived based on the matrix, and it is determined whether a particular one of the singular values satisfies an error criterion. In response to determining that the particular singular value does not satisfy the error criterion, the rank of the matrix is increased and the deriving and determining tasks are repeated. In response to determining that the particular singular value satisfies the error criterion, values of parameters that approximate the function are computed.Type: GrantFiled: January 25, 2010Date of Patent: May 20, 2014Assignee: WesternGeco L.L.C.Inventor: Can Evren Yarman

Patent number: 8694566Abstract: This method for decomposing an anharmonic periodic signal, the general form of which may be expressed as x(t)=x0+x1 cos(?(t)), wherein ?(t) is the phase of the signal, is characterized in that it consists of: determining an expression of the phase equation F ? ( ? ) = ? ? ? t , determining an expression of the phase ?(t) as a function of de parameters (r, rk, ?1, pk) measuring the anharmonicity of the signal and its morphology, from p cosn and p sinn functions defined by: p ? ? cos n ? ( t , r ) = ? k = 1 ? ? cos ? ( kt ) ? r k k n ? ? and ? ? p ? ? sin n ? ( t , r ) = ? k = 1 ? ? sin ? ( kt ) ? r k k n .Type: GrantFiled: January 7, 2011Date of Patent: April 8, 2014Assignee: Centre National de la Recherche ScientifiqueInventor: Patrick Hanusse

Patent number: 8682950Abstract: An input polynomial, in symbolic form, is received, classified, preprocessed, and factored. The input polynomial is classified as a constant, a univariate polynomial, or a multivariate polynomial. Various preprocessing is performed depending on the classification. After the input polynomial is preprocessed, the remaining polynomial is factored using a polynomial factoring algorithm. By preprocessing the input polynomial, the complexity of the polynomial to be factored is reduced, which reduces the computational expense of the polynomial factoring algorithm.Type: GrantFiled: May 28, 2010Date of Patent: March 25, 2014Assignee: Microsoft CorporationInventors: Xu Yang, Xiaolin Quan, Zhihui Ba, Dongmei Zhang

Patent number: 8676871Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.Type: GrantFiled: September 24, 2010Date of Patent: March 18, 2014Assignee: Intel CorporationInventors: Alex Pineiro, Thomas D. Fletcher, Brian J. Hickmann

Patent number: 8676872Abstract: A recursive method for computing numerical values for mathematical functions includes providing a recursive Taylor series representation of a mathematical function f(x) of a variable x evaluated around a given operating point a. The recursive Taylor series representation includes a plurality of derivative derived terms that include ratios of derivatives of f(x) evaluated at the operating point a. Coefficient data is determined from ones of the derivative derived terms stored in a tangible memory device evaluated at the operating point a over a predetermined range. An approximation for the mathematical function f(x) is computed using the recursive Taylor series representation evaluated with the coefficient data.Type: GrantFiled: February 17, 2011Date of Patent: March 18, 2014Assignee: Texas Instruments IncorporatedInventor: David Patrick Magee

Patent number: 8655934Abstract: A regenerative frequency divider device including a plurality of multipliers, each of which has a first input port, a second input port and an output port; a first combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of the multipliers; and a second combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of multipliers. Further, a first output signal generated by the first combiner is coupled to the second input port of at least two of the multipliers; and a second output signal generated by the second combiner is coupled to the second input port of at least two of the multipliers such that a complex signal is fed back to the multipliers performing the down conversion process. The present invention divider CRD can achieve superior output noise floor of ?180 dBc/Hz at multiGHz frequencies.Type: GrantFiled: January 9, 2007Date of Patent: February 18, 2014Assignee: General Instrument CorporationInventors: Branislav Petrovic, Maxim Ashkenasi, Andre Basovich

Patent number: 8655935Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiplyadder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.Type: GrantFiled: March 13, 2008Date of Patent: February 18, 2014Assignee: Fujitsu LimitedInventors: Mikio Hondou, Ryuji Kan, Toshio Yoshida

Patent number: 8650415Abstract: System, methods, and apparatuses produce simulated human physiological waveforms such as electrocardiograph (ECG) and blood pressure signals where the microcontroller and/or digitaltoanalog converters may be switched to a lower powerconsuming state by programmable instructions and switched on in response to a programmable sleep timer.Type: GrantFiled: February 4, 2011Date of Patent: February 11, 2014Assignee: PRONK Technologies, IncInventor: Karl Ruiter

Patent number: 8650235Abstract: A function generator for a digital system includes a plurality of subfunction generators. Each subfunction generator has an input that receives a respective input value and has an output that provides a respective output value responsive to the respective input value. A case detector receives a system input value and selectively routes at least a first portion of the system input value to the input of at least one selected subfunction generator. The case detector selects the selected subfunction generator in response to at least a second portion of the system input value. The case detector further suppresses transitions of data on the input of at least one nonselected subfunction generator. The case detector further selects the respective output value provided by the at least one selected subfunction generator and provides the selected respective output value as a function generator output value.Type: GrantFiled: July 18, 2011Date of Patent: February 11, 2014Inventor: Arthur Torosyan

Patent number: 8615540Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.Type: GrantFiled: July 24, 2009Date of Patent: December 24, 2013Assignee: Honeywell International Inc.Inventors: Jason Bickler, Karen Brack

Patent number: 8615537Abstract: The invention related to a method for encoding information using nonlinear evenly distributed functions, that comprises the following steps for building such a function: selecting a first natural integer n, a first set En of cardinal n, a group G operating on said first set En, a second natural integer q and a second set Eq of cardinal q; defining a set OG of the orbits of the group G operating on vectors of n elements in the set Eq, a function II that, for each vector of the n elements of the set Eq, associates the corresponding orbit and a second function ? allocating to each orbit of the group G a value of the set Eq; evenly distributing into a number q of sections the sums of the cardinals of the orbits of the group; defining a third function F comprising the first and second functions ?oII.Type: GrantFiled: December 14, 2009Date of Patent: December 24, 2013Assignee: Eads Secure NetworksInventor: Marc Mouffron

Patent number: 8572143Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.Type: GrantFiled: November 9, 2009Date of Patent: October 29, 2013Assignee: Agilent Technologies, Inc.Inventors: Thomas Dippon, Clemens Rabenstein

Patent number: 8572144Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.Type: GrantFiled: March 2, 2010Date of Patent: October 29, 2013Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev

Patent number: 8548161Abstract: In the field of cryptography there is a need to reduce the time taken to cryptographically transform data text while maintaining the low memory requirements associated with conventional squareandmultiply modular exponentiation. A method of cryptographically transforming data text c comprises the step of generating an integer representation m of the data text c according to m=cd where d is a predetermined exponent. The step of generating the integer representation m includes generating a sequence of intermediate numbers, each intermediate number being based on two or fewer earlier numbers in the sequence. Generating a sequence of intermediate numbers includes retrieving a prestored instruction to determine which two or fewer earlier numbers in the sequence a given intermediate number is based on and the functional manipulation of the or each earlier number required to generate the given intermediate number.Type: GrantFiled: December 10, 2010Date of Patent: October 1, 2013Assignee: NXP B.V.Inventor: Bruce Murray

Patent number: 8521796Abstract: This disclosure relates to setting the iteration count of a Cordic module as a function of a signal characteristic of an input signal provided to the Cordic module.Type: GrantFiled: November 25, 2008Date of Patent: August 27, 2013Assignee: Infineon Technologies AGInventor: Jianhui Hou