Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.

Abstract: A device receives images of a video stream, models for objects in the images, and physical property data for the objects, and maps the models and the physical property data to the objects in the images to generate augmented data sequences. The device applies different physical properties to the objects in the augmented data sequences to generate augmented data sequences with different applied physical properties, and trains a machine learning (ML) model based on the images to generate a first trained ML model. The device trains the ML model, based on the augmented data sequences with the different applied physical properties, to generate a second trained ML model, and compares the first trained ML model and the second trained ML model. The device determines whether the second trained ML model is optimized based on the comparison, and provides the second trained ML model when optimized.

Abstract: A plurality of tuple values of a stream of tuples is gathered. A normal operating range of the stream of tuples is determined. The normal operating range includes essentially all expected values of the stream of tuples. An outlier value which is outside of the normal operating range is identified. The outlier value is injected into the stream of tuples as an outlier tuple. A reaction to the injection of the outlier tuple is detected and recorded.

Abstract: Systems and methods for memory isolation are provided. The methods include receiving a request to write a data line to a physical memory address, where the physical memory address includes a key identifier, selecting an encryption key from a key table based on the key identifier of the physical memory address, determining whether the data line is compressible, compressing the data line to generate a compressed line in response to determining that the data line is compressible, where the compressed line includes compression metadata and compressed data, adding encryption metadata to the compressed line, where the encryption metadata is indicative of the encryption key, encrypting a part of the compressed line with the encryption key to generate an encrypted line in response to adding the encryption metadata, and writing the encrypted line to a memory device at the physical memory address. Other embodiments are described and claimed.

Abstract: An apparatus for modifying a sampling rate includes a forward transformer for forming a first version of a spectrogram by means of transformation with a first transformation length from an information signal with a first sampling rate. The apparatus includes a processor for forming a second version of the spectrogram with a lower bandwidth than the first version. The apparatus includes a reverse transformer for forming a coarsely pre-modified information signal with a second sampling rate that is reduced with respect to the first sampling rate, by means of reverse transformation of the second version of the spectrogram with a second transformation length that is reduced with respect to the first transformation length. The apparatus includes a time domain interpolator for acquiring an information signal with a third sampling rate that is modified with respect to the second sampling rate, by means of interpolation of the pre-modified information signal.

Abstract: An in-vehicle gateway device according to an embodiment includes a storage unit, a plurality of internal communication processors, a routing processor and a storage controller. The storage unit stores therein data output by an electronic control unit included in the in-vehicle system. The internal communication processors include an internal communication processor to which at least one electronic control unit is connected. The routing processor transfers data among the internal communication processors and outputs at least a part of the transferred data to the storage unit in a form capable of being stored in the storage unit. The storage controller manipulates or filters, in accordance with a certain rule, at least one of the data to store in the storage unit and the data output from the storage unit.

Abstract: A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.

Abstract: An adaptive filter includes: a filter configured to perform a filtering process for an input signal with a filter coefficient set therein, and output the processed input signal as an output signal; a calculating unit configured to calculate a value indicative of an error between an amplitude of the output signal and a reference amplitude; an output unit configured to output a first constant as a parameter when the amplitude of the output signal is greater than the predetermined amplitude, the parameter used when updating the filter coefficient, and output a second constant as the parameter when the amplitude of the output signal is smaller than the predetermined amplitude; and an updating unit configured to update the filter coefficient with an update amount corresponding to the parameter and the value indicative of the error, such that the error is reduced.

Abstract: An apparatus for simulating a signal composed of a plurality of individual signals from respective signal locations at a simulation location, having a provider for providing the plurality of individual signals in the time domain, a transformer for transforming the individual signals to the frequency domain, a processor for processing the individual signals transformed to the frequency domain each depending on a signal channel existing between the simulation location and the respective signal location, a combiner for combining the processed individual signals transformed to the frequency domain to a combined signal, and a transformer for transforming the combined signal to the time domain for generating the simulated combined signal at the simulation location.

Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.

Abstract: A method and apparatus provide digital frequency channelization of a digitally sampled input stream having a first bandwidth.

Abstract: Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Abstract: A storage manager and related method and computer program product manages client data on a data storage resource and includes the ability to utilize many different types of data stream filters that are neither built into the storage manager nor require a custom programming effort. A storage manager user may readily implement filtering by simply identifying a data stream filter the user wishes the storage manager to use for filtering the user's data. The filter can be an off-the-shelf program that is not part of the storage manager and which does not require client application or storage manager domain knowledge (e.g., knowledge of protocols or data types or formats used by the application or storage manager). The storage manager invokes the identified filter as part of a requested data stream operation and receives a data stream from a data stream source. The data stream is provided to the filter, which filters the data stream.

Abstract: The present invention provides a technique for changing the number of taps in filter processing without the need for execution of branch processing. A filter processing device comprises: an arithmetic circuit that performs arithmetic processing for filtering operation; an internal register that retains data to be subjected to arithmetic processing in the arithmetic circuit and that receives the result of arithmetic processing from the arithmetic circuit as data to be written back thereto; and a data generator that generates data to be fed to the arithmetic circuit through use of the data retained in the internal register. Further, in the filter processing device, there is disposed a tap number control circuit that is capable of controlling the number of taps in filter processing according to a tap control signal applied thereto. In this configuration, no branch processing is required for controlling the number of taps by the use of the tap number control circuit.

Abstract: The invention provides a method for improving efficiency of a filter bank. The filter bank includes multiple filters implemented by a firmware program. Each of the filters has a corresponding filter equation with a plurality of variables including a plurality of input samples and output samples of the corresponding filter. The variables of the filters are first stored in a specific order, wherein the variables of the same filter are stored together and the input samples and the output samples are stored separately and sorted according to a time index thereof. A starting pointer is then pointed to a first variable of a first filter of the filters. A plurality of current output samples of the filters is then generated according to the filter equations, the variables stored in the specific order, and a plurality of current input samples of the filters. The variables of the filter equations are then updated with the current input samples and the current output samples according to the specific order.

Abstract: A computer-implemented method of signal processing is provided. The method includes generating one or more masking signals based upon a computed Fourier transform of a received signal. The method further includes determining one or more intrinsic mode functions (IMFs) of the received signal by performing a masking-signal-based empirical mode decomposition (EMD) using the at least one masking signal.

Abstract: A digital signal processor (DSP) comprises an input terminal configured to receive an input, an adaptive nonlinear phase filter coupled to the input terminal, the adaptive nonlinear phase filter having a time-varying phase response, and an adaptive nonlinear amplitude filter coupled to the input terminal, the adaptive nonlinear amplitude filter having a time-varying amplitude response. A method of processing a signal comprises receiving the signal, sending the signal to an adaptive nonlinear phase filter, the adaptive nonlinear phase filter having a time-varying phase response, and sending the signal to an adaptive nonlinear amplitude filter, the adaptive nonlinear amplitude filter having a time-varying amplitude response.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

Abstract: A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

Abstract: An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The interpolation sub-filter that produces the highest sampling frequency is operated first, followed by interpolation sub-filters that operate at successively lower sampling frequencies. Computational independence of the cascaded sub-filters is guaranteed by adding delays to sampled and filtered signals. Delays are implemented by operating each of the cascaded sub-filters using prior filtering results that are computed during a previous sampling interval. A small increment to random-access memory is required for storing the successively delayed signals. The digital signal processor performing the filtering process is stalled for one clock cycle at the time a filtered signal sample is outputted so that the outputted signal sample can be produced without a timing conflict.

Abstract: A storage manager and related method and computer program product manages client data on a data storage resource and includes the ability to utilize many different types of data stream filters that are neither built into the storage manager nor require a custom programming effort. A storage manager user may readily implement filtering by simply identifying a data stream filter the user wishes the storage manager to use for filtering the user's data. The filter can be an off-the-shelf program that is not part of the storage manager and which does not require client application or storage manager domain knowledge (e.g., knowledge of protocols or data types or formats used by the application or storage manager). The storage manager invokes the identified filter as part of a requested data stream operation and receives a data stream from a data stream source. The data stream is provided to the filter, which filters the data stream.

Abstract: A micro-programmable digital filter includes a plurality of programmable filter elements, an instruction memory for storing a control program, at least one instruction decoder for programming the filter elements based on the control program, and arithmetic logic for selectively scaling and accumulating output values received from the filter elements and providing accumulated values as inputs to the filter elements. The filter elements are typically coupled in series so that a coefficient output from one filter element can be passed to an adjacent filter element for implementing longer filters. A separate instruction decoder may be included for each filter element. Execution of the separate instruction decoders is typically staggered so that the instruction decoders can share the instruction memory and an accumulator without collision. Each filter element can be programmed to implement a different filtering function, or multiple filter elements can be programmed to operate on a single filtering function.

Abstract: An improved Finite Impulse Response (FIR) filter is presented which provides linear scalability and implementation without the need for delay lines. A multiprocessor architecture includes a plurality of ALUs (Arithmetic and Logic Unit), Multipliers units, Data cache, and Load/Store units sharing a common Instruction cache. A multi-port memory is also included. An assigning functionality assigns to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values.

Abstract: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make K ? [ ( L 1 + L 2 L 1 ? L 2 ) ? N + L 2 L 1 + 1 ] memory accesses and KN multiply-accumulates, where L1 is the number of output vector elements computed during each pass through the outer loop and where L2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L1+2L2 general purpose registers.

Abstract: A device for filtering electrical signals has a number of inputs arranged spatially at a distance from one another and supplying respective pluralities of input signal samples. A number of signal processing channels, each formed by a neuro-fuzzy filter, receive a respective plurality of input signal samples and generate a respective plurality of reconstructed samples. An adder receives the pluralities of reconstructed samples and adds them up, supplying a plurality of filtered signal samples. In this way, noise components are shorted. When activated by an acoustic scenario change recognition unit, a training unit calculates the weights of the neuro-fuzzy filters, optimizing them with respect to the existing noise.

Abstract: A control apparatus includes a manipulated variable output unit, calculation unit, first lower limit setting unit, first upper limit setting unit, second lower limit setting unit, second upper limit setting unit, and controlling element. The manipulated variable output unit outputs first and second manipulated variables to an object to be controlled. The calculation unit calculates a limit cycle auto-tuning control parameter. The controlling element performs feedback control calculation based on the control parameter for the deviation between a set point and a controlled variable to calculate the first manipulated variable, and outputs the calculated first manipulated variable to the object.

Abstract: Method and system for adjusting or controlling a noise floor of a filtered signal for low frequencies. A filtered digital signal, having M bits, is processed to form an one-bit XOR signal. This XOR signal is added to the filtered signal to produce a modified filtered signal. A selected number of LSB bits of the modified filtered signal is removed to form a dithered filtered signal with a noise floor that is reduced for low frequencies.

Abstract: A filtering process is adapted for eliminating the need of prediscretizing a continuous-time differential model into a discrete-time difference model. It provides a universal robust solution to the most general formulation, in the sense that the system dynamics are described by nonlinear continuous-time differential equations, and the nonlinear measurements are taken at intermittent discrete times randomly spaced. The filtering process includes the procedures of validating the measurement using fuzzy logic, and incorporating factorized forward filtering and backward smoothing to guarantee numerical stability. It provides users a reliable and convenient solution to extracting internal dynamic system state estimates from noisy measurements, with wider applications, better accuracy, better stability, easier design, and easier implementation.

Abstract: A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a plurality of filter modules for digital processing/filtering of input values, having a memory area and a signal processing module, which contains in particular at least one multiplier-accumulator which has at least one multiplier and at least one adder. The input values, coefficients, and output values of the arrangement can be stored in the memory area and called up again therefrom as needed. The input values are gated with the coefficients to form output values. In order to alleviate the load on a higher-level microprocessor by digital processing/filtering of the input values, it is proposed that the digital filter arrangement have a Direct Memory Access controller for coordinating data transmission of the filter coefficients, input values and output values between the multiplier-accumulator and the memory area.

Abstract: Embodiments of a multiplierless pyramid filter are described.

Abstract: A filter comprising of an internal memory for storing data and coefficients; an address generation unit, for generating memory addresses; a multiply and accumulate unit (i.e.—MAC unit), for performing multiply and accumulate functions. The filter can operate in a plurality of modes, such as multiple or single channel FIR filtering; multiple or single channel IIR filtering; multiple or single channel echo cancellation; multiple or single channel decimation and multiple or single channel extrapolation.

Abstract: A filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In some realizations, both application code and filter code are executed on a same general purpose processor. The filter code incrementally loads respective portions of input and coefficient vector data from addressable storage into respective registers of the processor and performs successive operations thereupon to accumulate output vector data into other respective registers of the processor. The filter code typically exhibits an execution ratio of less than two input and coefficient data loads per operation to accumulate. In some realizations, the filter code is callable from the application code and provides the application code with a signal processing facility without use of a digital signal processor (DSP).

Abstract: A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame.

Abstract: A universal robust filtering process is adapted for eliminating the need of prediscretizing a continuous-time differential model into a discrete-time difference model. It provides a universal robust solution to the most general formulation, in the sense that the system dynamics are described by nonlinear continuous-time differential equations, and the nonlinear measurements are taken at intermittent discrete times randomly spaced. The universal robust filtering process includes the procedures of validating the measurement using fuzzy logic, and incorporating factorized forward filtering and backward smoothing to guarantee numerical stability. It provides users a reliable and convenient solution to extracting internal dynamic system state estimates from noisy measurements, with wider applications, better accuracy, better stability, easier design, and easier implementation.

Abstract: A processor (12) uses an architecture having a plurality of redundant state machines (86, 90) and a new instruction format (30) to increase efficiency of the utilization of operational circuitry, such as a multiply accumulate unit MAC (52). Thus the processor (12) can switch contexts or channels without incurring any dead or wasted cycles for the MAC unit (52).

Abstract: A processor (12) uses an architecture having a plurality of redundant state machines (86, 90) and a new instruction format (30) to increase efficiency of the utilization of operational circuitry, such as a multiply accumulate unit MAC (52). Thus the processor (12) can switch contexts or channels without incurring any dead or wasted cycles for the MAC unit (52).

Abstract: A DSP-based and multi-channel digital filter chip providing crossover filtering and parametric equalization. Crossovers can be low-pass, high-pass, or band-pass filters with programmable cutoff frequencies. Each equalizer band has independently adjustable center frequency band, and levels over a −60 dB to +16 dB range. The chip can work either with a microprocessor controlling the chip or in a stand-alone mode having the filter settings downloaded automatically from an external EEPROM. The chip is ideal for applications that require precise digital filtering or software programmable filters, and is also an alternative to analog filters, eliminating passive components and reducing circuit size.

Abstract: A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a plurality of filter modules for digital processing/filtering of input values, having a memory area and a signal processing module, which contains in particular at least one multiplier-accumulator which has at least one multiplier and at least one adder. The input values, coefficients, and output values of the arrangement can be stored in the memory area and called up again therefrom as needed. The input values are gated with the coefficients to form output values. In order to alleviate the load on a higher-level microprocessor by digital processing/filtering of the input values, it is proposed that the digital filter arrangement have a Direct Memory Access controller for coordinating data transmission of the filter coefficients, input values and output values between the multiplier-accumulator and the memory area.

Abstract: A method for optimizing the design of a digital filter for use in a microprocessor that utilizes sequential multiply and add instructions as distinct from single multiply and accumulate cycles. The method involves alternating the steps of multiplying and adding samples of the input signal and the coefficients that are assigned to the corresponding samples of the input signal. This add and multiply sequence is more efficient on most general-purpose computers than the more common load, multiply, add sequence used for this type of filter operation.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator and to simplify derivation of resulting discrete samples. In particular, an inverse relationship between weights applied to two samples is recognized and exploited. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight is associated with a second of the samples and a weight which is equivalent to the first weight is associated with the second sample and a weight which is equivalent to the second weight is associated with the first sample. The inverse relationship is exploited by forming two composite weights of the first and second weights and weighting composite sample signals with the composite weights. A first of the composite weights has a value which is one-half of the sum of the values of the first and second weights. A second of the composite weights has a value which is one-half of the difference of the values of the first and second weights.

Abstract: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods.

Abstract: A block infinite impulse response (IIR) processor has a first input register storing data of the block length "L" and capable of shifting the stored data by an integer times the data word length, a first coefficient register file, a second input register, a second coefficient register file, a third input register, a third coefficient register file, a register, a shift register, an accumulator and a multiply-and-accumulate unit for multiplying respective data blocks in the register by a least significant word in the shift register, and for adding the result of the multiplication to a value of the accumulator, for executing a parallel operation of "L" multiply-and-accumulate operations.

Abstract: A decoding process for a MPEG1 audio subband uses the symmetry of filter coefficients to reduce the number of multiplications required to decode an audio subband. The decoding process can be efficiently implemented on a single-instruction-multiple-data (SIMD) processor having vector registers capable of holding multiple samples from the subband. In a particular embodiment, some of samples are stored in a first vector register in a normal order and other samples are stored in a second vector register in a reverse order. For example, for eight data element vector registers, the first vector register contains a series of samples index values 0 to 7, and the second vector register contains a series of samples index values 31 to 24. Such ordering facilitates SIMD instructions which perform parallel operations combining value of index i with values of index 31-i.

Abstract: DSP error detection and filtering of a modem signal using a simple, robust, and low cost technique. The DSP technique utilizes a equalizer/filter to adjust the amplitude and phase delay of the transmitted data signal. The modem on the DSP chip may include a demodulator, parser/interpreter module, start and stop bit module, and modulator. The demodulator may include a switch, equalizer/filter, processing module, bit converter, adder, and averaging module. The averaging module computes an average value for the error signal during the frame training sequence. The error signal is the output of the bit converter minus the output of the demodulator. After each bit of the error signal is fed into the averaging module, the averaging module computes a new average. The averaging module performs an adaptive process. The average value of the error signal is compared to a threshold value.

Abstract: A system for equalizing an input signal including a datastream modulated on a carrier, with respect to both transmission channel distortions and local receiver distortions, includes a network for frequency downshifting the input signal, a controlled non-recursive filter (20) responsive to the downshifted input signal, and a demodulator (30) for receiving an output signal from the controlled filter. A signal processing network, including a filter network with a transfer function (40, 60, 80, 100) which is the inverse of the transfer function of the controlled filter, responds to an output signal from the demodulator for producing output control signals. The control signals are coupled to a coefficient control input of the non-recursive filter for equalizing the signal with respect to both transmission channel and receiver distortion.

Abstract: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make ##EQU1## memory accesses and KN multiply-accumulates, where L.sub.1 is the number of output vector elements computed during each pass through the outer loop and where L.sub.2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L.sub.1 +2L.sub.2 general purpose registers. For an embodiment in which L.sub.1 =L.sub.2 =8, inner and outer loop code make ##EQU2## memory accesses, which for filter implementations with large numbers of taps, approaches a 4.times. reduction in the number of memory accesses as compared to conventional methods.

Abstract: Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Abstract: A method for the estimation of the state variables of nonlinear systems with exogenous inputs is based on improved extended Kalman filtering (EKF) type techniques. The method uses a discrete-time model, based on a set of nonlinear differential equations describing the system, that is linearized about the current operating point. The time update for the state estimates is performed using integration methods. Integration, which is accomplished through the use of matrix exponential techniques, avoids the inaccuracies of approximate numerical integration techniques. The updated state estimates and corresponding covariance estimates use a common time-varying system model for ensuring stability of both estimates. Other improvements include the use of QR factorization for both time and measurement updating of square-root covariance and Kalman gain matrices and the use of simulated annealing for ensuring that globally optimal estimates are produced.