Filtering Patents (Class 708/300)
  • Patent number: 11817921
    Abstract: A method in an adaptive filter system is provided. The method comprises obtaining parameters for a plurality of branches of the adaptive filter system. The method further comprises computing gradient-based information for a selected one of the plurality of branches. The method further comprises updating the parameters for the plurality of branches based on the gradient-based information for the selected branch. An adaptive filter system is also provided.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 14, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Hao Gao, Haiying Cao, Sheng Liu
  • Patent number: 11797832
    Abstract: An Application Specific Integrated Circuit (ASIC) for computing a convolutional neural network (CNN) has a first input bus receiving an ordered stream of values from an array, each position in the array having one or more channels, and a plurality of kernel processing tiles receiving inputs through configurable multiplexors. The kernel processing tiles and buses are arranged and connected in a manner that the ASIC operates as a pipelined system delivering an output stream in synchronization with the input stream.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: October 24, 2023
    Assignee: Gigantor Technologies Inc.
    Inventor: Mark Ashley Mathews
  • Patent number: 11791363
    Abstract: An element includes a plurality of light-receiving elements to photoelectrically convert light received from an object, a convolution processing unit to perform convolution operation on signals that are output from the plurality of light-receiving elements, and a pooling processing unit to sample a signal that is output from the convolution processing unit, based on a predetermined condition. The convolution operation of the convolution processing unit and the sampling of the pooling processing unit are repeated.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 17, 2023
    Inventors: Shigeru Matsumoto, Sota Nakanishi, Tomohisa Ishida, Atsushi Miyamoto, Kiyoshi Uchikawa
  • Patent number: 11652471
    Abstract: Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 16, 2023
    Assignee: Google LLC
    Inventor: Jens Kristian Poulsen
  • Patent number: 11636329
    Abstract: Various examples related to real time detection with recurrent networks are presented. These can be utilized in automatic insect recognition to provide accurate and rapid in situ identification. In one example, among others, a method includes training parameters of a kernel adaptive autoregressive-moving average (KAARMA) using a signal of an input space. The signal can include source information in its time varying structure. A surrogate embodiment of the trained KAARMA can be determined based upon clustering or digitizing of the input space, binarization of the trained KAARMA state and a transition table using the outputs of the trained KAARMA for each input in the training set. A recurrent network detector can then be implemented in processing circuitry (e.g., flip-flops, FPGA, ASIC, or dedicated VLSI) based upon the surrogate embodiment of the KAARMA The recurrent network detector can be configured to identify a signal class.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 25, 2023
    Inventors: Kan Li, Jose C. Principe
  • Patent number: 11418678
    Abstract: An electronic apparatus includes a first communication apparatus, a second communication apparatus, a serial bus, and a first control circuit. The second communication apparatus includes a storage device configured to store stored data. A first control circuit determines whether or not a first data amount of stored data serving as request target of request data matches a second data amount of stored data included in response data transmitted from the second communication apparatus via a second signal line of the serial bus in response to the transmission of the request data on the basis of a data amount specifying signal transmitted by a third signal line of the serial bus when the request data is transmitted from the first communication apparatus via a first signal line of the serial bus, and outputs a determination result.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: August 16, 2022
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Yuichi Sugiyama, Hideo Tanii
  • Patent number: 11374553
    Abstract: A signal processing method performed by a processor of a signal processing device and includes: generating a fundamental matrix according to at least one set of fundamental coefficients; generating a phase-shifted matrix according to a predetermined phase shift and the fundamental matrix; and generating an output sequence according to an input sequence and the phase-shifted matrix. The set of fundamental coefficients is used to generate at least one bit of a code sequence, the output sequence is a phase-shifted version of the input sequence being shifted by k cycle(s), and k is the predetermined phase shift.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 28, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chih-Hao Liu
  • Patent number: 11323807
    Abstract: An echo cancellation method based on delay estimation is provided. In the method, a microphone signal and a reference signal are received and preprocessed. In the preprocessed microphone signal and the preprocessed reference signal, frequency point signals with non-linearity in a current echo cancellation scenario are determined. A current delay estimation value is calculated based on frequency point signals without non-linearity in the microphone signal and the reference signal. The reference signal is shifted based on the current delay estimation value. An adaptive filter is updated based on the preprocessed microphone signal and the shifted reference signal, to perform echo cancellation.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 3, 2022
    Assignee: IFLYIEK CO., LTD.
    Inventors: Mingzi Li, Feng Ma, Haikun Wang, Zhiguo Wang, Guoping Hu
  • Patent number: 11257183
    Abstract: The disclosed computer-implemented method may include determining a set of filter vectors. Each filter vector in the set of filter vectors may include a set of filter weights associated with at least one portion of an output volume of a resampling operation. The method may also include generating, via a clustering algorithm and based on the set of filter vectors, a filter bank for the resampling operation. The filter bank may include an additional set of filter vectors. The method may further include (1) transmitting the filter bank to a memory module included in a hardware accelerator, and (2) directing the hardware accelerator to execute the resampling operation using an input volume and the filter bank. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 22, 2022
    Assignee: Facebook, Inc.
    Inventor: Ioannis Katsavounidis
  • Patent number: 11227214
    Abstract: Systems, apparatuses, and methods for implementing memory bandwidth reduction techniques for low power convolutional neural network inference applications are disclosed. A system includes at least a processing unit and an external memory coupled to the processing unit. The system detects a request to perform a convolution operation on input data from a plurality of channels. Responsive to detecting the request, the system partitions the input data from the plurality of channels into 3D blocks so as to minimize the external memory bandwidth utilization for the convolution operation being performed. Next, the system loads a selected 3D block from external memory into internal memory and then generates convolution output data for the selected 3D block for one or more features. Then, for each feature, the system adds convolution output data together across channels prior to writing the convolution output data to the external memory.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 18, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sateesh Lagudu, Lei Zhang, Allen Rush
  • Patent number: 11176725
    Abstract: Systems and methods for image retargeting are provided. Image data may be acquired that includes motion capture data indicative of motion of a plurality of markers disposed on a surface of a first subject. Each of the markers may be associated with a respective location on the first subject. A plurality of blendshapes may be calculated for the motion capture data based on a configuration of the markers. An error function may be identified for the plurality of blendshapes, and it may be determined that the plurality of blendshapes can be used to retarget a second subject based on the error function. The plurality of blendshapes may then be applied to a second subject to generate a new animation.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 16, 2021
    Assignees: Sony Interactive Entertainment America LLC, Soul Machines Limited
    Inventors: Mark Andrew Sagar, Tim Szu-Hsien Wu, Frank Filipe Bonniwell, Homoud B. Alkouh, Colin Joseph Hodges
  • Patent number: 11165414
    Abstract: A filter circuit includes a first stage comprising a first infinite impulse response (IIR) filter; a third stage comprising a third IIR filter; and a second stage interposed between the first stage and the third stage, the second stage comprising a second IIR filter, where an output terminal of the first IIR filter is coupled to an input terminal of the second IIR filter, and an output terminal of the second IIR filter is coupled to an input terminal of the third IIR filter, where the second stage of the filter circuit is configured to operate in an acquisition mode when a transient is detected in an input signal to the first IIR filter, where during the acquisition mode, the second stage of the filter circuit is bypassed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Victor Popescu-Stroe, Dan-Alexandru Mocanu
  • Patent number: 11121788
    Abstract: The disclosure discloses a channel prediction method and system for a MIMO wireless communication system. The method includes the following steps: obtaining frequency domain channel information of each antenna pair of the MIMO wireless communication system through channel estimation; processing, by inverse Fourier transform, frequency domain channel information of each antenna pair to obtain information of each effective delay path of the MIMO wireless communication system; training the width learning system; utilizing the trained width learning system to predict each effective delay path of each antenna pair, so as to obtain the information of the next moment of each effective delay path of each antenna pair; after summarizing the information of the next moment of each effective delay path of each antenna pair obtained through prediction, the Fourier transform is utilized to convert the information into predicted frequency domain channel information.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: September 14, 2021
    Inventors: Yigang He, Yongbo Sui, Liulu He, Chaolong Zhang, Hui Shao
  • Patent number: 11062720
    Abstract: An information encoder for encoding an information signal includes: a converter for converting the linear prediction coefficients of the predictive polynomial A(z) to frequency values f1 . . . fn of a spectral frequency representation of the predictive polynomial A(z), wherein the converter is configured to determine the frequency values f1 . . . fn by analyzing a pair of polynomials P(z) and Q(z) being defined as P(z)=A(z)+z?m?lA(z?1) and Q(z)=A(z)?z?m?lA(z?1), wherein m is an order of the predictive polynomial A(z) and l is greater or equal to zero, wherein the converter is configured to obtain the frequency values by establishing a strictly real spectrum derived from P(z) and a strictly imaginary spectrum from Q(z) and by identifying zeros of the strictly real spectrum derived from P(z) and the strictly imaginary spectrum derived from Q(z).
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 13, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Tom Baeckstroem, Christian Fischer Pedersen, Johannes Fischer, Matthias Huettenberger, Alfonso Pino
  • Patent number: 11022996
    Abstract: One example aspect of the present disclosure relates to a method. The method can include receiving, by one or more computing devices, an input related to power consumption. The method can include filtering, by the one or more computing devices, the received input. The method can include classifying, by the one or more computing devices, the filtered input into one zone of a plurality of zones. The method can include determining, by the one or more computing devices, a setting associated with the classified zone. The setting can determine power production during an idle setting. The method can include causing, by the one or more computing devices, an adjustment to the determined setting at a rate determined by a rate limit.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 1, 2021
    Assignee: General Electric Company
    Inventors: Robert Schroer, Kevin Allen Davis
  • Patent number: 10979143
    Abstract: A frequency chirp correction method for the photonic time-stretch system comprises acquiring the stretching signal, i.e. acquiring the time-domain data after the time-domain stretching. First, the time-domain data of the stretching signal is Fourier transformed to obtain the spectral distribution. The spectral distribution is then convoluted with the first frequency-domain correction factor, and then multiplied with the second frequency-domain correction factor to obtain the modified frequency spectrum. Finally, the modified frequency spectrum is performed by the inverse Fourier transform to obtain the time-domain signal after the frequency chirp correction.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 13, 2021
    Inventors: Changqiao Liu, Xiaofeng Jin, Xianbin Yu, Xiangdong Jin, Xianmin Zhang, Shilie Zheng, Qinggui Tan, Bo Cong
  • Patent number: 10963746
    Abstract: Embodiments herein describe, when executing an average pooling operation in a neural network, scaling input operands before performing an accumulate operation. Performing average pooling in a neural network averages the values in each face of a 3D volume, thereby downsampling or subsampling the data. This can be performed by adding all the values in a face and then dividing the total accumulated value by the total values in the face. However, the order of operations in a multiply-accumulator (MAC) is reversed from the order of operations for performing average pooling. To more efficiently use the MAC, the order of operations when performing average pooling is reversed so that determining the average value for a face can be performed on a single MAC. To do so, the values in the face are first scaled by a multiplier before being summed by an accumulator.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventor: Andrew M. Whyte
  • Patent number: 10958483
    Abstract: The disclosed systems, structures, and methods are directed to a method for determining a set of N optimal coefficients to be supplied to an equalizer, the equalizer being employed in at least one of a serializer and a deserializer, the method comprising: receiving N different parameters, searching an initial set of N coefficients on an N-dimensional performance surface, in accordance with a genetic algorithm, wherein the N-dimensional performance surface corresponds to various coefficients in the N parameters, and fine tuning the initial set of N coefficients to provide the set of N optimal coefficients, in accordance with a gradient descent algorithm.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 23, 2021
    Inventors: Shayan Shahramian, Ryan Bespalko
  • Patent number: 10949168
    Abstract: An ALU is capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 16, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: David Carlson
  • Patent number: 10938604
    Abstract: A system for receiving signals transmitted via serial links includes an analog-to-digital converter configured to sample the first analog signal at a first rate, and generate a first digital input signal having a second data rate. The system also includes a decimator coupled to an output of the equalizer and configured to downsample the first equalized signal to a decimated signal having the first data rate. The system further includes a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a second slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: March 2, 2021
    Assignee: Macom Technology Solutions Holdings, Inc
    Inventors: Yehuda Azenkot, Georgios Takos, Bart R Zeydel
  • Patent number: 10929154
    Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Brian Lewis Brown
  • Patent number: 10868701
    Abstract: The present invention relates to a wavelet bandpass sampling method, with low aliasing and a corresponding device. The analogue signal to sample is correlated with a sequence of wavelets succeeding each other with a rate fp of which the positions in the sequence are temporally modulated from arguments of a CAZAC sequence, notably a Zadoff-Chu sequence. The correlation results are next sampled at a frequency fs?fp and digitally converted to provide a compressed representation of the signal. The temporal modulation of the positions of the wavelets makes it possible to obtain incoherent aliasing of the correlation signal in the sampling band and thereby to reduce aliasing.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Michael Pelissier, Marguerite Marnat
  • Patent number: 10827200
    Abstract: A video coding apparatus for encoding or decoding a frame of a video, the video coding apparatus comprising a frame reconstruction unit configured to reconstruct the frame, a parameter determination unit configured to determine one or more filter parameters, based on one or more first parameters which are based on the reconstructed frame and one or more second parameters which are based on codec signaling information, and a mixed-domain filtering unit configured to filter in a frequency domain and a pixel domain the reconstructed frame based on the determined filter parameters to obtain a filtered frame.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 3, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Victor Alexeevich Stepin, Roman Igorevich Chernyak, Ruslan Faritovich Mullakhmetov
  • Patent number: 10778192
    Abstract: A filter coefficient calculation device includes a function unit that has a plurality of functions to be executed by an FIR filter, a function selection unit that selects one or a plurality of functions from among the plurality of functions, and a filter coefficient calculation unit that calculates a filter coefficient in the selected one or plurality of functions, and is configured such that the function unit includes a first transfer function calculation unit, a second transfer function calculation unit, and a third transfer function calculation unit which calculate a transfer function of the FIR filter in the respective functions, and the filter coefficient calculation unit performs inverse Fourier transform on the transfer function in the selected one function or a product of the transfer functions in the plurality of functions to obtain an impulse response of the FIR filter and calculates the impulse response as the filter coefficient.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: September 15, 2020
    Inventor: Yasuo Hosaka
  • Patent number: 10748603
    Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Huseyin Ekin Sumbul, Gregory K. Chen, Raghavan Kumar, Phil Knag, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
  • Patent number: 10733007
    Abstract: Application management is facilitated by observing messages communicated amongst virtual applications external to application-hosting virtual machines. In one instance, the messages can be observed from within a virtual switch outside hosting virtual machines. One or more actions can subsequently be performed as a function of the messages such as but not limited to application monitoring as well as message routing, filtering, and/or transformation.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 4, 2020
    Inventors: Ashvin Sanghvi, Liarie Letca, Alexandre Coelho
  • Patent number: 10684825
    Abstract: An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers are equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Cavium, LLC
    Inventor: David Carlson
  • Patent number: 10663479
    Abstract: In some examples, a method determines an open/close status of a pivotable barrier on a moveable platform based on selective use of a plurality of different filters for filtering measurement data from a sensor device.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 26, 2020
    Assignee: BlackBerry Limited
    Inventors: Dake He, Alexander Levato, Yu Gao
  • Patent number: 10666307
    Abstract: A nonlinear compensator is provided to include a decomposition circuit and a plurality of filter elements. The decomposition circuit has a nonlinear frequency response characteristic and the decomposition circuit is configured to receive an input signal and decompose the input signal into decomposed signals corresponding to positive and negative frequency signal components of the input signal. Each of the plurality of filter elements is configured to receive at least portions of the decomposed signals and apply filter element characteristics to the decomposed signals with the filter element characteristics that are matched to the nonlinear frequency response of the decomposition circuit.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 26, 2020
    Assignee: Massachusetts Institute of Technology
    Inventor: Xiao-Yu Wang
  • Patent number: 10565325
    Abstract: Systems and methods are provided for simulating an electrical characteristic of an electronic device having input ports and output ports. A device frequency response data structure is accessed that contains data associated with a plurality of port-to-port frequency responses of the electronic device, each port-to-port frequency response being associated with a plurality of frequencies. A QR decomposition is performed based on data from the frequency response data structure. A subset of the port-to-port frequency responses is selected based on the QR decomposition. A set of common poles is identified using the selected subset of port-to-port frequency responses, and a model of time domain behavior of the electronic device is generated using the set of common poles.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 18, 2020
    Assignee: Ansys, Inc.
    Inventors: Michael J. Tsuk, Amit Hochman, Jacob K. White
  • Patent number: 10530504
    Abstract: The disclosure relates to a cluster detection device for detecting clusters in a beam-formed transmission, the cluster detection device comprising: a receiver, configured to receive a radio signal comprising time-frequency resources, wherein the time-frequency resources comprise a plurality of reference signals; a delay profile detector, configured to detect a set of delay profiles based on frequency-direction filtering of the plurality of reference signals; a Doppler profile detector, configured to detect a set of delay-Doppler profiles based on time-direction filtering of the set of delay profiles; and a cluster detection postprocessor, configured to derive a set of cluster parameters from the set of delay-Doppler profiles.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: January 7, 2020
    Assignee: Intel IP Corporation
    Inventor: Stefan Fechtel
  • Patent number: 10530339
    Abstract: A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 7, 2020
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventor: Srinivas Achanta
  • Patent number: 10483933
    Abstract: A method to adjust audio amplification may include presenting an audio configuration interface. The audio configuration interface may include multiple amplification settings that each correspond to a different one of multiple frequency range. The multiple amplification settings indicating amplifications may be applied to the multiple frequencies of audio output by a device. The method may further include obtaining an action to adjust the amplification of one or more of multiple amplification settings in the audio configuration interface to generate adjusted amplification settings. The method also includes, in response to obtaining the action, automatically applying the adjusted amplification settings to test audio and automatically outputting the test audio with the applied adjusted amplification settings through a speaker of the device.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 19, 2019
    Assignee: Sorenson IP Holdings, LLC
    Inventor: Christian Lalor
  • Patent number: 10476483
    Abstract: Filters are discussed where a first window function and a second window function are applied to a digital input signal, wherein a window length of the first window function is longer than a window length of the second window function. The results of this windowing are integrated.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 12, 2019
    Inventors: Dietmar Straeussnigg, Peter Bogner, Michael Kropfitsch, Jens Barrenscheen
  • Patent number: 10476609
    Abstract: A system and/or method is provided for enhanced listening of audio signals acquired via a telecoil by performing hum filtering. The system may include a telecoil and a telecoil hum filter. The telecoil hum filter may include a comb notch filter. The comb notch filter may include a delay module and a comb notch filter summing module. The telecoil may be operable to receive a magnetic signal and convert the magnetic signal to an input audio signal. The delay module of the comb notch filter may be configured to generate a delayed signal by applying a delay to the input audio signal. The delay may be based on a fundamental hum frequency. The comb notch filter summing module may be configured to generate a comb notch filter output signal by adding the input audio signal and the delay signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 12, 2019
    Inventor: Stephen D. Julstrom
  • Patent number: 10439595
    Abstract: A customizable data aggregating, data sorting, and data transformation system is disclosed. In particular, the system may allow for the application of various filters to a sample of data corresponding to various measurables associated with objects. A mean and standard deviation for each of the measurables in the filtered sample of data may be calculated and may be utilized in determining z-scores for a first set of raw measurements corresponding to the measurables. Once the z-scores for the first set of raw measurements are determined, selected weights may be applied to each of the z-scores to determine a weighted z-score for each of the measurables in the first set. Each weighted z-score may then be aggregated to generate a score for an object associated with the first set. The score for the object may be utilized to rank the object relative to other objects in the filtered sample of data.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 8, 2019
    Inventors: Craig S. Montgomery, Spence K. Purnell
  • Patent number: 10401517
    Abstract: Crosstalk attenuation for seismic imaging can include creation of a seismic image based on seismic data including multiples. The seismic image can include causal crosstalk and anti-causal crosstalk. Causal crosstalk and anti-causal crosstalk can be predicted based on the seismic data. The predicted causal crosstalk and the predicted anti-causal crosstalk can be attenuated from the seismic image.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 3, 2019
    Assignee: PGS Geophysical AS
    Inventors: Shaoping Lu, Norman Daniel Whitmore, Jr., Alejandro Antonio Valenciano Mavilio
  • Patent number: 10387740
    Abstract: A deep learning object detection and recognition system contains a number of cellular neural networks (CNN) based integrated circuits (ICs) operatively coupling together via the network bus. The system is configured for detecting and then recognizing one or more objects out of a two-dimensional (2-D) imagery data. The 2-D imagery data is divided into N set of distinct sub-regions in accordance with respective N partition schemes. CNN based ICs are dynamically allocated for extracting features out of each sub-region for detecting and then recognizing an object potentially contained therein. Any two of the N sets of sub-regions overlap each other. N is a positive integer. Object detection is achieved with a two-category classification using a deep learning model based on approximated fully-connected layers, while object recognition is performed using a local database storing feature vectors of known objects.
    Type: Grant
    Filed: May 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Charles Jin Young, Jason Z. Dong, Wenhan Zhang, Baohua Sun
  • Patent number: 10367477
    Abstract: In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 30, 2019
    Assignee: Analog Devices, Inc.
    Inventors: David Lamb, Luiz Chamon, Vitor H. Nascimento, Adam R. Spirer
  • Patent number: 10181332
    Abstract: Systems, methods, and apparatuses are presented herein for detecting and identifying unmanned aircraft systems (UAS) or drones. The system can include one or more UAS sensor nodes distributed about an area to be monitored. Each UAS sensor node can be communicably coupled to a central server but is able to conduct detection and identification procedures separate from the central server. The UAS sensor node can include a microphone that detects an audio signal generated within the area to be monitored. The node can convert the audio signal into a digital signal, can segment the audio signal, and can pass the signal through a bandpass filter. The node can also conduct a Fourier transform and smooth filtering on the digital audio signal before comparing the signal to multiple stored sample UAS audio signals for known UAS vehicles and motor stresses to determine a likelihood of a match.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 15, 2019
    Assignee: The Aerospace Corporation
    Inventors: Edward Aric Laag, Kiley Lauren Yeakel, Eric Bernard Wendoloski, Jason Laurence Tichy
  • Patent number: 10169084
    Abstract: The present invention provides a computer implemented method, system, and computer program product of deep learning via dynamic root solvers. In an embodiment, the present invention includes (1) forming an initial set of GPUs into an initial binary tree architecture, where the initial set includes initially idle GPUs and an initial root solver GPU as the root of the initial binary tree architecture, (2) calculating initial gradients and initial adjusted weight data, (3) choosing a first currently idle GPU as a current root solver GPU, (4) forming a current set of GPUs into a current binary tree architecture, where the current set includes the additional currently idle GPUs and the current root solver GPU as the root of the current binary tree architecture, (5) calculating current gradients and current adjusted weight data, and (6) transmitting an initial update to the weight data to the available GPUs.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Anto Ajay Raj John
  • Patent number: 10122371
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 6, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 10085106
    Abstract: A sound control device includes a sound collector for collecting a first sound signal generated from a noise source and deformed along a primary path between the noise source and a sound input unit, and a second sound signal generated through a speaker and deformed along a secondary path between the speaker and the sound input unit; and a sound controller for updating an adaptive filter in a designed adaptive control logic with at least one of the collected first and second sound signals and a preset target sound, and generating a sound effect that reflects the secondary path based on the updated adaptive filter.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 25, 2018
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Kyoung Jin Chang
  • Patent number: 10003324
    Abstract: Data samples are filtered by using a digital filter where the length of an impulse response of the digital filter is finite, an impulse response of the digital filter is symmetric and the operation of the digital filter is multi-rate. The method uses a polyphase decomposition to break down the input data stream into N parallel substreams and the multi-rate digital filter is separated by a polyphase decomposition into multiple lower-rate sub-filters where each of the sub-filters is separated into a set of simpler sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: June 19, 2018
    Inventors: Brian Berscheid, Aroutchelvame Mayilavelane
  • Patent number: 9832293
    Abstract: A smartphone comprising: a liquid crystal panel having a display surface having a quadrangular display area defined therein; a cover panel; an input unit disposed so as to be located outside the display area such that one side section included in four side sections defining the display area is located between the input unit and the display area, the input unit converting input bone conduction sound transmitted through the cover panel into an input signal; and an output unit disposed so as to be located outside the display area such that the one side section included in the four side sections defining the display area and located between the display area and the input unit is located between the output unit and the display area, the output unit converting an output signal and transmitting the same as output bone conduction sound to the cover panel.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: November 28, 2017
    Inventor: Mikihiro Noma
  • Patent number: 9784959
    Abstract: Unnecessary degradation of a light detector is prevented.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 10, 2017
    Inventor: Nobuhiro Takamizawa
  • Patent number: 9762249
    Abstract: A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 12, 2017
    Assignee: Movellus Circuits, Inc.
    Inventors: Muhammad Faisal, Jeffrey Alan Fredenburg, David Michael Moore
  • Patent number: 9660624
    Abstract: Circuitry that efficiently implements loop functions in an integrated circuit is provided. The circuitry combines a feed-forward circuit with a feedback loop that includes a unit delay element in a feedback path. The feedback path may couple the output of a processing element to the input of the processing element. The processing element may implement a function that satisfies commutative, associative, and distributive properties. Combining the feedback loop with the feed-forward circuit may allow for register retiming in the feedback loop and for register pipelining with optional register retiming in the feed-forward circuit. The circuitry may thus trade off an increase in throughput and clock frequency for additional resources.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 23, 2017
    Assignee: Altera Corporation
    Inventors: Nima Safari, Volker Mauer, Shahin Gheitanchi
  • Patent number: 9641359
    Abstract: A system including first and second filters and an adaptation engine. The first filter includes first taps that receive first coefficients and filters a digital signal to generate a first filtered signal. One of the first coefficients is constrained, such that the one of the first coefficients are not updated and phase and gain errors are introduced. The second filter includes second taps that receive second coefficients and filters the first filtered signal to generate a second filtered signal. The second coefficients include first and second coefficients. The adaptation engine, based on the one of the first coefficients, updates: the first coefficient to set a phase of the second filter; and the second coefficient to set a gain of the second filter. The phase of the second filter corresponds to a change in the phase error. The gain of the second filter corresponds to a change in the gain error.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: May 2, 2017
    Inventor: Pantas Sutardja
  • Patent number: 9641157
    Abstract: A method and device are provided for filtering digital audio signals using at least one ARMA filter, particularly during a filter change. The method includes the following steps: a step of receiving a first request to change filtering to or from filtering by a first ARMA filter; and, in response to the first request, a step of gradually switching, at each of a plurality of cascaded first filtering blocks, between digital-signal filtering by a first basic filtering cell and digital-signal filtering by another associated basic filtering cell, the first basic filtering cells of the plurality of first filtering blocks factorizing the first filter.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 2, 2017
    Assignee: ORANGE
    Inventors: Alexandre Guerin, Julien Faure, Claude Marro