Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.

Abstract: An apparatus in a configurable logic unit may include a configurable logic unit (CLU) configured to receive first and second operands and to perform an operand operation and generate an operation value. The apparatus may also include: a random value generator for generating a random value; an adder coupled to the CLU and the random value generator and configured to generate a sum of the operation value and the random value; and a shift register coupled to the adder and configured to shift the sum by a number of bits to generate shifted data at an output. The random value generator may be a linear feedback shift register. The output may be coupled to an additional CLU so that the shifted data may be used for subsequent operand operations. The apparatus may be implemented in a digital signal processor slice in a configurable logic block.

Abstract: Data output from each of the “n” delay elements and a remainder value output from a divider in the previous calculation are input to an adder, and an addition process for obtaining a total sum thereof is executed. In addition, a division process is performed by dividing the total sum output from the adder by “n,” and a quotient and a remainder are output from the divider. The remainder is delayed by a remainder delay element by one clock, is output to the adder, and is added in the next calculation.

Abstract: A process transmitter includes a circuit producing a plurality of digital values representing magnitudes for an analog signal and a filter receiving the plurality of digital values and producing a plurality of filtered digital values. Output analog circuitry in the process transmitter is configured to receive the filtered digital values and output an analog signal on a communication channel of the process transmitter. The output analog circuitry has a transfer function and the filter has a transfer function. The transfer function of the filter at least partially offsets the transfer function of the output analog circuitry.

Abstract: Techniques for auto-tuning anomaly detection are provided. In one technique, training data is stored that comprises training instances, each of which comprises a severity-duration pair and a label that indicates whether the severity-duration pair represents an anomaly. A model is trained based on a first subset of the training data. A second subset of the training data is identified where each training instance includes a positive label that indicates that that training instance represents an anomaly. Based on the second subset of the training data, the model generates multiple scores, each of which corresponds to a different training instance. A minimum score is identified that ensures a particular recall rate of the model. In response to receiving a particular severity-duration pair, the model generates a particular score for the particular severity-duration pair. A notification of an anomaly is generated if the particular score is greater than the minimum score.

Abstract: An image processing apparatus includes a core configured to perform a fast Fourier transformation (FFT) operation on the image data, a memory configured to store data that is output by the core, and a controller configured to control the core to perform the FFT operation on the image data. The core is resettable based on an amount of the image data.

Abstract: A method of increasing reliability of a wireless radio includes: creating a first waveform at a first center frequency of an encoded data stream using a first wireless radio; creating a second waveform at a second center frequency of the encoded data stream using the first wireless radio; combining the first waveform and the second waveform into a composite waveform with redundant data streams at different center frequencies using the first wireless radio; wirelessly transmitting the composite waveform using the first wireless radio; wirelessly receiving the composite waveform; filtering the received composite waveform using a first filter band; digitizing the received composite waveform using the second wireless radio; demodulating the digitized composite waveform into a first data stream and a second data stream with the second wireless radio; and creating a third data stream representative of the encoded data stream.

Abstract: A frequency converter comprising a frequency transposition block for samples (11Q_1, 11Q_2), a filtering block (12Q_1, 12Q_2), the filtered samples y(n) verifying y(n)=c(0)·x(n)+c(1)·x(n?1)+c(2)·x(n?2)+ . . . +c(p?1)·x(n?p+1)+c(p)·x(n?p)+c(p?1)·x(n?p?1)+ . . . + . . . +c(1)·x(n?2·p+1)+c(0)·x(n?2·p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0)·x(n), c(1)·x(n?1), c(2)·x(n?2), . . . , c(p)·x(n?p) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p?1)·x(n?p?1), . . . , c(1)·x(n?2·p+1), c(0)·x(n?2·p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(n?m); and determining y(n) by summation of the first and second terms.

Abstract: Aspects of the present invention provide techniques for compensating nonlinear impairments of a signal traversing an optical communications system. A parallel array of linear convolutional filters are configured to process a selected set of samples of the signal to generate an estimate of a nonlinear interference field. The predetermined set of samples comprises a first sample and a plurality of second samples. A processor applies the estimated nonlinear interference field to the first sample to least partially compensate the nonlinear impairment.

Abstract: A control facility for controlling a controlled system experiencing a disturbance includes a front nodal point receiving a target value and an actual value outputted by the controlled system and supplying a difference value corresponding to a difference between the target value and the actual value to a compensation circuit. The compensation circuit supplies a frequency-filtered and time-delayed signal formed as the sum of the weighted difference value and a weighted feedback signal as an input to a controller for the controlled system. The sum of a filter delay time and of first and second propagation delays is an integer multiple of the cycle duration of the disturbance, and a sum of the filter delay time and the first propagation delay is an integer multiple of the cycle duration minus a propagation time, which elapses until a change in the target value causes a change in the actual value.

Abstract: Systems, methods, and other embodiments associated with converting an input signal into an output signal with a different sampling rate. In one embodiment, an apparatus includes a feedforward circuit configured to receive the input signal comprised of discrete data samples with the first sampling rate and to generate a first intermediate value based, at least in part, on a feedforward coefficient and the input signal. The apparatus includes a feedback circuit configured to generate a second intermediate value that is based, at least in part, on a feedback coefficient and a predetermined number of previous samples of the output signal. The apparatus includes a signal combiner configured to combine the first intermediate value and the second intermediate value together to interpolate a data sample of the output signal at the second sampling rate. The output signal is a converted form of the input signal at the second sampling rate.

Abstract: A method for recovering a sparse signal of a finite field may include: updating discrete probability information of a target signal element of the finite field and discrete probability information of a measurement signal element of the finite field by exchanging the discrete probability information of the target signal element with the discrete probability information of the measurement signal element a predetermined number of times, wherein the target signal element and the measurement signal element are related to each other; calculating a final posteriori probability based on a priori probability of the target signal element and the discrete probability information of the measurement signal element, acquired as the exchange result; and recovering the target signal by performing maximum posteriori estimation to maximize the final posteriori probability.

Abstract: Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.

Abstract: A method and system for the design and implementation of an inverse-sinc function that can efficiently process signals produced by high-speed systems is presented. An integrated inverse-sinc module accepts multiple data streams that may result from parallel sub-systems and creates multiple outputs that can be interleaved to produce a sequence that has been filtered by an inverse-sinc function. The multiple-input, multiple-output system may be beneficially operated at a low data rate, such as the data rate used by each of the sub-systems.

Abstract: A signal processing device includes a bit-pattern output unit and a look-up table storage unit which are configured as follows: The bit-pattern output unit is provided for receiving input 1-bit digital signals generated by ?? modification and aligning bits of the input 1-bit digital signals in a chronological order to output parallel bit pattern. The look-up table storage unit is provided for storing a look-up table that represents a relationship between the bit patterns output from the bit pattern output unit and resulting values of a filtering arithmetic operation on the basis of the bit patterns. In the signal processing device, the bit patterns output from the bit-pattern output unit are provided as indexes. The indexes are referenced to output the resulting values of the filtering arithmetic operation corresponding to the bit patterns listed in the look-up table stored in the look-up table storage unit.

Abstract: An adaptive finite-impulse-response filter includes a series of taps; each tap has a corresponding value of tap coefficient. Values of tap coefficients are calculated to minimize a system error function. The solution is under-constrained, and some values of tap coefficients can grow and cause overflow errors. Growth of tap coefficients is controlled by introducing tap leakage. Disclosed is a symmetric leakage algorithm, in which an updated value of the tap coefficient of a particular tap is based on the old value of the tap coefficient of the particular tap, on the old values of the tap coefficients of a set of taps preceding the particular tap, and on the old values of the tap coefficients of a series of taps following the particular tap.

Abstract: Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.

Abstract: The present invention is directed toward a Finite Impulse Response (FIR) no-multiply filter (NMF), which replaces complex multiplications with phase additions. At each tap in the FIR filter, only phases are accumulated and at the output the complex result is reconstructed in I/Q. Noise dither is relied upon to smooth the digitized phase resolution. The NMF is ideally suited to a matched filtering scenario for constant modulus signals.

Abstract: Disclosed is a filter circuit, comprising a signal to be filtered, a difference circuit coupled to the signal to be filtered, a filter having an input coupled to the difference circuit, an integrator (or accumulator) having a first input coupled to an output of the filter circuit, and having a second input, and an accumulator coupled to an output of the integrator. A method of filtering is described also.

Abstract: An information processing device for processing reception signals converted into digital signals, includes: a first conversion unit for executing sampling rate conversion of each of the digital signals to be computed with each tap coefficient of a K'th-order FIR filter; a filter computing unit for executing computation processing of the K'th order FIR filter on K digital signals each of which have been subjected to sampling rate conversion by the first conversion unit; and a control unit for controlling sampling rate conversion of the digital signals by the first conversion unit, and the computation processing of the K'th order FIR filter by the filter computing unit.

Abstract: The VEA Detector and Dynamic Range Controller of the invention more accurately measure constant or non-constant, periodic or aperiodic, signals and the use of such measurements to control the upstream and/or downstream processing of program signals, including without limitation audio, video, and power program signals. The invention uses an antilog module acting within the context of a log domain circuit such that the “averaging” at an integrator is linear, not logarithmic. However, since the detection is within the log domain, the dynamic range of the VEA Detector is exponentially larger.

Abstract: Data rate conversion devices and methods are provided. A method for converting a first digital signal having a first sampling rate into a second digital signal having a sampling rate close to a predetermined second sampling rate comprises the following operations: when the ratio of the first sampling rate to the second sampling rate is a repeating infinite decimal, calculate at least two calibrating coefficient values and output the calibrating coefficient values according to a predetermined rule; conduct overflow operation on the output calibrating coefficient; and interpolate the first digital signal using the output calibrating coefficient and the result of the overflow operation to obtain the second digital signal such that during any period of a certain length along time axis, sampling times of the second digital signal equals to sampling times of the second sampling rate.

Abstract: A dynamic filtering device includes a variation detector, a coefficient generator and a filter. The cut-off frequency of the filter is dynamically adjusted according to variations of an input signal. A higher signal-to-noise ratio is obtained when a finger moves in slow motion and its response time is reduced when the finger moves in fast motion, therefore improving the response time and the noise immunity of the filter.

Abstract: A signal processing circuit has two types of filters: an IIR filter 11 and an FIR filter 12 having an equivalent transfer function at all times. In an adjustment mode in which the signal processing circuit is adjusted to have an arbitrary transfer function, the signal processing circuit makes a configuration setting to use the IIR filter 11. When completing the adjustment or in a signal processing mode, the signal processing circuit makes a configuration setting change to switch to the FIR filter 12 having the equivalent transfer function.

Abstract: Methods, circuits, and an apparatus for filtering high-speed serial data is disclosed. In one embodiment, a Programmable Logic Device (PLD) is configured with a filter circuit for filtering serial data at a first clock rate. The filter circuit converts an N number of serial data streams into an N number of M-bit words based on a deserialization factor. The M-bit words are converted to an M number of N-bit data words. The N-Bit data words are filtered at a second clock rate, reformatted, serialized, and outputted as individual serial data streams at the first clock rate. In one embodiment, the N-bit data words are digitally filtered by a Finite Impulse Response (FIR) filter operating at the second clock rate. The data output of the FIR filter is then serialized into an N number of serial data output streams operating at the first clock rate.

Abstract: A digital filter having improved overload characteristics provides improved performance in audio equalizers and other systems. In contrast to a standard digital filter, clipping is enforced at the output of the filter and an integrator is used to implement the first filter stage, which is then followed by another stage that may be a unit delay or an integrator. Scalers and combiners are provided to scale an input signal representation and the output signal representation and combine them to provide the particular coefficient inputs to the integrator and the second stage forming a direct form filter. The resulting filter implements the same transfer function as a corresponding direct form filter, with an improved recovery from internal overload conditions. Higher-order filters can be formed by cascading the second-order filters formed by multiple integrator/second stage pairs.

Abstract: A FIR filter (20) has a delay line comprising four delay elements (21a, 21b, 21c, 21d) for delaying a signal received at a filter input (22) and four multipliers (24a, 24b, 24c, 24d) for multiplying the delayed signals by respective partial filter coefficients a, b, c, d. The delay elements (21a, 21b, 21c, 21d) and multipliers (24a, 24b, 24c, 24d) are connected alternately in series. Four taps (23a, 23b, 23c, 23d) extract the signal from the delay line immediately after each of the delay elements (21a, 21b, 21c, 21d) and output the delayed, multiplied signals to an adder (25) for adding the delayed, multiplied signals to generate a filter output (26). The partial filter coefficients a, b, c, d effectively combine to implement filter coefficients A, B, C, D for the taps (23a, 23b, 23c, 23d), e.g. with A=a, B=a*b, C=a*b*c and D=a*b*c*d.

Abstract: The present disclosure provides a method and system for combining multiple coefficient words using only the magnitude bits of each of the coefficient words and using the sign bits of each of the coefficient words to modify the output of the combined magnitude bits. Using this method and/or system, it is possible to implement, for example, digital filters using larger coefficient word sizes without having to incur the inefficiencies and cost associated with using additional hardware resources, while maintaining an acceptable gain error in the filter response.

Abstract: A read channel of a magnetic recording apparatus includes a filter that uses filter coefficients to process the data detected by a read head from the magnetic recordable media. The coefficients change with time and circumstances. When data is read and found to pass error detection, the filter coefficient set used for the data is stored in a memory as a last good coefficient set. Upon failure of the filtering process, the coefficient set used is replaced with a coefficient set stored in the memory as the last good coefficient set.

Abstract: A read channel of a magnetic data storage device includes a filter to provide equalization of the signal being detected from the magnetic media. The filter utilizes coefficients for the filter response. The filter coefficients may drift sideways over time. The drift is detected and a correction is implemented by imposing a leakage on the coefficients to re-center the filter response. The leakage sign differs depending on the direction of drift detected.

Abstract: An information processing device for processing reception signals converted into digital signals, includes: a first conversion unit for executing sampling rate conversion of each of the digital signals to be computed with each tap coefficient of a K'th-order FIR filter; a filter computing unit for executing computation processing of the K'th order FIR filter on K digital signals each of which have been subjected to sampling rate conversion by the first conversion unit; and a control unit for controlling sampling rate conversion of the digital signals by the first conversion unit, and the computation processing of the K'th order FIR filter by the filter computing unit.

Abstract: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Abstract: A digital filter having the capability to completely prevent the digital filter from generating the overflow oscillation by detecting positive and negative overflow propagating one or a plurality of bits by means of an overflow detecting circuit. When overflow is detected, a clipping circuit serves to fix the output signal to a positive maximum value or a negative maximum value.

Abstract: A method and system of efficiently processing a discrete time input signal having a plurality of input signal samples that occur at a first clock rate into a discrete time output signal having a second clock rate that is R times the first clock rate is presented. The method includes receiving the input signal and filtering the input signal with an N-taps finite impulse response (FIR) filter having N filter coefficients. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

Abstract: An improved Finite Impulse Response (FIR) filter is presented which provides linear scalability and implementation without the need for delay lines. A multiprocessor architecture includes a plurality of ALUs (Arithmetic and Logic Unit), Multipliers units, Data cache, and Load/Store units sharing a common Instruction cache. A multi-port memory is also included. An assigning functionality assigns to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values.

Abstract: The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system.

Abstract: A digital decimation filter having FIR decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital IF stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.

Abstract: A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232, 240), multipliers (210, 220), and adders (208, 216, 228) for defining a transfer function, where the circuit corresponds in order and values to intrinsic values of the transfer function. The quantizers are connected in series after the multipliers to eliminate any double precision additions which give rise to the appearance of parasitic oscillations. The savings in hardware results from locating the quantizers after the multipliers; thus, eliminating all double precision additions that are mandatory in the classical second-order lattice structure. The second-order allpass filter coefficients that retain the limit-cycle-absent property of the filter correspond to specific guidelines.

Abstract: Wiring is variably connected between delay section 102 having N delay elements, D0 to DN-1, and multiplying section 104 having N multipliers, c(0) to c(N-1). Further, wiring is variably connected between multiplying section 104 and adding section 106 having N adders, K0 to KN-1. When the oversampling number of an input signal is dynamically varied, wiring control section 109 varies the wiring so as to obtain a filter structure with a number of parallels corresponding to the oversampling number. Thus, the finite impulse response filter is capable of responding to the dynamically varied oversampling number, and reducing its circuit size.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.

Abstract: A circuit arrangement and method utilize a programmable shifter coupled downstream of a multiplier to shift the product of an input value and a pre-scaled filter coefficient that implements a predetermined filter function. Through the judicious selection of an appropriate pre-scaled filter coefficient and a shift distance to shift the product, truncation errors associated with a digital implementation of a filter may be minimized, offering improved filter response compared to other discrete filter implementations with like coefficient resolution, or in the alternative, permitting acceptable filter response to be maintained with reduced coefficient resolution. Moreover, where the coefficient resolution is reduced, a filter may be implemented using relatively less space, less power consumption and less delay than in comparable conventional designs.

Abstract: The disclosed filter structure employs parallel first and second input signal data paths. The first data path includes a digital Finite Impulse Response (FIR) filter having a small number of non-zero multiplier coefficients to define its theoretical impulse frequency response. The second data path includes plural series filters including (1) a digital FIR or Infinite Impulse Response (IIR) filter including a reduced-number of designer-chosen non-zero multiplier coefficients that tend to introduce error sources in the physical-realized filter structure's impulse frequency response and (2) a set of one or more frequency stop filters, each of which permits zero signal transmission therethrough at a different selected frequency.

Abstract: A method of generating filter coefficients to provide a desired nth order filter response comprises adding one or more substantially co-located pole and zero pairs to form an (n+m)th order filter having the desired nth order filter response.

Abstract: A digital filter having the capability to completely prevent the digital filter from generating the overflow oscillation by detecting positive and negative overflow propagating one or a plurality of bits by means of an overflow detecting circuit. When overflow is detected, a clipping circuit serves to fix the output signal to a positive maximum value or a negative maximum value.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital filtering. The method comprises the steps of successively delaying each of the input values {x0,x1, . . . ,xN−1} to create tap values {t0,t1, . . . ,tN−1}, multiplying each of the tap values {t0,t1, . . . ,tN−1} by A•{h0,h1, . . . ,hN−1} to produce {At0h0,At1h1, . . . ,AtN−1hN−1}wherein values {h0,h1, . . . ,hN−1} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency in filtering the input data stream, summing the values {At0h0,At1h1, . . .

Abstract: A method and apparatus for performing filtering operations on video data using a limited amount of memory is accomplished by multiplying a first coefficient value and a first input value to produce a product. A random number is generated and added to the product to produce a dithered product. The dithered product is added to an accumulated value to produce a partial sum. A truncated version of the partial sum is stored in a buffer as the new accumulated value. The multiply and add operations are repeated for a number of coefficient values and input values such that the accumulated value includes contributions from a number of different input values. The resulting accumulated value is provided as an output.

Abstract: The object of the invention is to provide a technique of preventing the limit cycle, with a simplified structure, for the IIR digital filter adopting arithmetic operation part of finite word length. A digital filter shown in FIG. 1 includes an extracting means 2 to extract only 2 bits at a low end of an input signal S1 and to output the extracted signal; an amplifying means 3 to amplify the extracted signal at an amplitude level to a level larger than a critical input level of an IIR digital filter 1 and output the extracted signal as amplified; and an adding means 4 to add the input signal S1 and the extracted signal S3 as amplified and input them into the IIR digital filter 1.

Abstract: A filter system that filters a digital signal to produce a filtered digital signal where the digital signal has alternating first data values and second data values. The filter system includes a demultiplexer that produces a first signal that includes the first data values and a second signal that includes the second data values. A first filter is provided to filter the first signal and the second signal to produce a first filtered signal including filtered first data values. A second filter is provided to filter the first signal and the second signal to produce a second filtered signal including filtered second data values. A multiplexer alternately selects the filtered first data values and the filtered second data values to produce the filtered digital signal.