Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: A method (and structure) for performing a matrix subroutine, includes storing data for a matrix subroutine call in a computer memory in an increment block size that is based on a cache size.

Abstract: A method and system of accurately processing a discrete time input signal having a first clock rate into a discrete time output signal having a second clock rate is presented. The method includes delta filtering the input signal to produce an intermediate signal having the first clock rate and delta interpolating the intermediate signal to produce the output signal. Delta filtering includes calculating an input delta signal by subtracting an initial value from the input signal, generating a filtered delta signal, and adding the initial value to the filtered delta signal. Delta interpolating includes upsampling the intermediate signal to the second clock rate, calculating an upsampled intermediate delta signal by subtracting an initial value from the upsampled intermediate signal, filtering the intermediate delta signal, and adding the initial value to the filtered intermediate delta signal.

Abstract: A delta-sigma modulator. The novel delta-sigma modulator includes one or more filter stages arranged in cascade, wherein each filter stage includes a first circuit for generating a first output signal and second circuit for generating a second output signal; and a summing circuit for adding the first and second output signals from each of the filter stages. In an illustrative embodiment, the first circuit is a bandpass filter including an inductive-capacitive resonator and the second circuit is an integrator, which generates a second output signal that is orthogonal to the first output signal. The output of the summing circuit is digitized and then converted back to analog to provide a feedback signal. The feedback signal is subtracted from an input signal, and the resultant difference signal is input to a first filter stage.

Abstract: A method and apparatus for real-time derivation of precise digital clock edges and synchronous logic samples from a digital signal having a clock channel and at least one data channel acquires a plurality of temporally offset analog samples during each of a sequence of sample periods and from consecutive samples where there is a logic level transition estimates an edge time. From the edge times for the clock channel an offset is added and applied to the at least one data channel to determine the synchronous logic samples for the data channel at each offset clock edge time.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: A Finite Impulse Response (FIR) filter circuit (60) includes delay elements (63, 64, 66), multipliers (71, 72, 73, 74), a summing device (78), and a digital integrator (69) at the output of the FIR filter circuit (60). A method for processing data using the FIR filter circuit (60) includes differentially encoding data prior to storing or processing of the data. The method provides a technique for compressing data since less memory is needed to store derivative data. The method further includes integrating the derivative data using the digital integrator (69) to decompress the derivative data.

Abstract: A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A digital system for filtering a single bit input signal according to the transfer function H(z), wherein H(z) has a gain G, a pole at location b0, and a zero at location a0. The digital system filters the single bit input signal without using computationally expensive multibit multiplication. The digital system achieves these advantages with a digital circuit having a first gain stage generating a gain corrected signal, a delay element generating a delayed gain corrected signal, a feed-forward stage generating a feed-forward signal, and a summer for generating an output signal based upon the sum of the gain corrected signal, the delayed gain corrected signal and the feed-forward signal.

Abstract: A &pgr;/4 DQPSK modulator includes a rotated and offset &pgr;/4 encoder that provides encoded I, Q constellation indices values using positive integers. The positive integer I and Q values are input to a digital filter that provides filtered I, Q constellation indices values. These filtered values are then rotated and offset back to conventional &pgr;/4 DQPSK constellation values, modulated and transmitted. Since the rotated and offset &pgr;/4 encoder provides I, Q constellation indices as positive integers, the filters are implemented as multiplierless digital filters which significantly reduces the complexity of the filters. Specifically, the multiplierless digital filters can be implemented using shift registers and summers. In a preferred embodiment the filters are programmable. In addition, using positive integers to represent the rotated and offset &pgr;/4 signalling constellation indices allows the indices to be represented as a binary value with less bits in contrast to prior art systems.

Abstract: A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.

Abstract: Digital filtering is performed by receiving an L-bit block of 1-bit data samples, wherein L is greater than 1, and using the L-bit block of 1-bit data samples to select a corresponding one of 2L filter output values. Selection may be accomplished by using each of the L 1-bit data samples to determine a product value by alternatively selecting a corresponding filter coefficient or a negation of the filter coefficient, and then generating the corresponding one of the 2L filter output values by adding together the L product values. Alternatively, part or all of the L-bit block of 1-bit data samples may be used to address one or more memory structures having stored therein corresponding filter output values. When more than one memory structure is used, the outputs from the memories are added together to generate the filter result. In another aspect, a shift register and latch arrangement decimate the serially received 1-bit data samples, thereby allowing the filter result to be generated at the decimated rate.

Abstract: A signal processing system receives and mixes a plurality of analog input signals having a maximum frequency. Each analog input signal is connected to an input of a modulator producing a high frequency oversampled digital signal. Each high frequency oversampled signal is connected to an input of a first decimation filter which produces an intermediate frequency oversampled multiple bit signal. Each of the intermediate frequency oversampled signals is connected to a respective input of a first digital mixer which produces a single mixed multiple bit output signal. The single mixed multiple bit output signal is connected to a second decimation filter which produces a final digital output signal, at a frequency suitable for representing the mixed analog input signals.

Abstract: A filter system that filters a digital signal to produce a filtered digital signal where the digital signal has alternating first data values and second data values. The filter system includes a demultiplexer that produces a first signal that includes the first data values and a second signal that includes the second data values. A first filter is provided to filter the first signal and the second signal to produce a first filtered signal including filtered first data values. A second filter is provided to filter the first signal and the second signal to produce a second filtered signal including filtered second data values. A multiplexer alternately selects the filtered first data values and the filtered second data values to produce the filtered digital signal.