Matched Filter Type Patents (Class 708/314)
  • Patent number: 9927783
    Abstract: A control system for controlling operation of an electric appliance is provided. The control system includes a correlator digital filter configured to receive input signals including at least one target signal associated with operation of the electric appliance and extract the target signal from the input signal. The control system also includes a controller operatively coupled with the correlator digital filter and the electric appliance, where the controller is configured to receive the extracted target signal from the correlator digital filter.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: March 27, 2018
    Assignee: Emerson Electric Co.
    Inventor: John Broker
  • Patent number: 9638789
    Abstract: An embodiment relates to a method for processing input data that includes multiplying a portion of the input data with a first set of coefficients or with a second set of coefficients, wherein the first set of coefficients and the second set of coefficients are stored in a memory, wherein the first set of coefficients is used on phase modulated input data and wherein the second set of coefficients is used on input data that are not phase modulated.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies AG
    Inventors: André Roger, Romain Ygnace
  • Patent number: 9466301
    Abstract: A method and system has been developed and demonstrated which provides real-time frequency translation, frequency compression, and user selectable response time for non-deterministic signals. This method and system provides for the real-time separation and isolation of theoretically an infinite amount of frequencies present in an incoming non-deterministic signal. The bandwidth of the filter for the separated frequencies is user selectable and provides varying rise times for the individual frequencies. The linear frequency shifting property of the algorithm creates bandwidth compression opportunities while signals are present in a channel for transmission.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 11, 2016
    Inventor: Kenneth John Lannes
  • Patent number: 8977665
    Abstract: In one embodiment, a fault-aware matched filter augments the output of a component matched filter to provide both fault-aware matched filter output and a measure of confidence in the accuracy of the fault-aware matched filter output. In another embodiment, an optical flow engine derives, from a plurality of images, both optical flow output and a measure of confidence in the optical flow output. The measure of confidence may be derived using a fault-aware matched filter.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: March 10, 2015
    Assignee: Prioria Robotics, Inc.
    Inventor: Walter Lee Hunt, Jr.
  • Publication number: 20140059102
    Abstract: Aspects of a method and system for efficient full resolution correlation may include correlating a first signal with a second signal at a rate corresponding to a first discrete signal, wherein each sample of the first signal may be generated by summing a plurality of consecutive samples from the first discrete signal, and the second signal may be generated by summing the plurality of consecutive samples from a second discrete signal. The correlating may be performed by a matched filter and/or a correlator. The first signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the first discrete signal comprising N*L samples. The second signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the second discrete signal comprising N*L samples.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 27, 2014
    Applicant: Broadcom Corporation
    Inventors: Francis Swarts, Mark Kent
  • Patent number: 8605833
    Abstract: A signal processing apparatus for determining whether a receiving signal is a target signal is provided. The apparatus includes: a sampling device for sampling the receiving signal to generate a plurality of sampled values; a first calculation device, coupled to the sampling device, for generating a plurality of first values according to the sampled values and a plurality of reference values; a second calculation device, coupled to the first calculation device, for grouping the first values into a plurality of value groups, respectively calculating the value groups to generate a plurality of second values and generating a determination value by calculating the second values; and a determination device, coupled to the second calculation device, for determining whether the receiving signal is the target signal by comparing the determination value with a threshold value.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: December 10, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Tien-Hsin Ho, Shao Ping Hung, Tai Lai Tung
  • Patent number: 8571095
    Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: October 29, 2013
    Assignee: NEC Corporation
    Inventor: Shigeki Wada
  • Patent number: 8499019
    Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: July 30, 2013
    Assignee: Ross Video Limited
    Inventors: Yu Liu, David Allan Ross, Kizito Gysbertus Antonius Van Asten
  • Patent number: 8489662
    Abstract: Certain embodiments of the invention may include systems and methods for implementing a multirate digital interpolating filter. According to an example embodiment of the invention, the method includes sampling symbol data from one sample per symbol to N samples per symbol, wherein sampling includes: convolving the symbol data with a decimated finite impulse response (FIR) aperture impulse response coefficient set, convolving the symbol data with one or more shifted decimated FIR aperture impulse response coefficient sets, and summing the convolution results to produce interpolated bandlimited data.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: July 16, 2013
    Assignee: The Aerospace Corporation
    Inventor: John James Poklemba
  • Patent number: 8170089
    Abstract: Provided is an apparatus for channel equalization in frequency domain, including: a channel estimation unit for estimating a channel on received signal from outside, a channel matched filter for changing channel characteristic of the channel estimated by the channel estimation unit and the received signal to channel characteristic to meet condition required for noncausal filtering, a noncausal filter for changing the channel characteristic changed by the channel matched filter from nonminimum phase channel to minimum phase channel, a reverse channel calculation unit for calculating a reverse of the channel changed by the noncausal filter in frequency domain, and a frequency domain equalization unit for performing channel equalization with respect to the channel changed by the noncausal filter in the frequency domain by using the reverse obtained by the reverse channel calculation unit as coefficients of the frequency domain equalization apparatus.
    Type: Grant
    Filed: December 26, 2005
    Date of Patent: May 1, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Seung-Won Kim, Soo-In Lee, Sang-Won Son, You-Seok Lee, Hyoung-Nam Kim
  • Patent number: 8098782
    Abstract: A communications device includes pre-processing circuitry for processing a received wideband complex signal including an undesired narrowband interference component therein, and for determining a frequency of the undesired narrowband interference component. A filter is downstream from the pre-processing circuitry and operable to generate a received wideband complex signal with at least one frequency notch therein to suppress the undesired narrowband interference component. The filter includes a finite impulse response (FIR) filter with L taps to generate N output values, with L>N. A Fast Fourier Transform (FFT) block is downstream from the FIR filter and has a length N so that filter transition regions occur between frequency bins of the FFT block. A notching block is downstream from the FFT block to generate the frequency notch. An Inverse Fast Fourier Transform (IFFT) block is downstream from the notching block and has the length N.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: January 17, 2012
    Assignee: Harris Corporation
    Inventor: Mark Chamberlain
  • Patent number: 8077796
    Abstract: Systems and methods for utilizing new communication standards in wireless local area networks are provided that also support legacy wireless stations. The method can include user equipment determining channel state information, selecting a unitary channel decomposition precoder format based on the determined channel state information and transmitting the precoder format information to a base station. During a return transmission the user equipment can receive user data with the precoder format information and utilize a non-linear detector to demodulate and decode the user data. Based on the reception the user equipment can estimate channel quality; and transmitting channel quality information as feedback.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: December 13, 2011
    Assignee: Intel Corporation
    Inventors: Xiao-Feng Qi, Keith Holt
  • Patent number: 7961776
    Abstract: A device for decoding a direct sequence spread spectrum-encoded binary message includes a sampler that captures at least one sequence of binary samples corresponding to one bit of the transmitted message. The captured sequence of samples are applied to a filter matched to the spreading code used, thus making it possible to delete the spreading applied to the original message. The device further includes, at the output of the sampler, an error correction block including a memory storing a plurality of binary sequences corresponding to all of the possible values for a captured sequence of samples. A replacement circuit replaces the captured sequence of samples with the stored sequence, thereby minimizing the number of samples different from the captured sequence of samples, and allowing the stored sequence to be applied to the matched filter.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: June 14, 2011
    Assignees: STMicroelectronics (Rousset) SAS, Universite de Provence d'Aix-Marseille I
    Inventors: Benoît Durand, Christophe Fraschini, Philippe Courmontagne, Stéphane Meilleire
  • Patent number: 7904841
    Abstract: A method and system is described for optimizing a digital filter defined by coefficients that are multiplied by input data and accumulated to generate output data. A factorization set of candidate factors is compiled based on the coefficients. For each of the candidate factors, an optimized solution is generated. To generate the optimized solution, the candidate factor is applied to the coefficients and a working set of terms is compiled. Terms in the working set are converted to power-of-two representations and grouped with other terms that have a common partial sum, or multiple of the partial sum, within their respective power-of-two representations. A reduction set is compiled from the grouped terms and an order of application is selected based on optimization objectives. The reduction set is then applied to the working set of terms to generate the optimized solution, which is ranked and stored based on the optimization objectives.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: March 8, 2011
    Assignee: Lockheed Martin Corporation
    Inventors: Walter Vincent Dixon, III, Mark Richard Gilder
  • Patent number: 7817754
    Abstract: Performing approximate diagonalization of a correlation metric by user permutation to improve Multiuser Detector (MUD) processing. The system reorders the entries in the S-Matrix in order to move the bit decisions closer together in the decision tree. In one embodiment the reordering is a sequential pairwise correlation.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: October 19, 2010
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Robert B. MacLeod
  • Publication number: 20100262425
    Abstract: Disclosed is a noise suppression device capable of better noise suppression by means of a simpler structure and with a lighter computational load. A noise suppression device (100) has a noise suppression processor (150) to estimate the required information only from the observed information, which is the required information corrupted by noise. A correlator (154) calculates the correlation of the estimation error when the state quantity, which contains the required information, of the system at time n+1 was estimated from the information until time n or time n+1 for the observed information at only time n.
    Type: Application
    Filed: March 18, 2009
    Publication date: October 14, 2010
    Applicant: Tokyo University of Science Educational Foundation Administrative Organization
    Inventors: Nari Tanabe, Toshihiro Furukawa
  • Patent number: 7640282
    Abstract: A signal is filtered by multiplying its Fourier transform by the Fourier transform of a reference sequence to which the filtering is to be matched. The reference sequence (e.g. a Golay sequence pair) is defined as an iterative combination of shorter sequences and its Fourier transform is generated by an iterative process of combining the Fourier transforms of a shorter starting sequence.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: December 29, 2009
    Assignee: British Telecommunications PLC
    Inventor: Robert H Kirkby
  • Patent number: 7606339
    Abstract: An information handling system includes a wireless device and interference suppression apparatus that adapts to the different interference problems experienced by the wireless device when the system changes from one operating mode or state to another. The interference suppression apparatus includes a controller that instructs an adaptive filter with respect to the appropriate filter characteristics to employ to suppress interference when the system is operating in a first mode. When the system changes to a second mode of operation, the interference suppression apparatus updates the filter characteristics to filter characteristics which are appropriate for suppressing interference associated with the second mode of operation.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: October 20, 2009
    Assignee: Dell Products L.P.
    Inventors: Fahd Pirzada, Kaushik Ghosh
  • Patent number: 7474147
    Abstract: A method and apparatus for a frequency shift keying (FSK) demodulator use a configuration to improve the autocorrelation for better receiver performance. The demodulator uses parallel first and second lines connected to the same input signal, the first line having a delay element to provide an integer-delay of M, the second parallel line having a filter for causing a group delay of ?+M where ? is fractional, and a multiplier for receiving the signals from said first and second lines and generating a resultant signal from which a base band signal can be recovered. The resultant signal is passed through a low pass base band filter to recover the base band signal. ? may have a value of 3.25 and M may be 6. The demodulator may selectively be implemented in caller ID service and in low end modems chosen from a group comprising V.21, Bell 103, V.23 and Bell 202A modems.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: January 6, 2009
    Assignee: Ittiam Systems (P) Ltd.
    Inventor: Gopinath Patra
  • Patent number: 7466781
    Abstract: Apparatuses, methods, and articles of manufacture disclosing a filter with a plurality of convolver branches are described herein. Each of the plurality of convolver branches include a multiplier, integrator, and sampler and hold circuit. A sampled output of one branch may be fed back to another branch. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Dmitry Petrov, Lev Smolyar
  • Patent number: 7460983
    Abstract: A method and apparatus adapted to calibrate a signal path of a signal analysis system such that loading effects of the system are substantially removed from measurements of a device under test. A signal under test from the device under test is coupled to a test probe in the signal path and used with selectable impedance loads in the test probe to characterize transfer parameters of the device under test. An equalization filter in either the frequency or time domain is computed from the device under test transfer parameters for reducing in signal error attributable to the measurement loading of the device under test.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: December 2, 2008
    Assignee: Tektronix, Inc.
    Inventors: John J. Pickerd, Kan Tan, William A. Hagerup, Rolf P. Anderson, Sharon M. Mc Masters
  • Publication number: 20080294708
    Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. Substantially the same hardware can be utilized for processing in-phase and quadrature phase components of the data word (X0-XM-1). The coefficients (C0-CM-1) can represent real numbers and/or complex numbers. The coefficients (C0-CM-1) can be represented with a single bit or with multiple bits (e.g., magnitude). The coefficients (C0-CM-1) represent, for example, a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.
    Type: Application
    Filed: January 24, 2008
    Publication date: November 27, 2008
    Applicant: ParkerVision, Inc.
    Inventors: Gregory S. Rawlins, Ray Kassel
  • Patent number: 7454453
    Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM?1) with encoding coefficients (C0-CM?1), wherein each of (X0-XM?1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. X0 is multiplied by each state (C0(0) through C0(k?1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k?1). This is repeated for data bits (X1-XM?1) and corresponding coefficients (C1-CM?1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated until a final layer of results is generated.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 18, 2008
    Assignee: ParkerVision, Inc.
    Inventors: Gregory S. Rawlins, Ray Kassel
  • Publication number: 20080243982
    Abstract: In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Eliahou Arviv, Robert L. Lang, Yi-Chen Li, Oliver Ridler, Xiao-an Wang
  • Patent number: 7418065
    Abstract: A multicarrier receiver sequentially correlates two training symbols to determine a length of a cyclic prefix associated with each of the training symbols.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: Sigang Qiu, Minh-Anh Vuong, Atul Salvekar, Xiaoshu Qian
  • Patent number: 7340019
    Abstract: Briefly, in accordance with one embodiment of the invention, a programmable filter may implement an infinite impulse response filter so that a transceiver in which the filter is utilized may be programmable to operate in one or more modes in accordance with one or more communication standards. The programmable infinite impulse response filter may replace one or more analog filters of the transceiver so that a desired filter response may be programmed by a baseband processor. Delay functions of an infinite impulse response filter may be implemented using feedback and multiplexing.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventors: Dmitry Petrov, Lev Smolyar
  • Patent number: 7330522
    Abstract: An apparatus of sequentially decoding CCK codes includes a series of received signal registers used to respectively temporarily save the received signals, a phase selector used to select one numeral from 1, ?1, j or ?j respectively for CCK code of each chip to multiple with the signal register, a series of adders used to sequentially complete adding operation, a series of sequential operation registers used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders, and a comparing device used to select a maximal value from those saved in the operation registers. The comparing device includes a comparator and a maximum register. According to the invention, the data processing speeds up while the hardware complexity is reduced.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: February 12, 2008
    Assignee: Integrated System Solution Corp.
    Inventors: Chen-Yen Huang, Kuang-Ping Ma, Chun-Chang Lin, Albert Chen
  • Patent number: 7295624
    Abstract: A wireless receiver for receiving signals from an interference-limited transmitter in an interference-limited system comprising at least one transmit antenna, wherein the signals comprise a plurality of symbols. The receiver comprises a plurality of receive antennas and collection circuitry for collecting a plurality of signal samples with at least one symbol and interference effects. The receiver also comprises suppression circuitry, accumulation circuitry, circuitry for providing estimates of a group of bits, error detection circuitry and circuitry for requesting the transmitter to transmit a retransmission of a packet in response to detecting an error.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Eko N. Onggosanusi, Anand G Dabak, Timothy M. Schmidl
  • Patent number: 7233969
    Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0–XM?) with encoding coefficients (C0–CM?1), wherein each of (X0–XM?1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k?1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k?1). This is repeating for data bits (X1–XM?1) and corresponding coefficients (C1–CM?1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: June 19, 2007
    Assignee: ParkerVision, Inc.
    Inventors: Gregory S. Rawlins, Michael W. Rawlins, David F. Sorrells
  • Patent number: 7161528
    Abstract: The invention relates to a method of suppressing pulsed signals in particular of DME or TACAN type present in the radio signals received (Ue) by a radio-frequency receiver, characterized in that the reception frequency band of the receiver is divided into frequency sub-bands corresponding to the transmission channels of the pulsed signals, in that the presence of the pulsed signals and the transmission channel of said pulsed signals in the frequency sub-bands are detected, and in that the frequency sub-band comprising the detected pulsed signals is filtered over the duration of the pulsed signal so as to eliminate said pulsed signals pulse type.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 9, 2007
    Assignee: Thales
    Inventors: Estelle Kirby, Alain Renard
  • Patent number: 7039091
    Abstract: A method for managing a code sequence according to a first embodiment of the present invention is disclosed. Sets of n contiguous sample values that include sample values in a plurality of sample sequences are accessed. Sets of n contiguous coefficients are accessed. The sample values in each of the plurality of sets of sample values that are accessed are processed in parallel with corresponding coefficients that are accessed. Each of the plurality of sets of sample values are processed during a different time step.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: May 2, 2006
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 7010559
    Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k-1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k-1). This is repeating for data bits (X1-XM-1) and corresponding coefficients (C1-CM-1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: March 7, 2006
    Assignee: ParkerVision, Inc.
    Inventors: Gregory S. Rawlins, Michael W. Rawlins, David F. Sorrells
  • Patent number: 6868109
    Abstract: A receiving system or a received radio-wave estimation method is provided that can maintain received field strengths at a nearly uniform level under multipath conditions. The antenna switch can select outputs of four antennas at high speed. The high-frequency amplifier amplifies the output of the antenna switch and the demodulator demodulates amplified signals. The matched filter bank, surrounded with chain lines, receives a demodulated signal, for example, the I-phase component. In the matched filter bank, the phase shifter shifts respective signals output from four delay elements. The adder synthesizes the phase-shifted signals and then supplies the maximum matched output to the maximum level selector.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: March 15, 2005
    Assignee: Futaba Corporation
    Inventors: Ryuji Kohno, Satoru Ishii
  • Patent number: 6862323
    Abstract: Disclosed are a low pass filter, and a direct conversion receiver (DCR) implementing the same, which filter and second signal channels with improved phase and gain match, allowing use of the filter and DCR in wideband environments. A first M-pole filter channel, comprised of a first plurality of 2-pole active filter stages, filters the first signal channel. A second M-pole filter channel, comprised of a second plurality of 2-pole active filter stages, filters the second signal channel. One of the second plurality of 2-pole filter stages includes two variable components. The values of the variable components of the second M-pole filter channel are adjusted to match the gain and phase of the first and second filter channels.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: March 1, 2005
    Assignee: Rockwell Collins
    Inventor: Roger K. Loper
  • Patent number: 6816621
    Abstract: A novel method is presented for implementing a filter for processing a discrete signal having the steps of first obtaining a plurality of sample values from the discrete signal; then using each sample value to retrieve a bit vector from a plurality of tables. Afterwhich, a logical AND step is performed on the set of retrieved bit vectors; and a determination is made as to whether the resultant bit vector is comprised of all zeros or not. If so, then a predetermined default action is performed, otherwise the position of a non-zero bit in the bit vector is determined and the non-zero bit position is then used to generate a value of the filter.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: November 9, 2004
    Assignee: Xerox Corporation
    Inventor: John C. Handley
  • Patent number: 6775684
    Abstract: A digital matched filter has a serial-to-parallel conversion circuit that converts input data fed thereto in serial form into n sets of parallel data and a plurality of delay circuits that each output serial data fed thereto with a delay corresponding to n sets of data. The serial-to-parallel conversion circuit and the delay circuits are each fed with n clocks having different phases, and are composed of delay devices connected in n groups of serially connected delay devices so that the input data is shifted in synchronism with the rising edges of those n clocks. The outputs from the individual delay devices are multiplied by codes by multipliers, and the results of those multiplications are added together and output as output data by an adder.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: August 10, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinji Toyoyama, Yuichi Sato
  • Patent number: 6772182
    Abstract: A matched-phase noise filter includes an analog to digital converter (ADC) for receiving an analog composite, noise-dominated signal containing a signal of interest and producing a digital composite signal, an input/output port receiving the digital composite signal and providing a matched-phase signal, and a processor receiving the digital composite signal via the I/O port and generating the matched-phase signal. According to one aspect of the invention, the signal to noise ratio between the signal of interest and a noise component within the digital composite signal is increased by approximately an order of magnitude, based on an actual spectrum of the digital composite signal and an estimated spectrum of the noise component, and independent of the particular form of the signal of interest. A method of matched-phase noise filtering for improving the SNR of a noise dominated signal independent of the form of the signal is also described.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: August 3, 2004
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: B. Edward McDonald, Gregory J. Orris, William A. Kuperman
  • Patent number: 6700490
    Abstract: Digital implementation of electronic article surveillance (EAS) detection filtering for pulsed EAS systems is provided. Embodiments include direct implementation as a quadrature matched filter bank, as an envelope detector, a correlation receiver, and as a discrete Fourier transform. Pre-detection nonlinear filtering is also provided for impulsive noise environments.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: March 2, 2004
    Assignee: Sensormatic Electronics Corporation
    Inventor: Thomas J. Frederick
  • Publication number: 20030193995
    Abstract: A digital matched filter receives an input signal in natural order, correlates the input signal against a code and generates a filtered output signal in a permuted order with respect to the input signal. The code is a factorization of a first and second patterns. The filter includes a first filter to correlate against the first code and a second filter to correlate against the second pattern. A memory is included to store intermediate values produced from the first filter correlation operation. Certain ones of the intermediate values are selectively retrieved from memory in accordance with a unique addressing scheme for each second filter correlation operation. More specifically, the addressing scheme allows retrieved intermediate values to be reused in successive second filter correlations. The permuted order outputs of the filter are of no concern in many applications, like cell searching, where buffering is available.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 16, 2003
    Inventors: Nicolas Darbel, Sylvain Guilley
  • Publication number: 20030138030
    Abstract: A configurable cellular terminal engine (CTE) in accordance with an exemplary embodiment of this invention is configurable by an external agent (e.g., microcontroller, DSP, or state machine) to suit the particular requirements of different spread spectrum systems. In an exemplary embodiment, the CTE comprises on a chipset a modem unit and a channel codec unit. The modem unit has a front end unit for coupling to an antenna; a matched filter searchers unit coupled at least to the front end unit; a searchers unit coupled to at least the front end unit; a finger processing unit coupled to the front end unit; a parameter estimation processor unit coupled to at least the finger processing unit and the searchers unit; and a transmitter unit. The channel codec unit has a channel decoder unit coupled at least to the finger processing unit; and a channel encoder coupled at least to the transmitter unit.
    Type: Application
    Filed: August 2, 2002
    Publication date: July 24, 2003
    Inventors: Stratis Gavnoudias, Joseph Boccuzzi, Alexander Jacques, Raj M. Misra, Yan Zhang, Avi Silverberg, Richard Rizza, Yosef Nacson
  • Patent number: 6516020
    Abstract: Despreading codes are switched at effective timings to perform despreading calculations by providing a rate difference between the first clock signal to input a spread signal to be subjected to the correlation detection to a data holding section and the second clock signal to switch a despreading code used to detect the correlation of the spread signal held in the data holding section.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: February 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoyuki Kurihara
  • Patent number: 6512785
    Abstract: A matched filter bank including a plurality of matched filters and a sampling and holding units commonly used by the total matched filters. Therefore, the circuit size is diminished. An inverting amplifier for the matched filter with a variable gain includes an input capacitance, an inverting amplifier connected to an output of the input capacitance, and a plurality of feedback capacitances connected between an input and output of the inverting amplifier. A plurality of switches are connected to input side of the feedback capacitances for alternatively connecting the feedback capcitanec to the input of the inverting amplifier or a reference voltage. The feedback capacitances connected to the reference voltage are invalid with respect to a composite capacitance of the feedback capacitance and have no influence to the amplifier.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: January 28, 2003
    Assignee: Yozan Inc.
    Inventors: Changming Zhou, Xuping Zhou, Kunihiko Suzuki, Xiaoxing Zhang, Takashi Tomatsu
  • Patent number: 6456646
    Abstract: Methods and systems are provided whereby correlations between a received signal sample set and a plurality of potential codeword data set are determined and a potential codeword with the highest correlation value is selected as the decoded codeword. The correlation of a potential codeword may be determined by computing a squared magnitude of correlation values between the potential codeword and the received sample set starting at various time points and then summing the squared magnitudes of the correlation values at those points. The number of time points used for correlation computation and summing depends on the time spread of the received symbol pulse. Furthermore, the correlations may be weighted before summing.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: September 24, 2002
    Assignee: Ericsson Inc.
    Inventors: Ramanathan Asokan, Gregory E. Bottomley
  • Patent number: 6445756
    Abstract: A peak detecting circuit capable of accurately detecting a peak of a time discrete signal without increasing a circuit scale. The peak detecting circuit detects a peak of a waveform of a time discrete signal by calculating an approximate function which approximates the waveform of the time discrete signal. A peak of the approximate function is detected according to parameters of the approximate function so that the peak of the approximate function is estimated as the peak of the waveform of the time discrete signal.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: September 3, 2002
    Assignee: Ricoh Company, Ltd.
    Inventor: Satoshi Takahashi
  • Publication number: 20020061057
    Abstract: The present invention provides a digital filter which is used for a transmitter receiver in a mobile communication system and is capable of reducing the circuit scale.
    Type: Application
    Filed: November 16, 2001
    Publication date: May 23, 2002
    Inventors: Makoto Wakamatsu, Jun Watanabe
  • Patent number: 6366938
    Abstract: A technique for correlating a sequence of signal sample values with a predetermined digital code to produce correlation values for shifts in the sequence of signal sample values relative to the predetermined digital code is disclosed. The technique is realized by combining subgroups of the signal sample values in the sequence to form sets of precombinations, and then selecting one precombination from each set of precombinations to provide a plurality of selected precombinations. The plurality of selected precombinations are then added or subtracted to produce a correlation value corresponding to a shift in the sequence of signal sample values.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: April 2, 2002
    Assignee: Ericsson, Inc.
    Inventors: Jacob Levison, Paul W. Dent
  • Patent number: 6363108
    Abstract: A novel and improved method and apparatus for searching is described. Channel data is despread utilizing a matched filter structure. The in-phase and quadrature amplitudes of the despreading delivered to coherent accumulators to sum for a programmable duration of time. The amplitude accumulations are squared and summed to produce an energy measurement. The energy measurement is accumulated for a second programmable time to perform non-coherent accumulation. The resulting value is used to determine the likelihood of a pilot signal at that offset. Each matched filter structure comprises an N-value shift register for receiving data, a programmable bank of taps to perform despreading and optional Walsh decovering, and an adder structure to sum the resulting filter tap calculations.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: March 26, 2002
    Assignee: Qualcomm Inc.
    Inventors: Avneesh Agrawal, Qiuzhen Zou
  • Publication number: 20010038667
    Abstract: A matched filter requiring no high-speed processor and which consumes less power is disclosed. Partial filters 301-30N obtained by dividing number of matched filter taps by N are provided with a controller 341 for controlling which partial filters are enabled. The controller 341 is supplied with maximum amount of delay of an input signal and with symbol timing. On the basis of the maximum amount of delay, the controller 341 enables only the minimum number of partial filters 301-30n that are capable of executing an amount of computation that is required in one symbol period. The enabled partial filters are used multiple number of times per symbol period and the output, each time, integrated sample by sample. Since the disabled partial filters will not operate, it is possible to reduce power consumption and computation time.
    Type: Application
    Filed: May 1, 2001
    Publication date: November 8, 2001
    Inventors: Kenzo Urabe, Kazushige Yamamoto
  • Patent number: 6304591
    Abstract: The present invention is a match filter architecture that is used in the Spread ALOHA Multiple Access (SAMA) receiver to facilitate the separation of individual user's data from the incoming SAMA sample “chip” stream. The filter outputs the convolution of the incoming signals with the matched filter impulse response at the same rate as the sampling of incoming chips, thus providing a means to detect more than one user within one match pattern interval. The filter operates completely synchronously with a high frequency filter clock, which is used to generate the sample clock. Incoming chip samples are loaded in the delay shift register at the sample clock rate. The samples are shifted at the filter clock frequency. Each bit in the chip trickles down through serial adders, with one clock period of delay for each serial adder. At the final accumulator, the serial sum bits are collected for parallel presentation to output registers at the sampling frequency.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: October 16, 2001
    Assignee: ALOHA Networks, Inc.
    Inventor: Carin Wethington
  • Publication number: 20010009575
    Abstract: A matched filter has a circuit calculating an exclusive-OR of two input data, a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively, and a correlation processor. The correlation processor, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.
    Type: Application
    Filed: November 30, 2000
    Publication date: July 26, 2001
    Inventors: Shinji Toyoyama, Yuichi Sato