Abstract: A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.

Abstract: Methods and systems for non-destructive, stabilization-based encoder optimization. A video item to be provided to one or more users of a platform is identified. An indication of a motion is identified between an initial video frame of a video sequence associated with the video item and a subsequent video frame of the video sequence. One or more motion stabilization transformations are applied to the video item to modify the motion between at least the initial frame and the subsequent frame. Upon applying the one or more motion stabilization transformations to the video item, the video item is encoded. The encoded video item and one or more instructions to cause the client device to reverse the one or more motion stabilization transformations applied to the video item after decoding the encoded video item are transmitted to a client device connected to the platform.

Abstract: An arithmetic circuit includes a LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] that are sums of products of data x[m, n] of a data set X[m] containing M pairs of data x[m, n] and the coefficients c[n], in parallel for each of the M pairs. The distributed arithmetic circuit (2-m) includes binomial distributed arithmetic circuits that, for each of the pairs, calculate sums of products of a value obtained by pairing N data x[m, n] corresponding to the circuit two by two and a value obtained by pairing the coefficients c[n] two by two, and a figure matching circuit that matches a number of decimal figures of the sums with a predetermined number of decimal figures.

Abstract: A device for signal processing includes a signal input, a control input, and a CIC filter of an nth order for filtering the input signal. The CIC filter includes n integrators, which are disposed one behind the other and include a memory in each case, and n is greater than one. For each of n?1 first integrators, the device includes an associated correction calculator for correcting an integration error using at least one signal value stored in the memory of the respective first integrator. The device transmits these stored signal values in response to the control signal to the associated correction calculators and to delete the memory of the remaining last integrator. Either the memories of the n?1 first integrators are also deleted, or the device includes a further correction calculator and the signal values are transmitted in response to the control signal also to the further correction calculator.

Abstract: A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.

Abstract: Techniques for identifying a wake word by a device that is also playing audio content at the same time are described herein. For example, a device may execute playback of an audio file with a corresponding first variable wave form. The device may receive a second variable wave form that includes the first variable wave form and additional audio. In embodiments, a latency value may be identified based on comparing amplitudes and frequencies of portions of the first variable wave form and the second variable wave form. The second variable wave form may be modified by applying the latency value and inverting the second variable wave form with respect to the first variable wave form. The modified variable wave form may be merged with the first variable wave form to generate a merged variable wave form. A particular audio signal may be identified in the merged variable wave form.

Abstract: A band-pass filter is described comprising a first first-order filter stage comprising a first resistor characterized by a first impedance and connected to a first node, referred to as a filter input node, and, through a second node to a first reactive component connected to a third node, the first impedance being such that a first current therethrough is dependent on the difference between the voltages at the first and second nodes; and a second first-order filter stage comprising a second resistor characterized by a second impedance and connected to the second node, and, through a fourth node, to a second reactive component connected to a fifth node. The second impedance is such that a second current therethrough is dependent on the negative of the sum of the voltages at the second and fourth nodes. The band-pass filter further comprises summing means for summing the voltages at the second and fourth nodes to output a voltage at a sixth node.

Abstract: A finite impulse response (FIR) filter that implements a shifting coefficients architecture is provided. A shifting coefficients architecture can allow for the data samples being processed by the FIR filter by shifting the coefficients rather than the data. In one or more examples, the shifting coefficients architecture includes one or more delay tap lines that store data samples, and one or more shift registers that store coefficients. At every clock cycle, only the oldest data sample stored in the delay tap lines is updated with a new sample, while the other data samples remain static. Concurrently, each coefficient can be shifted by one register. Then each coefficient can be multiplied with a corresponding data sample, and the results can be aggregated to generate an FIR filter output.

Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.

Abstract: Sample-and-hold device for an electrical signal including an input module having two inputs, including a first switching block including two input switches, each input of the input module being connected at the input of one of the input switches, the input module being connected at the input of a first track-and-hold module with two inputs and two outputs, so as to alternately convey the signal from one of the two inputs to one of the two inputs of the first track-and-hold module; the device including a second track-and-hold module connected in parallel with the first track-and-hold module, these track-and-hold modules connected at the output of the first switching block, and an output module including a second switching block including two output switches, the outputs of the first and second track-and-hold modules being connected to the inputs of the output switches, to time interleave the output signals of the track-and-hold modules.

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract: An encoded data slice is received for storage by a dispersed storage and task (DST) execution unit. A plurality of initial integrity values are generated by executing a plurality of integrity check algorithms on the encoded data slice. The encoded data slice and the plurality of initial integrity values are stored in a memory of the DST execution unit. A subset of the plurality of integrity check algorithms are selected in response to a request to retrieve the encoded data slice. At least one final integrity value is generated by executing the subset of the plurality of integrity check algorithms on the encoded data slice stored in memory. An integrity status is generated by comparing the at least one final integrity value to the corresponding subset of the plurality of initial integrity values.

Abstract: A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

Abstract: A method of performing quadrature mirror filter (QMF) synthesis filtering includes recording new samples corresponding to a current time slot at positions of samples to be discarded in a first array that includes modulated QMF sub-band samples. The method further includes extracting samples from the first array to remove aliasing between adjacent sub-bands, determining filter coefficients corresponding to the extracted samples by using modulo operation, and synthesizing a time domain sample where aliasing is removed by using the extracted samples and the filter coefficients.

Abstract: A hosted application gateway server node may be communicatively coupled to backend systems, client devices, and database shards associated with database servers. Through the gateway server node, various services may be provided to managed containers running on client devices such that enterprise applications can be centrally managed. A sharding manager may manage relationships of database items across database shards. Each shard stores a copy of a table representing a split of a relationship. A shard ID mask is included in each item's ID. At query time, the shard ID can be extracted and used to query the correct database. This query routing mechanism allows navigation from one shard to another when multiple items are in a relationship (e.g., share the same resource such as a document). As such, embodiments can eliminate the need for APIs to join in data that span multiple shards.

Abstract: Multi-reliability regenerating (MRR) erasure codes are disclosed. The erasure codes can be used to encode and regenerate data. In particular, the regenerating erasure codes can be used to encode data included in at least one of two or more data messages to satisfy respective reliability requirements for the data. Encoded portions of data from one data message can be mixed with encoded or unencoded portions of data from a second data message and stored at a distributed storage system. This approach can be used to improve efficiency and performance of data storage and recovery in the event of failures of one or more nodes of a distributed storage system.

Abstract: Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.

Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

Abstract: Systems and methods are provided herein relating to audio matching. Interest points that are onsets are generally very efficient in audio matching in that they are robust to multiple types of distortion. Prominent onsets can be detected within an audio signal excerpt as interest points and combined as a function of a set of interest points to form a descriptor. Descriptors associated with an audio signal excerpt that contain a set of prominent onsets as interest points can be used in matching the audio signal excerpt to an audio reference. The benefits in generating and using prominent onsets within descriptors improve the accuracy of an audio matching system.

Abstract: A hybrid video decoder has an extractor, a predictor and a reconstructor. The extractor is configured to extract motion information and residual information for a first block of a current picture from a data stream. The predictor is configured to provide, depending on the motion information, a prediction for the block of the current picture by interpolating a reference picture, using a combination of an IIR filter and FIR filter. The reconstructor is configured to reconstruct the current picture at the block using the prediction for the block and the residual information for the block. Furthermore, a hybrid video encoder, a data stream, a method for encoding a video and a method for decoding a video are described.

Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.

Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a (64) channel filter bank using a prototype filter length of (640) coefficients and a system delay of (319) samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip.

Abstract: A reconfigurable digital signal filter processing unit for use in a communication device is provided. The reconfigurable filters processor can implement different filter topologies to adapt to a range or wireless technology characteristics. The reconfigurable filter processor comprises a plurality of filter blocks whose inputs can be selected based on the desired configuration of the filter. Each filter block applies a transfer function to a received signal to achieve a desired filtering function.

Abstract: A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow chaining of Direct Form II FIR filters into longer Direct Form II FIR filters. An output accumulator also allows the specialized multiplier block to operate as a time-division multiplexed FIR filter, performing several filtering operations during each clock cycle of the programmable device.

Abstract: Systems and methods for latency compensation are disclosed. In one embodiment, a computer-based system for latency compensation in a dynamic system comprises a processor and logic instructions stored in a tangible computer-readable medium coupled to the processor which, when executed by the processor, configure the processor to receive at least first parameter data from a first sensor and second parameter data from a second sensor, direct the at least first parameter data and the second parameter data into a combining filter, receive additional parameter data about the dynamic system from at least one additional sensor, construct a model of latency effects on the first parameter data and the second parameter data, and use the model of latency effects to compensate for latency-based differences in the first parameter data and the second parameter data.

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract: Provided is a signal processing apparatus for compensating for a non-linear distortion of a digital signal, including: an analysis signal generating section that converts the digital signal into a analysis signal of a complex number, using a digital filter; and a compensation section that compensates for the analysis signal, using a compensation coefficient of a complex number corresponding to the non-linear distortion, where the digital filter divides data of the digital signal into “n” data sequences, assigns (n*L+k)th data of the digital signal to a k-th data sequence, performs filtering on each of the data sequences using a same filter coefficient, and combines each of the data sequences after the filtering, thereby generating an imaginary number portion of the analysis signal, where “n” is an integer equal to or greater than 2, L=0, 1, . . . , and k=1, 2, . . . , n.

Abstract: An apparatus and method for aligning input and feedback signals in a transmission circuit are provided. The method includes capturing an input signal and a feedback signal, determining a first time delay between the input signal and the feedback signal, determining a second time delay between the input signal and the feedback signal, the determination of the second time delay having a higher resolution than the determination of the first time delay, and applying the first time delay and the second time delay to temporally align the input signal with the feedback signal. Use of the present invention provides an improved resolution of time alignment while reducing the overall complexity and cost of the transmission circuit.

Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

Abstract: A specialized processing block such as a DSP block may be enhanced by including direct connections that allow the block output to be directly connected to either the multiplier inputs or the adder inputs of another such block. A programmable integrated circuit device may includes a plurality of such specialized processing blocks. The specialized processing block includes a multiplier having two multiplicand inputs and a product output, an adder having as one adder input the product output of the multiplier, and having a second adder input and an adder output, a direct-connect output of the adder output to a first other one of the specialized processing block, and a direct-connect input from a second other one of the specialized processing block. The direct-connect input connects a direct-connect output of that second other one of the specialized processing block to a first one of the multiplicand inputs.

Abstract: A circuit and method for computing the circular convolution of an input signal with a finite impulse response operates to store initial input samples of the input signal, perform convolution of the remaining input samples in the block of input samples and then supplying the stored initial input samples for convolution, thereby generating circular convolution output samples.

Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Abstract: A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

Abstract: A digital filter is provided for radio communication processing capable of dynamically modifying the characteristic and simultaneously processing a plurality of systems. In the digital filter, calculation core groups capable of modifying function are arranged and connected to one another by an input interface unit and an output interface unit. When the communication mode is modified, the number of calculation resources to be used and setting contents are decided according to the setting candidate of the filter characteristic required and the calculation resource empty state.

Abstract: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter.

Abstract: A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.

Abstract: Aspects of a method and system for multi-band amplitude estimation and gain control in an audio CODEC are provided. In this regard, an audio signal may be filtered and delayed to generate one or more sub-band signals, a gain may be applied to each sub-band signal to generate one or more level adjusted sub-band signals, and the one or more level adjusted signals may be added to a delayed version of the audio signal. The gain applied to a particular one of the one or more sub-band signals may be controlled based on a detected amplitude of a summed signal derived by summing the particular one of the one or more sub-band signals and a corresponding one of the one or more level-adjusted sub-band signals.

Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data structures, groups or streams.

Abstract: An apparatus is provided. In the apparatus, an input to index (I2I) module maps a complex input into a real signal. A real data tap delay line is coupled to the I2I module and includes N delay-elements. A complex data tap delay line is configured to receive the complex input and includes M delay elements. A set of K of non-linear function modules is also provided. Each non-linear function module from the set has at least one real input, at least one complex input, and at least one complex output. A configurable connectivity crossbar multiplexer couples K of the N real tap delay line elements to real inputs of the set non-linear functions and couples K of the M complex tap delay line elements to complex inputs of the set non-linear function modules.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Abstract: A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality.

Abstract: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Abstract: A reconfigurable digital signal filter processing unit for use in a communication device is provided. The reconfigurable filters processor can implement different filter topologies to adapt to a range or wireless technology characteristics. The reconfigurable filter processor comprises a plurality of filter blocks whose inputs can be selected based on the desired configuration of the filter. Each filter block applies a transfer function to a received signal to achieve a desired filtering function.

Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.

Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a (64) channel filter bank using a prototype filter length of (640) coefficients and a system delay of (319) samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip.

Abstract: The present invention relates to an interpolation FIR (finite impulse response) filter having multiple data rates in a mobile communication system, and a method of filtering data using the same. In the method of filtering data using the interpolation FIR filter, a first filter uses an FIR low pass filter that restricts a band to satisfy a bandwidth corresponding to a data spectrum mask required in the mobile communication system. The other filters use interpolation FIR halfband filters that are implemented by a small number of taps. Accordingly, the interpolation FIR filter having multiple data rates can be easily implemented, and can be easily applied to the mobile communication system that transmits and receives data having various data rates.

Abstract: The present invention relates to a FIR filter process (1?) and to a respective FIR filter arrangement (1) wherein at least one multiplex mode is given which is characterized in that in the respective summation stage (30?) or summation block (30) partial summations are carried out and controlled in conformity with a multiplexed structure underlying a multiplexed input signal (MS) in order to obtain partial sums (?pk-1) as accordingly filtered single signals.

Abstract: Signal filtering and filter design techniques are disclosed. An interconnection circuit switchably couples an input and an output of an element that is operable to perform a signal filtering operation on a signal received at the input so as to provide a filtered signal at the output. This enables the element to be used to implement a series of cascaded signal filtering operations. An iterative filter design method and a data structure that enables control of the element and/or the interconnection circuit are also disclosed. According to another aspect of the invention, an element is operable to perform any of multiple signal filtering operations on a received input signal. Controlled selection of respective sets of filter parameters associated with the multiple signal filtering operations enables the element to be used to implement the signal filtering operations in parallel filtering paths.