Abstract: System and methods for shaped single carrier orthogonal frequency division multiplexing with low peak to average power ratio are provided. The system receives an input signal and modulates the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array where each Dirichlet kernel has a main lobe and a plurality of side lobes. Modulating the input signal suppresses a peak to average power ratio of the offset Dirichlet kernel output time array by reducing the plurality of side lobes of each Dirichlet kernel and respective amplitudes of the side lobes.

Abstract: Aspects of the disclosure are directed to a computation unit implementing a systolic array and configured for detecting errors while processing data on the systolic array. Checksum circuit in communication with a systolic array is configured to compute checksums and perform error detection while the systolic array processes input data. Instead of pre-generating checksums in input matrices, input matrices can be directly fed into the systolic array through the checksum circuit. On the output side, the checksum circuit can generate and compare checksums with checksums in an output matrix generated by the systolic array. Error checking the operations to generate the output matrix can be performed without delaying the operations of the systolic array, and without preprocessing the input matrices.

Abstract: A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.

Abstract: System and methods for shaped single carrier orthogonal frequency division multiplexing with low peak to average power ratio are provided. The system receives an input signal and modulates the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array where each Dirichlet kernel has a main lobe and a plurality of side lobes. Modulating the input signal suppresses a peak to average power ratio of the offset Dirichlet kernel output time array by reducing the plurality of side lobes of each Dirichlet kernel and respective amplitudes of the side lobes.

Abstract: Aspects of the disclosure are directed to a computation unit implementing a systolic array and configured for detecting errors while processing data on the systolic array. Checksum circuit in communication with a systolic array is configured to compute checksums and perform error detection while the systolic array processes input data. Instead of pre-generating checksums in input matrices, input matrices can be directly fed into the systolic array through the checksum circuit. On the output side, the checksum circuit can generate and compare checksums with checksums in an output matrix generated by the systolic array. Error checking the operations to generate the output matrix can be performed without delaying the operations of the systolic array, and without preprocessing the input matrices.

Abstract: A digital processor runs a machine learning algorithm in parallel with a sampling server. The sampling sever may continuously or intermittently draw samples for the machine learning algorithm during execution of the machine learning algorithm, for example on a given problem. The sampling server may run in parallel (e.g., concurrently, overlapping, simultaneously) with a quantum processor to draw samples from the quantum processor.

Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

Abstract: Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.

Abstract: Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

Abstract: A method and device for evaluating the performance of an industrial control loop based on full loop reconstruction simulations. The method comprises: performing reconstruction simulation on control modules one by one except a controlled object in the loop, and judging the correctness of the reconstructed modules; establishing a mathematical model of the object, connecting the mathematical model to the reconstructed modules to complete reconstruction of the entire loop, and optimizing the mathematical model of the object to obtain an optimized model of the object; adjusting parameters of the modules according to a control performance index, and performing simulation calculation on the reconstructed loop using the parameters to obtain an ideal value of the reconstructed performance control index for evaluating the performance of the loop. The loop is reconstructed, the influence of the modules, a PID controller, a filter, a piece-wise linear function and a deadband, on the performance is evaluated.

Abstract: A detection circuit (physical quantity detection circuit) includes a digital calculation circuit (calculation processing unit) that performs calculation processing of generating calculation data in response to magnitude of a physical quantity based on detection data formed by digitalization of a detection signal corresponding to the physical quantity. When N is an integer number equal to or larger than two, the digital calculation circuit performs the calculation processing including average processing of calculating an average value of N data values contained in at least one of the detection data and data obtained by performing part of the calculation processing.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values to one intermediate value.

Abstract: In general, the present invention relates to a method and system for synthesizing artificial reverberation using modal analysis of a room or resonating object. In one embodiment of the inventive system, a collection of resonant filters is employed, each driven by the source signal, and their outputs summed. With filter resonance frequencies and dampings tuned to the modal frequencies and decay times of the acoustic space or resonating object being simulated, and filter gains set according to the source and listener positions within the space or object, any number of acoustic spaces and resonant objects may be simulated.

Abstract: A method of digitally filtering an audio signal using an adjusted audio filter. The adjusted audio filter is represented by an impulse response including a waveform in its time domain represented by a sine function of absolute values. A composite audio filter is derived from two adjusted audio filters although any number of filters may be used. The composite audio filter generally includes a bank of the filters which together define a frequency bandwidth representative of the audio signal or spectrum to be filtered. Also a bandpass filter is constructed by combining frequency responses for sine components of absolute values integrated from 0 to bpf and sine components of absolute values integrated from 1/bpf to 0. The frequency response may be the sum of the frequency responses for each of the filters used to create the composite bandpass filter.

Abstract: In some embodiments, a multistage filter whose biquad filter stages are combined with latency between the stages, a system (e.g., an audio encoder or decoder) including such a filter, and methods for multistage biquad filtering. In typical embodiments, all biquad filter stages of the filter are operable independently to perform fully parallelized processing of data. In some embodiments, the inventive multistage filter includes a buffer memory, at least two biquad filter stages, and a controller coupled and configured to assert a single stream of instructions to the filter stages. Typically, the multistage filter is configured to perform multistage filtering of a block of input samples in a single processing loop with iteration over a sample index but without iteration over a biquadratic filter stage index.

Abstract: An accessory having an earbud for insertion into a user's ear is disclosed. The earbud may include a speaker and a microphone in which the speaker plays an audio signal for the user and the microphone receives the audio signal. The accessory includes a processor that is coupled to the speaker and the microphone to execute various operations. For example, the operations may include: determining a ratio of an energy estimation of the speaker audio signal to an energy estimation of the audio signal received by the microphone; determining a gain for the speaker audio signal based upon the ratio; based upon the gain, selecting a shelving filter; and applying the shelving filter to the speaker audio signal.

Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract: A smoothing apparatus for peak windowing includes an operator for generating a first input signal for smoothing using an input signal for peak windowing and a predetermined clipping threshold level. The apparatus also includes a subtractor for subtracting a feedback signal from the first input signal, and a maximum operator for generating a second input signal. The apparatus also includes a feedback path for generating a feedback signal for a next smoothed input signal by multiplying samples of the second input signal by window coefficients in a first window coefficient combination and a predetermined gain and summing up the multiplication results. The apparatus further includes a convolutional operator for generating a smoothed signal by multiplying samples of the second input signal by window coefficients in a second window coefficient combination for low pass filtering and summing up the multiplication results.

Abstract: One feature includes a method for implementing a fixed point recursive filter that reduces or eliminates steady state error. The method comprises obtaining a first filter state value, processing the first filter state value to remove a scaling factor to obtain a second filter state value, ascertaining that the recursive filter has reached a steady state, determining a nonlinear drift parameter based on a difference between the first filter state value and the second filter state value multiplied by the scaling factor, and adjusting the second filter state value with the nonlinear drift parameter to reduce steady state error of the recursive filter. Ascertaining that the recursive filter has reached the steady state may include determining that a filter output value at time n is equal to a filter output value at time n?1.

Abstract: A digital filter has a plurality of filters, wherein each filter performs coefficient multiplication and delay processing for an input signal and an output signal, obtains the output signal from the input signal, and includes a plurality of coefficient multipliers for multiplying a signal by a predetermined coefficient. The digital filter also includes a plurality of delay circuits for delaying a signal, and an adder for adding a plurality of signals. A first RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the first filter and stores delay data for the delay circuit of the second filter. A second RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the second filter and stores delay data for the delay circuit of the first filter.

Abstract: A technique for performing parallel-input parallel-output infinite impulse response (IIR) filtering uses two parallel-input-parallel-output finite impulse response (FIR) filters. One FIR filter is used as a feed-forward filter and one FIR filter is used as a feed-back filter. The feed-back filter is coupled to delays and summers to allow the filter operations to be performed in parallel.

Abstract: A digital filter for reducing a sampling rate for an input signal includes a parallelizing block for splitting the input signal into at least two parallel raw signals, an integration block for converting the parallel raw signals into an intermediate signal, and a differentiation block for generating an output signal by differentiating the intermediate signal. The integration block includes a logic block that is designed for generating two parallel sum signals from the parallel raw signals using summation operations, and a recursion block that is designed for generating the intermediate signal recursively from the parallel sum signals.

Abstract: A digital optimal filter having an especially sinusoidal pulse response uses a filter structure with a recursive and a transversal portion. The transversal portion comprises filter coefficients for the representation of scan results of half a period of the sinusoidal pulse response signal. The recursive filter structure is used to change the sign after generation of the scan results for half a period and to mark the start and the end of the pulse response. A plurality of periods can lie in between the start and the end of the pulse response, this is why the digital optimal filter can be used to extract especially sinusoidal burst signals from an original signal, namely in digital technology, which is advantageous for the implementation of IC's.

Abstract: A signal processing circuit has two types of filters: an IIR filter 11 and an FIR filter 12 having an equivalent transfer function at all times. In an adjustment mode in which the signal processing circuit is adjusted to have an arbitrary transfer function, the signal processing circuit makes a configuration setting to use the IIR filter 11. When completing the adjustment or in a signal processing mode, the signal processing circuit makes a configuration setting change to switch to the FIR filter 12 having the equivalent transfer function.

Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback signal may be generated using a sequence estimation process and a non-linearity function. A phase of the equalized ISC signal may be adjusted using the generated phase adjustment signal, to generate a phase adjusted partial response signal. The phase adjustment signal may be generated based on a phase difference between the equalized ISC signal and the partial response feedback signal. At least one ISC vector may be generated by buffering samples of the phase adjusted ISC signal.

Abstract: A digital all-pass filter has an input port leading to an input sum block and a first feed forward path. Within the first feed forward path is a multiplier. The filter also has an output port coupled to an output sum block that receives a signal from the first feed forward path. A first feedback path is also provided from the output port to the input sum block. The first feedback path includes a multiplier therein. Nested within this structure is a first order all-pass filter having a feed forward path including a forward path delay and forward path that is delayed and a feedback path absent a separate delay element and beginning after the forward path delay element.

Abstract: Computer-implementable recursive summation algorithms are disclosed that are useful for efficiently performing recursive convolution, such as is often required in Statistical Signal Analysis (SSA) techniques. The disclosed recursive summation algorithms can be more computationally-efficient from both a speed and memory perspective than other recursive convolution techniques known in the prior art, such as the techniques relying on Fast Fourier Transforms (FFTs).

Abstract: Digital signal-processing structure and methodology which feature a time-slice-based digital fabricating engine, and software operating structure operatively associated with that engine structured to operate the engine in a time-slice-based fabrication mode wherein the engine, in a time-differentiated and instantiating manner, functions to fabricate a time-succession of individual, composite wave digital filters. Each of these filters takes the form of (1) a concatenated assembly including one to a plurality of upstream, early-stage, decimate-by-two, signal-processing agencies connected in a cascade series arrangement, with each such agency possessing a first transfer function having a first transition bandwidth, and (2) a single, downstream, later-stage, decimate-by-two, signal-processing agency which possesses a second transfer function having a transition bandwidth which is less than the mentioned first transition bandwidth.

Abstract: The invention concerns a method and apparatus (28) for determining an angle (9) by means of a resolver (3). In the method, an excitation signal (29) of constant frequency is supplied to the resolver (3), the resolver response signals (13, 14) are measured, successive (16) measurements of each response signal are stored into a sample buffer (5), FIR filtering (10) is computed for the response signal values (16) present in the sample buffer (5) at the instant of computation, the computation points (23, 24) and the set of computation result values (18) corresponding to these points are stored in memory, at least two sets of values (18, 19) of computation results are compared to each other and of these the value set Amax (19) which contains the highest computation result as an unsigned value is selected, and FIR filtering (10) is repeatedly computed at the computation points (25, 26) corresponding to value set Amax (19).

Abstract: Provided is an apparatus of separating a musical sound source, which may re-construct mixed signals into target sound sources and other sound sources directly using sound source information performed using a predetermined musical instrument when the sound source information is present, thereby more effectively separating sound sources included in the mixed signal. The apparatus may include a Nonnegative Matrix Partial Co-Factorization (NMPCF) analysis unit to perform an NMPCF analysis on a mixed signal and a predetermined sound source signal using a sound source separation model, and to obtain a plurality of entity matrices based on the analysis result, and a target instrument signal separating unit to separate, from the mixed signal, a target instrument signal corresponding to the predetermined sound source signal by calculating an inner product between the plurality of entity matrices.

Abstract: A method of detecting and isolating at least one rhythmic component from a discrete-time input signal, comprises subjecting the input signal to discrete wavelet packet transform multi-resolution analysis; applying wavelet packet basis selection criteria to the result of the analysis to evaluate rhythmic signal features of the input signal; and isolating at least one rhythmic signal component from the input signal based on the evaluation.

Abstract: A signal separating device includes an iterative estimator, a repeating calculator, a result output unit, and a repetition controller. The repeating calculator repeatedly causes the iterative estimator to iteratively perform independent component analysis on an observed signal matrix, and to further perform independent component analysis on the source signal matrix obtained as a result. The result output unit outputs the product of the respective mixing matrices obtained during each repetition as a mixing matrix with respect to the observed signal matrix, while also outputting the source signal matrix obtained during the final repetition as a source signal matrix with respect to the observed signal matrix. The repetition controller causes the repeating calculator to repeat the calculation control until all mixing matrices and all source signal matrices satisfy a convergence condition. The iterative estimator may perform a fixed number of iterations, or perform iterations until convergence is obtained.

Abstract: One feature includes a method for implementing a fixed point recursive filter that reduces or eliminates steady state error. The method comprises obtaining a first filter state value, processing the first filter state value to remove a scaling factor to obtain a second filter state value, ascertaining that the recursive filter has reached a steady state, determining a nonlinear drift parameter based on a difference between the first filter state value and the second filter state value multiplied by the scaling factor, and adjusting the second filter state value with the nonlinear drift parameter to reduce steady state error of the recursive filter. Ascertaining that the recursive filter has reached the steady state may include determining that a filter output value at time n is equal to a filter output value at time n?1.

Abstract: A recursive approach to quantum computing employs an initial solution, determines intermediate solutions, evaluates the intermediate solutions and repeats using the intermediate solution, if the intermediate solution does not satisfy solution criteria. A best one of the intermediate solutions may be employed in the recursion.

Abstract: An improved method for reducing the accuracy requirements on the starting model when performing multi-scale inversion of seismic data (65) by local objective function optimization (64). The different scales of inversion are brought about by incorporating a low-pass filter into the objective function (61), and then decreasing the amount of high-frequency data that is filtered out from one scale to the next. Moreover, the filter is designed to be time varying, wherein the filter's low-pass cutoff frequency decreases with increasing traveltime of the seismic data being filtered (62). The filter may be designed using Pratt's criterion for eliminating local minima, and performing averages (or other statistical measure) of the period and the traveltime error only with respect to source and receiver location but not traveltime (63).

Abstract: Systems and techniques relating to processing information received from a spatially diverse transmission. In some implementations, an apparatus includes an input configured to receive data that has been transmitted over a wireless channel using multiple transmit antennas, nt, and multiple receive antennas, nr; and an equalizer responsive to multiple data streams corresponding to the multiple receive antennas and configured to generate an equalization matrix, Gntxnr, using a kernel matrix order updated from n(t?i)xn(r?j) to ntxnr, the kernel matrix updates being distributed across preamble processing operations. The input can be responsive to a selectable number of at least four antennas in an orthogonal frequency division multiplexed (OFDM) multiple-in-multiple-out (MIMO) system, and the equalizer can be configured to distribute the kernel matrix updates across multiple training fields of data preambles.

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: The invention relates to a hardware implemented filtering method including establishing a representation DIS of the derivative of at least a part of a time-quantized input signal IS, and establishing at least one sample of a time- and amplitude-quantized output signal OS by performing filtering on the basis of at least a part of a filter representation IFC1, IFC2, IFC3 and the representation DIS of the derivative of at least a part of the input signal IS. The invention further relates to a hardware implemented decimation method for decimating a time-quantized input signal IS including dividing the time-quantized input signal IS into intervals, for each of the intervals establishing a sample of a time- and amplitude-quantized output signal OS according to the above mentioned filtering method. The invention further relates to a fast filtering means FFM implementing the above-mentioned methods.

Abstract: Systems and techniques relating to processing information received from a spatially diverse transmission. In some implementations, a method comprises: obtaining a received signal that was transmitted over a wireless channel using spatially diverse transmission, the received signal comprising multiple subcarriers; and recursively computing a signal-to-noise-ratio (SNR) of the received signal while receiving channel response information of the wireless channel derived from the received signal; wherein the recursively computing comprises recursively updating a diagonal kernel matrix, the method further comprising generating an equalization matrix from the recursively updated diagonal kernel matrix, the equalization matrix being useable in equalizing the received signal across the multiple subcarriers.

Abstract: A filtering integrated circuit comprises: a storing circuit; a filter coefficient calculating unit configured to receive frequency information that identifies a characteristic frequency of an output signal in a filtering process, and to set filter coefficients calculated based on the frequency information in the storing circuit; and a filtering unit configured to output the output signal after applying a filtering process to an inputted signal based on the filter coefficients set in the storing circuit.

Abstract: A computer-implemented method of signal processing is provided. The method includes generating one or more masking signals based upon a computed Fourier transform of a received signal. The method further includes determining one or more intrinsic mode functions (IMFs) of the received signal by performing a masking-signal-based empirical mode decomposition (EMD) using the at least one masking signal.

Abstract: The present invention provides a filter circuit which can eliminate single noise effectively and is relatively simple in circuit configuration. First and second absolute values of differences between one-clock-preceding output data and both of one-clock-preceding input data and two-clock-preceding input data are respectively calculated by subtracters. When the first absolute value<the second absolute value, a selector selects one-clock-preceding input data as the present output data. When the first absolute value?the second absolute value, the selector selects two-clock-preceding input data as the present output data.

Abstract: In one embodiment, a statistical model is generated based on observed data, the observed data being associated with a network device, online parameter fitting is performed on parameters of the statistical model, and for each newly observed data value, a forecast value is generated based on the statistical model, the forecast value being a prediction of a next observed data value, a forecasting error is generated based on the forecast value and the newly observed data value, and whether the data of the network stream is abnormal is determined based on a log likelihood ratio test of the forecasting errors and a threshold value.

Abstract: Briefly, embodiments of methods or structures for reconstruction of uniform digital signal sample values from nonuniform digital signal sample values are disclosed

Abstract: Provided is an apparatus and method for estimating high-integration, high-speed and pipelined RLSs. Pipeline characteristics are given to an RLS algorithm to provide a high-speed HIP-RLS estimation apparatus. The HIP-RLS estimation apparatus has higher integration level than a conventional CORDIC-based RLS estimation apparatus. Thus, the use of the HIP-RLS estimation apparatus can reduce a chip size, thereby making it possible to fabricate more chips using the same wafer. Also, the HIP-RLS estimation apparatus is suitable for high-speed wireless communication because it has a high signal processing speed.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

Abstract: Disclosed is a channel estimator and a method for changing a coefficient of an IIR filter depending on a moving speed of a mobile communication terminal. In the channel estimator, a coefficient changing unit receives I and Q signals from a current base station, and selects a coefficient of the IIR filter optimized depending on the moving speed of the current mobile communication terminal. The coefficient changing unit sets the selected coefficient of the IIR filter to the IIR filter of the channel estimator. Accordingly, it is possible to prevent the performance degradation of the channel estimator caused by the speed of the mobile communication terminal.

Abstract: An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.

Abstract: A method of detecting and isolating at least one rhythmic component from a discrete-time input signal, comprises subjecting the input signal to discrete wavelet packet transform multi-resolution analysis; applying wavelet packet basis selection criteria to the result of the analysis to evaluate rhythmic signal features of the input signal; and isolating at least one rhythmic signal component from the input signal based on the evaluation.