Equalizer Patents (Class 708/323)
  • Patent number: 8443034
    Abstract: Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: May 14, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8428115
    Abstract: An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: April 23, 2013
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventors: Ziche Zhang, Guosheng Wu
  • Patent number: 8417752
    Abstract: An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: April 9, 2013
    Assignee: Altera Corporation
    Inventors: Doris Po Ching Chan, Simardeep Maangat, Thungoc M. Tran, Sergey Shumarayev
  • Patent number: 8417754
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: April 9, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Publication number: 20130077186
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Haitao Xia, Dahua Qin, Shaohua Yang
  • Patent number: 8392493
    Abstract: It is an object of the present invention to provide techniques which allow for easier change in filter characteristics of a digital filter. Then, in order to attain this object, in a weighing device according to the present invention, a filter coefficient calculator (6) calculates a filter coefficient using a predetermined mathematical expression and outputs the result to a signal processor (5). The signal processor (5) carries out a filtering process on a weight signal (DS) of a digital signal using the filter coefficient. The mathematical expression includes a first parameter which specifies an amount of attenuation in at least one attenuation band where attenuation should be locally intensified in a stopband of amplitude characteristics of the filtering process, a second parameter which specifies the band position of the at least one attenuation band, and a third parameter which specifies a starting frequency of the stopband.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: March 5, 2013
    Assignee: Ishida Co., Ltd.
    Inventors: Naoyuki Aikawa, Yukio Morishita
  • Publication number: 20130054664
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventors: Wu Chang, Victor Krachkovsky, Fan Zhang, Shaohua Yang
  • Patent number: 8380774
    Abstract: A read channel of a magnetic recording apparatus includes a filter that uses filter coefficients to process the data detected by a read head from the magnetic recordable media. The coefficients change with time and circumstances. When data is read and found to pass error detection, the filter coefficient set used for the data is stored in a memory as a last good coefficient set. Upon failure of the filtering process, the coefficient set used is replaced with a coefficient set stored in the memory as the last good coefficient set.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: February 19, 2013
    Assignee: Tandberg Storage ASA
    Inventor: Steffen Skaug
  • Patent number: 8355430
    Abstract: An embodiment of the invention pertains to demodulating a data communication into a sequence of symbols. In this embodiment, a first filter generates a first convolution between a first plurality of coefficients and the data communication. The data communication is a distortion of a first sequence of symbols selected from a plurality of symbols in a constellation. A first error circuit maps the first convolution to a second sequence of symbols. An adaption circuit adjusts the first coefficients until a convergence at a last one of the symbols in the second sequence. A second filter generates a second convolution between a second plurality of coefficients and the data communication. The second coefficients are initialized to the first coefficients from the adaption circuit. A second error circuit maps the second convolution to a third sequence of symbols.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: January 15, 2013
    Assignee: Xilinx, Inc.
    Inventor: Christopher H. Dick
  • Patent number: 8341202
    Abstract: A method for calculating coefficients of a filter and a method for filtering are provided. The invention directly factorizes a specific function in a cepstrum domain by spectral factorization and cepstrum technique to obtain coefficients of denominator function from the filter. In other words, the invention adopts a non-iterative algorithm to reduce computational complexity and avoid convergence due to calculating coefficients. Besides, the specific function of the invention includes a compensation function, so that a Fourier transform with greatly reduced size can be utilized in the spectral factorization to greatly save the computations and keep good system performance at a receiver.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: December 25, 2012
    Assignee: Sunplus mMobile Inc.
    Inventors: Wei-De Wu, Shin-Yuan Wang
  • Patent number: 8335440
    Abstract: A system, method, and apparatus is disclosed for enabling a constant modulus algorithm (CMA) to be reliably used for blind equalization training of an equalizer. According to one embodiment, received signals in a binary phase shift keying (BPSK) format are converted to a quadrature phase shift keying (QPSK) format, to which CMA processing can be reliably applied for equalization. According to another aspect of this embodiment, the equalized QPSK signals are rotated to convert the signals to an equalized BPSK format for output.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: December 18, 2012
    Assignee: Infinera Corporation
    Inventors: David J. Krause, Han Henry Sun, John D. McNicol
  • Patent number: 8320439
    Abstract: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 27, 2012
    Assignee: Agere Systems Inc.
    Inventors: Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Paul H. Tracy
  • Patent number: 8300684
    Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: October 30, 2012
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Ye Liu, Kenneth Paist, Mark Trafford
  • Patent number: 8295340
    Abstract: The present invention relates to the field of communication devices, e.g. wireless communication devices. More particularly, the present invention relates to the field of signal equalization, especially minimum mean square error equalization. The present invention especially relates to an equalizer for a communication device, a method of equalizing one or more received signals and a software program product for carrying out the method. The present invention reduces the size of a look-up table needed for a division operation and, generally, provides for a reduced complexity of the equalizer and receiver.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: October 23, 2012
    Assignee: Sony Corporation
    Inventors: Zhaocheng Wang, Richard Stirling-Gallacher
  • Patent number: 8284828
    Abstract: Instability resulting from non-linear impairments is detected and an equalizer of an end device is reset. An equalization instability threshold is retrieved from a data storage device. An equalization parameter for the end device is monitored and, if the equalization parameter exceeds the equalization instability threshold, the equalizer is reset.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: October 9, 2012
    Assignee: General Instrument Corporation
    Inventors: Michael J. Cooper, John L. Moran
  • Patent number: 8275028
    Abstract: A computer system may comprise a receiver to perform equalization. The receiver comprises an equalizer. The equalizer may determine locations of a principal tap, a platform noise tap, and a pre-cursor tap in a feedforward path of an equalizer. Also, the equalizer may determine locations of a post-cursor tap, a cross-term tap, and a portable tap in a feedback path of the equalizer. The receiver may align the portable tap in the feedback path with the principal tap in the feedforward path. The platform noise tap may cancel the effect of platform noise on a principal located at the principal tap, thus enabling the computer system to operate effectively in severe platform noise environment. Also, the computer system may operate in statics and portable environment in which platform noise and AGWN may be present.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Intel Corporation
    Inventors: Ernest Tsui, Siva Simanapalli, Lei Shao
  • Patent number: 8275026
    Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. In some embodiments, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. When the equalizer includes purely resistive impedances Z0 and Z1, the equalizer's transfer function is Z1/Z0·(?+?·(1+s·C0·Z0)), where ? is a gain parameter determined by the tail current of one differential pair and ? is a gain parameter determined by the tail current of the other differential pair.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 25, 2012
    Assignee: Silicon Image, Inc.
    Inventor: Dongyun Lee
  • Patent number: 8259854
    Abstract: The present invention relates to a receiver apparatus and method of channel estimation in a telecommunication system which provides at least two pilot sequences, and to a computer program product. Channel estimation is achieved by estimating channel taps separately for each of the at least two pilot sequences in every transmission block, and for applying estimated channel taps obtained from the estimation to at least one of a temporal and spatial filtering or combining operation to refine the channel estimate. Accordingly, temporal correlations and cross-correlations of the at least two pilot sequences are exploited without requiring knowledge of path delays and beamforming parameters.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: September 4, 2012
    Assignee: ST-Ericsson SA
    Inventors: Ahmet Bastug, Giuseppe Montalbano
  • Patent number: 8233523
    Abstract: In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer, the residual ISI detector, and the sign of the residual ISI, and has a magnitude that is dependent on the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Limited
    Inventor: Yasuo Hidaka
  • Patent number: 8223904
    Abstract: A multiple-input receiver for processing one or more communication signals is disclosed. The receiver includes a first and second demodulators, a decoder and decision logic. The first and second demodulators respectively use a first algorithm and a second algorithm and are both coupled to the receiver. The first algorithm includes interference nulling and is different from the second algorithm. A decoder can be alternatively used with the first or second demodulators to decode one or more signals from the receiver. The decoder produces a decoded signal. The decision logic chooses to use either the first demodulator or the second demodulator to affect the decoded signal.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: July 17, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Hemanth Sampath
  • Patent number: 8213494
    Abstract: In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer that produced the second output signal and the residual ISI detector that produced the first output signal, and has a magnitude that is substantially independent of the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: July 3, 2012
    Assignee: Fujitsu Limited
    Inventor: Yasuo Hidaka
  • Patent number: 8208529
    Abstract: Provided are an equalization apparatus and method of compensating a distorted received signal. The equalization apparatus includes: a filter unit removing inter-symbol interference (ISI) from a multi-channel signal that is received; and a zero-offset controller identifying a zero offset of the multi-channel signal and determining operating coefficients of the filter unit by reflecting the identified zero offset. A response filter, which reduces loss and noise, can be used, and the structure of the response filter can be simplified. In addition, channel characteristics are estimated in real time at an initial stage of data transmission and reception. Thus, an equalizer optimized for channel interference characteristics can be provided.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 26, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Choong-reol Yang, Je-soo Ko
  • Patent number: 8204103
    Abstract: Systems and techniques relating to processing information received from a spatially diverse transmission. In some implementations, an apparatus includes an input configured to receive data that has been transmitted over a wireless channel using multiple transmit antennas, nt, and multiple receive antennas, nr; and an equalizer responsive to multiple data streams corresponding to the multiple receive antennas and configured to generate an equalization matrix, Gntxnr, using a kernel matrix order updated from n(t?i)xn(r?j) to ntxnr, the kernel matrix updates being distributed across preamble processing operations. The input can be responsive to a selectable number of at least four antennas in an orthogonal frequency division multiplexed (OFDM) multiple-in-multiple-out (MIMO) system, and the equalizer can be configured to distribute the kernel matrix updates across multiple training fields of data preambles.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: June 19, 2012
    Assignee: Marvell International Ltd.
    Inventor: Konstantinos Sarrigeorgidis
  • Publication number: 20120124119
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventor: Shaohua Yang
  • Patent number: 8175201
    Abstract: Various embodiments of the present invention provide systems and methods for performing adaptive equalization. For example, various embodiments of the present invention provide methods for adaptive equalization that include providing a data processing system with an equalizer circuit (210) and a target filter circuit (265). The equalizer circuit performs equalization based at least in part on an equalizer coefficient (215). The methods further include generating an error (285) based upon a first output from the equalizer circuit and a second output from the target filter circuit. An inter-symbol interference component (295) is extracted from the error (285) and used to calculate an equalizer gradient (226). Based at least in part on the equalizer gradient (226), the equalizer coefficient (215) is calculated.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: May 8, 2012
    Assignee: LSI Corporation
    Inventors: George Mathew, Yuan Xing Lee, Hongwei Song, Liu Jingfeng, Jongseung Park
  • Publication number: 20120102082
    Abstract: Disclosed herein is a reception apparatus, including a first equalization section, a second equalization section, and an arithmetic operation section. The first equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses a single carrier. The second equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses multi carriers. The arithmetic operation section is adapted to carry out arithmetic operation for determining information to be used for the equalization by the first equalization section and arithmetic operation for determining information to be used for the equalization by the second equalization section.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 26, 2012
    Applicant: SONY CORPORATION
    Inventors: Naoki YOSHIMOCHI, Katsumi Takaoka, Hidetoshi Kawauchi
  • Publication number: 20120089657
    Abstract: Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits.
    Type: Application
    Filed: October 11, 2010
    Publication date: April 12, 2012
    Inventors: Shaohua Yang, Haitao Xia
  • Publication number: 20120084336
    Abstract: Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit is operable to store a data input as a stored input. The plurality of noise predictive filters are operable to receive a processing input. At least one of the noise predictive filters is selectably modifiable to either increase the probability of finding a sync mark in the processing input or to maintain a baseline probability of finding the sync mark in the processing input. The controller circuit is operable to determine an operational mode that may be a standard operational mode, a bit flipping mode, or a filter modification mode.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Shaohua Yang, Bruce McNeill, Weijun Tan
  • Patent number: 8144759
    Abstract: Complex adaptive methods for complex information processing employ optimal individual convergence factors for real and imaginary components of the weight vector. For wireless receivers operating on QPSK, a Complex IA-ICA performs better than existing Complex Fast-ICA methods in terms of accuracy and convergence speed, can process such complex signals in time-varying channels, and employs time-varying and time-invariant convergence factors, independent for the real and imaginary components of the system parameters, and provide individual or group system parameter adjustments. Such systems employ the within complex adaptive ICA with individual element adaptation (Complex IA-ICA).
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 27, 2012
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Wasfy B. Mikhael, Raghuram Ranganathan
  • Patent number: 8131791
    Abstract: An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel relative to the first equalizer logic. The second equalizer logic can include a low and high sign bit pipelines providing first and second conditional sign bits by assuming a low and high sign bits, respectively, for a first bits being concurrently processed by the first equalizer logic and a sign bit selection element to select between the first and second conditional sign bits based on the sign bit outcome of the first equalizer logic. The first and second pipelines compensate bits using compensation weights chosen using most recent first and second conditional sign bits and sign bit outcome.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick W. Bosshart
  • Patent number: 8126045
    Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: John Francis Bulzacchelli, Gautam Gangasani, Mounir Meghelli, Sergey V. Rylov, Michael A. Sorna, Steven J. Zier
  • Patent number: 8121232
    Abstract: A receiving system and a method of processing broadcast signal are disclosed herein. The receiving system includes a signal receiving unit, a detector, and a channel equalizer. The signal receiving unit receives a broadcast signal including mobile service data and a data group including N number of training sequences. The detector detects N number of training sequences from the broadcast signal (wherein N?5), wherein the detected N number of training sequences are received during N number of training sections.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: February 21, 2012
    Assignee: LG Electronics Inc.
    Inventors: Hyoung Gon Lee, Byoung Gill Kim, Won Gyu Song, In Hwan Choi, Jin Woo Kim
  • Patent number: 8117249
    Abstract: Systems and methods provide analog delay elements, which may be utilized in isolation or in a cascade, such as for use within equalizers or other types of applications. For example, a delay element may include a broadband amplifier and a passive, programmable filter, which may provide a desired magnitude and group delay response over a wide frequency range while being tolerant of process variations. An equalizer, for example, may include the delay element within its feed forward filter and/or within its other circuits, such as within its adaptive coefficient generator or slicer input time-align circuit.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: February 14, 2012
    Assignee: Scintera Networks, Inc.
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Qian Yu, Abhijit Phanse
  • Patent number: 8098724
    Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: January 17, 2012
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Wilson Wong
  • Patent number: 8094707
    Abstract: An apparatus, computer software, and method for data detection in channels suffering from intersymbol interference comprising receiving a signal representative of a binary digit of data, computing a reliability score for that binary digit of data via windowed Chase equalization, and based on the reliability score, causing a signal to be output that the binary digit is a zero or a one.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: January 10, 2012
    Assignee: Arrowhead Center, Inc.
    Inventors: SaiRamesh Nammi, Deva K. Borah
  • Patent number: 8085835
    Abstract: The present invention provides a system and method for performing ranging operations in a able modern system. In accordance with embodiments of the present invention, transmission times, transmission power levels, transmission carrier frequencies, and pre-equalization parameters are adjusted to provide for robust operation of the cable modem system. More particularly, iterative processing steps are used to provide coefficient ordering, scaling, and aligning between the multiple cable modems and the cable modem termination system present in a cable modern system.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: December 27, 2011
    Assignee: Broadcom Corporation
    Inventors: Jonathan S. Min, Fang Lu
  • Patent number: 8081675
    Abstract: In accordance with the teachings described herein, an extended equalizer circuit is provided for equalizing a digital communication signal transmitted over a transmission medium that causes a frequency-dependent attenuation of the digital communication signal. An equalizer may be used that includes a linear equalization circuit and a non-linear equalization circuit, the linear equalization circuit being configured to apply a linear filter to the digital communication signal to compensate for the frequency-dependent attenuation caused by a first portion of the transmission medium, and the non-linear equalization circuit being configured to apply one or more non-linear operations to the digital communication signal.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: December 20, 2011
    Assignee: Gennum Corporation
    Inventors: Mohammad Hossein Shakiba, Vasilis Papanikolaou, David L. Lynch
  • Patent number: 8077642
    Abstract: A method includes transmitting a first signal over a network from a first communication link to a second communication link. The method further includes receiving a second signal with the first communication link from the second communication link. The method further includes canceling signal echo from the first signal present in the second signal with a digital echo canceller. The method further includes providing correction data from a memory array to the digital echo canceller during the cancellation of the signal echo. An associated apparatus is also disclosed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: December 13, 2011
    Assignee: Intel Corporation
    Inventor: Ehud Shoor
  • Publication number: 20110293289
    Abstract: A system, method, and apparatus is disclosed for enabling a constant modulus algorithm (CMA) to be reliably used for blind equalization training of an equalizer. According to one embodiment, received signals in a binary phase shift keying (BPSK) format are converted to a quadrature phase shift keying (QPSK) format, to which CMA processing can be reliably applied for equalization. According to another aspect of this embodiment, the equalized QPSK signals are rotated to convert the signals to an equalized BPSK format for output.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventors: David J. Krause, Han Henry Sun, John D. McNicol
  • Patent number: 8064556
    Abstract: This disclosure describes equalization techniques for spread spectrum wireless communication. The techniques may involve estimating a channel impulse response, estimating channel variance, and selecting filter coefficients for an equalizer based on the estimated channel impulse response and the estimated channel variance. Moreover, in accordance with this disclosure, the channel variance estimation involves estimation of two or more co-variances for different received samples. Importantly, the equalizer is “fractionally spaced,” which means that the equalizer defines fractional filtering coefficients (filter taps), unlike conventional equalizers that presume that filter coefficients are defined at integer chip spacing. The techniques can allow the equalizer to account for antenna diversity, such as receive diversity, transmit diversity, or possibly both.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: November 22, 2011
    Assignee: Qualcomm Incorporated
    Inventors: Parvathanathan Subrahmanya, Inyup Kang, Jia Fei, Rajesh Sundaresan
  • Patent number: 8031765
    Abstract: A system includes a first filter that receives an input signal and comprises N taps to filter postcursor inter-symbol interference (ISI) of the input signal. S taps of the N taps have a coefficient that is limited between ?1 and 0. S and N are integer values greater than or equal to 1. N is greater than or equal to S. A decision feedback equalizer includes a decision circuit that communicates with the first filter. A second filter communicates with an input and an output of the decision circuit.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventor: Runsheng He
  • Patent number: 8018986
    Abstract: A signal receiving apparatus which can reduce a circuit scale to reduce a cost in a mobile wireless communication system which transmits and receives a spread spectrum signal is provided. The signal receiving apparatus includes a filter coefficient updating unit 104 which generates a filter coefficient w on the basis of an input signal x, a transformational despreading unit 101 which performs a despreading process to the input signal x, and an FIR filter 103 which performs multiplication by using a despreading output z output from the transformational despreading unit and the filter coefficient w output from the filter coefficient updating unit 104 as inputs to output a result which the multiplication results are added as a signal data symbol output S. The transformational despreading unit 101 obtains a despreading output by addition and subtraction between the input signal x and a spread code sequence c.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: September 13, 2011
    Assignee: NEC Corporation
    Inventor: Daiji Ishii
  • Patent number: 8014471
    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: September 6, 2011
    Assignee: Broadcom Corporation
    Inventors: Davide Tonietto, Ali Ghiasi
  • Patent number: 8001170
    Abstract: An equalizer system comprises a gain adjuster and a filter system. The gain adjuster provides a plurality of gain settings. The filter system is coupled to the gain adjuster and filters an input signal to output a filtered signal in response to the gain settings. The filter system comprises at least one high shelving filter with a first transfer function and at least one low shelving filter with a second transfer function. The reciprocal of the first transfer function is equal to the second transfer function.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: August 16, 2011
    Assignee: Mediatek Inc.
    Inventor: Kuang-Hui Hsu
  • Patent number: 7991078
    Abstract: In a signal processing apparatus adapted to process a signal transmitted via a transmission path, distortion of a waveform of a signal value of a specific symbol is predicted on the basis of a characteristic of distortion depending on values of symbols transmitted before the specific symbol, and the distortion is removed from the waveform of the received signal thereby producing a distortion-removed waveform. A comparison value is calculated for each allowable value of the specific symbol by subtracting a predicted signal value of the specific value from the distortion-removed waveform. A symbol value corresponding to the smallest comparison value is determined as the value of the specific symbol. An error suspicion level value indicating the degree of suspicion of being incorrect is calculated for each of the predetermined number of symbols, and already determined values of symbols are corrected in accordance with the error suspicion level values.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 2, 2011
    Assignee: Sony Corporation
    Inventors: Shunsuke Mochizuki, Takashi Nakanishi, Ryosuke Araki, Seiji Wada, Masahiro Yoshioka, Hiroto Kimura, Hiroshi Ichiki, Tetsujiro Kondo
  • Patent number: 7987220
    Abstract: The present invention provides an equalizer (200) and a method for computing equalizer filter coefficients in a communication receiver. The equalizer filter coefficients are computed on the basis of a real matrix T which is generated from channel estimation vector f, which is derived from the channel estimation inputs.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: July 26, 2011
    Assignee: NEC Corporation
    Inventor: David Stanhope
  • Patent number: 7978759
    Abstract: Systems and techniques relating to processing information received from a spatially diverse transmission. In some implementations, a method comprises: obtaining a received signal that was transmitted over a wireless channel using spatially diverse transmission, the received signal comprising multiple subcarriers; and recursively computing a signal-to-noise-ratio (SNR) of the received signal while receiving channel response information of the wireless channel derived from the received signal; wherein the recursively computing comprises recursively updating a diagonal kernel matrix, the method further comprising generating an equalization matrix from the recursively updated diagonal kernel matrix, the equalization matrix being useable in equalizing the received signal across the multiple subcarriers.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 12, 2011
    Assignee: Marvell International Ltd.
    Inventor: Konstantinos Sarrigeorgidis
  • Patent number: 7974336
    Abstract: An equalization system used in a communication receiver has multiple equalization stages. A front equalizer supplies equalization output to a feed back filter in a rear equalizer to speed initialization of the rear equalizer. In addition, the rear equalizer supplies decision output to the front equalizer to estimate errors so as to provide more accurate tap coefficient adjustments. Both the front equalizer and the rear equalizer can be implemented with iterative equalizers to further enhance equalization performance.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: July 5, 2011
    Assignee: Mediatek Inc.
    Inventors: Wei-Ting Wang, Ming-Luen Liou
  • Patent number: 7953163
    Abstract: A method and apparatus for channel equalization in a multi-carrier communication system. The method may include receiving a symbol having multiple sub-carriers and reducing an error on at least one of the sub-carriers of the symbol by adding to it, one or more weighted multiples of other sub-carriers. The added weighted multiples may be from neighboring sub-carriers in the same symbol and/or from other symbols in a tone, for example, a previous or next symbol. The apparatus may include a reduced-complexity block linear equalizer.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: May 31, 2011
    Assignee: Broadcom Corporation
    Inventor: Brian Wiese
  • Patent number: RE44219
    Abstract: Disclosed is an adaptive receiving MIMO (multi input and multi output) system and method which decides a symbol detecting order so as to estimate the symbol having the minimum summation of weights of least square errors at the time of estimating the symbol for respective equalizers provided in parallel by the number of transmit antennas, and updates filter tap coefficients based on the RLS algorithm according to the detecting orders. Therefore, the filter tap coefficients are directly updated without tracking channels in the time-varying channel environment, and accordingly, detection performance very similar to those of the channel tracking and conventional V-BLAST scheme is provided with reduced complexity.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: May 14, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hee-Jung Yu, Ji-Hoon Choi, Yong-Hoon Lee