Abstract: A method and apparatus for improving the performance of video encoders and decoders involves selecting a set of transforms from among a plurality of sets of transforms that can be used for coding blocks in a region of a video image. Within a region, selection of a particular transform from among a plurality of transforms comprising the selected set of transforms is used to encoder or decode at least one block in the region. Associated indices representing the set of transforms to be used within a region and the selected transform for a block can be sent in a bitstream. In an alternate embodiment, a default set of transforms is complemented by selection of an additional set of transforms on a block or region basis.

Abstract: A neural processing device and method for pruning thereof are provided. The neural processing device includes a processing unit configured to perform calculations, an L0 memory configured to store input and output data of the processing unit, wherein the input and output data include a two-dimensional weight matrix and a weight manipulator configured to receive the two-dimensional weight matrix and partition it into preset sizes to thereby generate partitioned matrices, to generate a pruning matrix by pruning the partitioned matrix, and to transmit the pruning matrix to the processing unit.

Abstract: A system and method for a logic device is disclosed. A plurality of nanotracks are disposed over a substrate, along a first axis, with at least a left nanotrack, a right nanotrack and a middle nanotrack disposed between the left nanotrack and the right nanotrack. At least one connector nanotrack is disposed to connect two adjacent nanotracks. An input value is defined at a first end of the plurality of nanotracks by selectively nucleating a skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. The nucleated skyrmion moves towards the second end of the nanotrack when a charge current is passed along the first axis. The presence of the skyrmion sensed at the second end of the middle nanotrack indicates an output value of the first value.

Abstract: The present disclosure relates to a neural network quantization parameter determination method and related products. A board card in the related products includes a memory device, an interface device, a control device, and an artificial intelligence chip, in which the artificial intelligence chip is connected with the memory device, the control device, and the interface device respectively. The memory device is configured to store data, and the interface device is configured to transmit data between the artificial intelligence chip and an external device. The control device is configured to monitor the state of the artificial intelligence chip. The board card can be used to perform an artificial intelligence computation.

Abstract: The present disclosure relates to a neural network quantization parameter determination method and related products. A board card in the related products includes a memory device, an interface device, a control device, and an artificial intelligence chip, in which the artificial intelligence chip is connected with the memory device, the control device, and the interface device respectively. The memory device is configured to store data, and the interface device is configured to transmit data between the artificial intelligence chip and an external device. The control device is configured to monitor the state of the artificial intelligence chip. The board card can be used to perform an artificial intelligence computation.

Abstract: A method of processing spectrum monitoring (SM) big data based on tensor decomposition comprises the steps of: S1: processing calibration of geolocation V, synchronized clock t, synchronized time tn(0 . . . N); of SM stations and determining SM sampling point M and bandwidth B; S2: processing discretization for a monitoring time and structured processing of SM data for a monitoring period to obtain a one-dimensional SM sequence Itn at the given sampling time and a two-dimensional SM matrix W at the given monitoring period; S3: constructing a cuboid matrix Q based on the two-dimensional SM matrix W, processing tensor decomposition for the cuboid matrix Q and identify the emitter.

Abstract: Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.

Abstract: A graph model of a graphical user interface (GUI) may be generated by processing usage data of the GUI where the usage data comprises sequences of GUI pages and actions between GUI pages. The nodes of the graph model may be determined by obtaining GUI pages from the usage data, identifying dynamic GUI elements in the GUI pages, generating canonical GUI pages by modifying the GUI pages using the dynamic GUI elements, and creating graph nodes using the canonical GUI pages. The edges of the graph may be determined by processing actions from the GUI data that were performed by users to transition from one GUI page to another GUI page. The graph model of the GUI may be used for any appropriate application, such as determining statistics relating to the GUI or statistics relating to individual users of the GUI.

Abstract: A device is further configured to determine a location within a spatial domain for a first program. The device is further configured to determine a first distance threshold value that corresponds with a first distance away from the location of the first program within the spatial domain. The device is further configured to determine distances between the location of the first program and locations of other programs from the plurality of programs and to identify one or more programs from the plurality of programs that are less than the first distance threshold value. The device is further configured to identify the one or more programs from the plurality of programs that are less than the first distance threshold value.

Abstract: A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.

Abstract: Example implementations relate to performing automated hierarchical configuration tuning for a multi-layer service. According to an example, a service definition and optimization criteria are received for tuning a configuration of a service. The service definition includes information regarding multiple of layers of the service and corresponding configuration groups. An acyclic dependency graph is created including nodes representing each of the of layers and each of the corresponding configuration groups.

Abstract: A method for scheduling jobs for the calculator includes measuring core utilization of the second-type processor, when the measured core utilization is less than a reference value, transmitting, by the first-type processor, a job suspension instruction to suspend a first job, which is currently being executed, to the second-type processor, in response to the job suspension instruction, copying data of a region occupied by the first job in a memory of the second-type processor to a main memory, copying data of a second job stored in the main memory to the memory of the second-type processor, and transmitting, by the first-type processor, an instruction to execute the second job to the second-type processor.

Abstract: A computer-implemented method for automatic multilabel classification includes receiving a label matrix Y for multiple training instances. The label matrix Y includes multiple labels, each label representing a respective category. The method further includes computing an intermediate matrix YYT, where YT is a transpose of the label matrix Y. The method further includes computing a basis matrix H by a non-negative matrix factorization of the intermediate matrix YYT. The method further includes generating a group testing matrix A by sampling the basis matrix H. The method further includes generating, for each training instance from the training instances, a reduced label vector z by computing a product of the group testing matrix A and a label vector y for respective training instance from the label matrix Y. The method further includes predicting multiple labels associated with an input based on the reduced label vector z.

Abstract: Methods and systems for storing pixels of a video/image frame are disclosed. According to one embodiment, a method for storing pixels of a video frame comprises allocating a region of a memory to a pixel block having pixels of the video frame selected in out-of-raster-scan-order. The allocated region corresponds to a plurality of contiguous locations in the memory, and wherein the allocated region includes a first portion for storing pixel values. Values of pixels are stored in the pixel block in the first portion.

Abstract: A semiconductor device including cells arranged in a matrix with m rows and n columns, where each of m and n is an integer of 2 or more, in which the cells retain first data with m rows and n columns, the cells input second data with m rows, and the semiconductor device outputs third data with m rows obtained by vector-matrix multiplication of the first data and the second data, is provided.

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

Abstract: Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using shared hardware circuits. The unified architecture exploits the symmetry properties of forward and inverse transform matrices to achieve hardware sharing across different the transform sizes and also between forward and inverse transform computations.

Abstract: A tag match determination unit determines, in response to an acquisition request for predetermined data, whether predetermined data is present in a primary cache. When the predetermined data is not present in the primary cache, the move-in buffer outputs the acquisition request for the predetermined data to a secondary cache management unit or the storage device and holds determination purpose information based on state information on a predetermined area that stores therein the predetermined data. A storage processing unit determines, when an acquired response from the secondary cache management unit or the storage device is a predetermined type, based on the determination purpose information, whether or not to acquire the state information stored in the primary cache; invalidates the predetermined area when it is determined not to acquire the state information; and stores, in the predetermined area, the predetermined data included in the response.

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors.

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors. Local storage on the streaming engine is organized as sectors based on the number of rows in the matrix to allow overlapping transposition processing and to minimize memory accesses.

Abstract: A methodology for creating and executing instruction words for simultaneous execution of instruction operations is provided. The methodology includes creating a dependency graph of nodes with instruction operations, the graph including at least a first node having a first instruction operation and a second node having a second instruction operation being directly dependent upon the outcome of the first instruction operation; first assigning the first instruction operation to a first instruction word; second assigning a second instruction operation: to the first instruction word upon satisfaction of a first at least one predetermined criteria; and to a second instruction word, that is scheduled to be executed during a later clock cycle than the first instruction word, upon satisfaction of a second at least one predetermined criteria; and executing, in parallel by the plurality of ALUs and during a common clock cycle, any instruction operations within the first instruction word.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: A video coding apparatus for encoding a compressive sensing signal has a processor. The processor obtains a compressive sensing sampling matrix; and captures the compressive sensing signal representing image data based on the compressive sensing sampling matrix, wherein the compressive sensing sampling matrix is non-uniform varied.

Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.

Abstract: A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.

Abstract: Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using shared hardware circuits. The unified architecture exploits the symmetry properties of forward and inverse transform matrices to achieve hardware sharing across the different transform sizes and also between forward and inverse transform computations.

Abstract: In one embodiment, a matrix operation may be performed, wherein the matrix operation comprises a matrix multiplication operation on a plurality of matrix operands. Matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the plurality of matrix operands. The plurality of matrix operands may be extracted from the matrix data, wherein the plurality of matrix operands comprises a first matrix operand and a second matrix operand. A first transform may be performed on the first matrix operand to obtain a transformed matrix operand, wherein performing matrix multiplication using the transformed matrix operand is faster than performing matrix multiplication using the first matrix operand. Matrix multiplication may be performed on the transformed matrix operand to obtain a partial result. A second transform may be performed on the partial result to obtain a result of the matrix multiplication operation.

Abstract: A Huffman cache is used to hold Huffman dictionaries that are changeable for dynamically selecting literal frequencies that are similar, wherein the Huffman cache is a data storage cache.

Abstract: A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.

Abstract: A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data. The transformation unit is arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.

Abstract: A GPU loads point sprites that represent coded blocks of transform coefficients of one or more frames encoded in a bitstream and loads a transform kernel as a transform kernel texture. The GPU constructs an output frame using an inverse transform on the coded blocks of transform coefficients by transforming the point sprites with the transform kernel texture and by optionally dequantizing the point sprites. A single render pass may be used in which the rasterization formula performs the inverse transform and optionally dequantization. To preserve bandwidth, a CPU may refrain from sending the GPU at least some zero valued transform coefficients for the point sprites. Also, to reduce processing, the transform coefficients can remain in a zig-zag arrangement. The transform kernel texture used in the decoding can correspond to a modified version of the basis matrices used to encode the frame, which compensates for the zig-zag arrangement.

Abstract: A storage unit includes first to third storage areas. An operation unit executes, while executing a first process to perform an FFT (Fast Fourier Transform) operation by using the first storage area, a second process to transmit a calculated FFT calculation result stored in the second storage area to other processes and to store an FFT operation result received from said other processes in the third storage area.

Abstract: A method for performing 2-dimensional discrete Fourier transform of a subject image data to be performed in one or more digital processors includes performing 1-dimensional fast Fourier transform on each row of the subject image data and 1-dimensional fast Fourier transform on each column of the subject image, and performing a simplified fast Fourier transform processing on the extracted boundary image without performing column-by-column 1-dimensional fast Fourier transform by: performing 1-dimensional fast Fourier transform only on a first column vector in the extracted boundary image data, using scaled column vectors to derive fast Fourier transform of remaining columns of the extracted boundary image data, and performing 1-dimensional fast Fourier transform on each row of the extracted boundary image data.

Abstract: A method and system may identify a video data block using a video codec and apply a transform kernel of a butterfly asymmetric discrete sine transform (ADST) to the video data block in a pipeline.

Abstract: Systems, apparatuses, and methods for performing in-place matrix transpose operations are disclosed. Operations for transposing tiles of a matrix are scheduled in an order determined by moving diagonally through tiles of the matrix. When a diagonal line hits a boundary, then a tile on a new diagonal line of the matrix is selected and operations are scheduled for transposing this tile. Only tiles within a triangular region of the matrix are scheduled for being transposed. This allows memory access operations to be performed in parallel, expediting the matrix transpose operation compared to linear tile indexing.

Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.

Abstract: A method of processing image data includes generating image data including luminance and chrominance data representing a selected object, separating the luminance and chrominance data, storing the separated luminance and chrominance data in corresponding separate spaces in memory, and separately compressing the stored luminance and chrominance data.

Abstract: Reduction of a circuit size and power consumption for performing digital filtering processing in a frequency domain is realized.

Abstract: Fourier transform computation for distributed processing environments is disclosed. Example methods disclosed herein to compute a Fourier transform of an input data sequence include performing first processing on the input data sequence using a plurality of processors, the first processing resulting in an output data sequence having more data elements than the input data sequence Such example methods also include performing second processing on the output data sequence using the plurality of processors, the output data sequence being permutated among the plurality of processors, each of the processors performing the second processing on a respective permutated portion of the output data sequence to determine a respective, ordered segment of the Fourier transform of the input data sequence.

Abstract: A battery system according to the present invention includes: a battery module comprising a plurality of cell groups connected in series, each comprising a plurality of cells connected in series; a plurality of integrated circuits provided to corresponding each cell group of the battery module, that perform detection of terminal voltages of the cells in the corresponding each cell group, and that also perform diagnosis; and a battery controller that, along with issuing commands to the plurality of integrated circuits, also receives results of detection and results of diagnosis by the plurality of integrated circuits; wherein the battery system comprises a writable non-volatile memory, and data is stored in the writable non-volatile memory specifying usage environment of the battery module, including a maximum voltage or a maximum current of the battery module and history data based upon operation history of the battery module.

Abstract: Provided are, among other things, systems, methods and techniques for identifying matching objects in a computer database. In one representative technique, a set of attribute-value pairs corresponding to a query data object are input, with individual ones of the attribute-value pairs including an identified attribute and a value for the identified attribute; multiple characteristic fingerprints are assigned to individual ones of the attribute-value pairs in the set, the characteristic fingerprints having been selected from an attribute-specific field of available characteristic fingerprints based on the value for the identified attribute; a subset of at least one characteristic fingerprint is selected from across the characteristic fingerprints for the query data object, based on a selection criterion, and a database is queried using the subset of at least one characteristic fingerprint to identify any matches.

Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described. A full transform is a transform that implements the complete mathematical description of the transform. A full transform operates on or provides full transform coefficients. A scaled transform is a transform that operates on or provides scaled transform coefficients, which are scaled versions of the full transform coefficients. The scaled transform may have lower computational complexity whereas the full transform may be simpler to use by applications. The full and scaled transforms may be for a 2D IDCT, which may be implemented in a separable manner with 1D IDCTs. The full and scaled transforms may also be for a 2D DCT, which may be implemented in a separable manner with 1D DCTs. The 1D IDCTs and 1D DCTs may be implemented in a computationally efficient manner.

Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described and comprise (1) performing a first transform on a block of first input values to obtain a block of first output values by scaling the block to obtain scaled input values, performing a scaled one-dimensional (1D) transform on each row of the block, and performing a scaled 1D transform on each column of the block; and (2) performing a second transform on a block of second input values to obtain a block of second output values by performing a scaled 1D transform on each row of the block, performing a scaled 1D transform on each column of the block, and scaling the block.

Abstract: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup comprises groupings of elements taken from a plurality of selected dimensions of the input data set for subsequent multidimensional DFT operations.

Abstract: An embodiment of the invention includes asynchronous data calculation and data exchange in a distributed system. Such an embodiment is appropriate for advanced modeling projects and the like. One embodiment includes a distribution of a matrix of data across a distributed computing system. The embodiment combines transform calculations (e.g., Fourier transforms) and data transpositions of the data across the distributed computing system. The embodiment further combines decompositions and transpositions of the data across the distributed computing system. The embodiment thereby concurrently performs data calculations (e.g., transform calculations, decompositions) and data exchange (e.g., message passage interface messaging) to promote distributed computing efficiency. Other embodiments are described herein.

Abstract: In a matrix multiplication in which each element of the resultant matrix is the dot product of a row of a first matrix and a column of a second matrix, each row and column can be broken into manageable blocks, with each block loaded in turn to compute a smaller dot product, and then the results can be added together to obtain the desired row-column dot product. The earliest results for each dot product are saved for a number of clock cycles equal to the number of portions into which each row or column is divided. The results are then added to provide an element of the resultant matrix. To avoid repeated loading and unloading of the same data, all multiplications involving a particular row-block can be performed upon loading that row-block, with the results cached until other multiplications for the resultant elements that use the cached results are complete.

Abstract: In an elliptic curve cryptographic system, point coordinates in a first coordinate system are transformed into a second coordinate system. The transformed coordinates are processed by field operations, which have been modified for operating on the transformed point coordinates. In some implementations, the point coordinates are transformed using a linear transformation matrix having coefficients. The coefficients can be fixed, variable or random. In some implementations, the transformation matrix is invertible.

Abstract: An information processing system for performing a transform of a multidimensional matrix in a distributed memory network. The method includes storing a multidimensional matrix of side N in a distributed memory network with a plurality of nodes and distributing work associated with a calculation of a transform of the matrix among N2 of the plurality of nodes. The system further includes a receiver for receiving results of the calculation of the transform of the matrix by the nodes.

Abstract: Padding or adding data to a data signal can increase the speed with which a signal processor can process the data. Methods are provided herein that can accurately predict the optimal pad size of a two dimensional array of data, which can be used to increase the processing speed of a signal processor by optimizing run-time for a two-dimensional (2-D) fast Fourier transform (FFT) operation.