Abstract: A Discreet Cosine Transform (DCT) circuit consisting of a pipe-lined Single Instruction stream, Multiple Data stream (SIMD) processor array, a transpose memory and a control circuit is provided by exploiting the row-column decomposition method, wherein the processor array is capable of computing one dimensional DCT. In an N-point DCT application, the processor array consists of N PEs (processor elements), each of which can compute a N/2-point inner product. Instead of a conventional Multiplexed Analogue Components (MAC) design, the present DCT circuit computes the N/2-point inner product by a word-parallel bit-serial method, which uses N/2 Read Only Memory (ROM) tables, a Wallace tree and one carry propagate adder. This implementation achieves cost-saving and better timing in comparison to a MAC design. Meanwhile, the circuit also has the advantages of simple data routing, regular structure and modular design, and is suitable for Very Large Scale Integration (VLSI) implementation.

Abstract: A matrix transposition device with which speed of processing such as a two-dimensional orthogonal transformation can be raised, wherein there is provided of a plurality of storage devices 22-0 to 22-p arranged so as to be able to input input column vectors in parallel and output output column vectors in parallel, the sum of the address ranges being enough to store all element data of the input matrix; a plurality of input selection devices 21-0 to 21-p capable of selecting one numerical value input from among a plurality of parallel numerical value inputs and inputting selected numerical value to corresponding storage devices; a plurality of address generators 23-0 to 23-p capable of designating independent addresses with respect to the storage devices; output selection devices 24-0 to 24-n capable of respectively independently selecting outputs of any storage devices; and a control device 25 which performs a control so that elements of any input row vectors are stored in different storage devices at the time

Abstract: The invention provides a high speed two-dimensional discrete cosine transform circuit which can reduce the number of addition operations for rounding to one time. The two-dimensional IDCT circuit calculates M.times.N-point two-dimensional inverse discrete cosine transforms wherein M.times.N is equal to 2.sup.2n, and includes an M.times.N two-dimensional IDCT operator for calculating two-dimensional inverse discrete cosine transforms as matrix vector products of a transform matrix of MN rows and MN columns and MNth-order input vectors, a shift operator for shifting results of the calculation of the M.times.N two-dimensional IDCT operator rightwardly, and an adder for adding 2.sup.n-2 to a discrete cosine coefficient from among discrete cosine transform coefficients to be inputted to the M.times.N two-dimensional IDCT operator. An output signal of the shift operator is outputted as a circuit output signal of the two-dimensional IDCT circuit.