Abstract: A method and system to quickly analyze and predict battery failure and short-circuit comprises a battery cell unit carried with a sensor unit continuing detect a value of a condition of the battery cell unit to obtain a time domain result. The system will further convert the time domain result into a frequency domain result and will send an alarm or warning if such frequency domain result has exceeded a pre-set threshold. The present invention could accurately send the reminder or warning of the upcoming short-circuit at earlier stage of the battery cell unit by simply analyzing the time domain result converting as the frequency domain result. The system provided by the present invention has the ability to detect micro-circuit of the battery cell unit to facilitate detecting battery failure and short-circuit to avoid any emergency happened to the battery while using.

Abstract: A method for processing data based on 3072-point Fast Fourier Transform (FFT) and a processor based on 3072-point FFT are provided. The method for processing data based on 3072-point FFT includes: storing 3072-point data into a data storage module according to a predetermined mapping relationship (101); reading 16 data in parallel from the data storage module for performing 3-point DFT operation, and storing results into the data storage module in situ after completion of the operation (102); and reading 32 data in parallel from the data storage module for performing 1024-point DFT operation and storing results into the data storage module in situ after completion of the operation until the FFT of 3072-point data is completed (103).

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: Present disclosure describes an improved scaling mechanism for a multi-stage fixed-point FFT algorithm used to process signals received by radar or sonar systems. Proposed scaling includes scaling an output of every pair of consecutive butterfly stages of the FFT algorithm by a scaling factor equal to two times of the inverse of a growth factor for the pair of consecutive butterfly stages for the FFT algorithm for a purely complex exponential input signal. Besides this scaling, input signals are allowed to overflow by saturation. Such mechanism yields adequate performance of radar and sonar receivers implementing fixed-point FFTs for any types of input signals, from random to substantially complex exponential or sinusoidal signals. Proposed scaling achieves a balance between having signal to noise ratio (SNR) that is possible to obtain for a particular input signal and SNR that is needed to successfully process that signal for radar and sonar applications.

Abstract: A folded butterfly module performs a radix-22 butterfly operation, and includes: a buffer operable to store first and second to-be-stored data and output first and second stored data; a first multiplexer operable to output one of the second stored data and input data as first selection data; a butterfly operator performing a radix-2 butterfly operation on the first stored data and the first selection data to generate operation data and the second to-be-stored data; a second multiplexer operable to output one of the input data and the operation data as the first to-be-stored data; a third multiplexer operable to output one of the operation data and the second stored data as second selection data; and a multiplier generating output data that equal a product of the second selection data and twiddle data.

Abstract: Fast Fourier Transform (FFT) operates by decomposing a longer length input signal into many smaller length signals. The decomposition may be carried out in different number of smaller length signals at each stage. The number of smaller length signals at each stage is referred to as a radix. FFT may be implemented either with decimation in time or with decimation in frequency method. Depending on the method used, reordering of the input or the output data sequence may be required in order to get the data sequence in the correct order. Mixed radix FFT is an FFT structure that uses a combination of radixes. The reordering for mixed radix FFT by bit reversing or digit reversing the index has non-trivial complexity. A method and apparatus are disclosed that enable efficient and zero latency reordering of a data sequence for an FFT structure that uses a combination of two or more radixes.

Abstract: 2D nearest-neighbor quantum architectures for Shor's factoring algorithm may be accomplished using the form of three arithmetic building blocks: modular addition using Gossett's carry-save addition, modular multiplication using Montgomery's method, and non-modular multiplication using an original method. These arithmetic building blocks may assume that ancillae are cheap, that concurrent control may be available and scalable, and that execution time may be the bottleneck. Thus, the arithmetic building blocks may be optimized in favor of circuit width to provide improved depth existing nearest-neighbor implementations.

Abstract: A data processing method is disclosed, including: twiddling input data, so as to obtain twiddled data; pre-rotating the twiddled data by using a symmetric rotate factor, where the rotate factor is a·W4L2p+1, p=0, . . . , L/2?1, and a is a constant; performing a Fast Fourier (Fast Fourier Transform, FFT) transform of L/2 point on the pre-rotated data, where L is the length of the input data; post-rotating the data that has undergone the FFT transform by using a symmetric rotate factor, where the rotate factor is b·W4L2q+1, q=0, . . . , L/2?1, and b is a constant; and obtaining output data.

Abstract: Generally, this disclosure describes a method and apparatus for reduced memory footprint fast Fourier transforms (FFTs). An apparatus may include intermediate factor circuitry configured to generate an intermediate factors vector including a number of intermediate factors in response to a request to generate an FFT of an N-point input data set, N composite, wherein N is equal to a product of a number of nonunity integer factors, the number of intermediate factors is related to the nonunity integer factors of N and the number of intermediate factors is less than N. The apparatus may include intermediate result circuitry configured to reconstruct a subset of twiddle factors based at least in part on an element by element product of a first subset of the intermediate factors vector and a complex conjugate of a second subset of the intermediate factors vector, wherein the twiddle factors are complex roots of unity.

Abstract: A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.

Abstract: An adaptive equalizer (100) has a signal converter (200) for performing a fast Fourier transform and/or an inverse fast Fourier transform. The signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable of accessing the first wide-bit memory (201); a butterfly computation unit group (204) comprising a plurality of butterfly computation units; and a first connection switching unit (203) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.

Abstract: Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector to yield a rotated vector and to store rotation directions of the series of successive rotations, and at least one lookup table operable to yield an angle of rotation based on the rotation directions.

Abstract: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A pipelined FFT circuit used for processing a sequential input data with a set of N samples comprises a data division unit, a data-preprocessing unit and M sets of data computation unit. The data division unit is used for dividing the sequential input data into a first input data stream and a second input data stream. The data-preprocessing unit receives the first and second input data streams and orders the first input data stream to an odd number-index data stream, the second input data stream to an even number-index data stream respectively. Each of the data computation units has a data switch and a butterfly computator connected with the data switch, where M=log2N, the data switch of the first data computation unit is connected with the data-preprocessing unit.

Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.

Abstract: An apparatus and method for signal detection in which a digital sample stream is fed round robin into a plurality of buffers, which are sequentially compared with a reference signal to determine a match. A processor determines the chronological order of the samples in each bit of each buffer, and directs a bitwise comparison between the signal in each buffer with the reference to determine a match, e.g., by correlation. The apparatus and method are preferably implemented with a Field-Programmable Gate Array (FPGA). This scheme permits real time correlation of a data stream with a reference without use of shift registers, or a significant number of dedicated logic blocks.

Abstract: A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.

Abstract: A fast Fourier transform (FFT) architecture operable to transform data of variable point size includes a plurality of input ports, a plurality of memory elements, a crosspoint switch, a plurality of processing elements, and a plurality of output ports. The inputs ports read time-domain data from an external source. The memory elements store input data, intermediate calculation results, and output data. The crosspoint switch allows data to flow from any one architecture component to any other architecture component. The processing elements perform the FFT calculation. The output ports write frequency-domain data to an external source.

Abstract: The invention relates to techniques for implementing high-speed precoders, such as Tomlinson-Harashima (TH) precoders. In one aspect of the invention, look-ahead techniques are utilized to pipeline a TH precoder, resulting in a high-speed TH precoder. These techniques may be applied to pipeline various types of TH precoders, such as Finite Impulse Response (FIR) precoders and Infinite Impulse Response (IIR) precoders. In another aspect of the invention, parallel processing multiple non-pipelined TH precoders results in a high-speed parallel TH precoder design. Utilization of high-speed TH precoders may enable network providers to for example, operate 10 Gigabit Ethernet with copper cable rather than fiber optic cable.

Abstract: A memory-based Fast Fourier Transform device is provided, which adopts single-port random access memory (RAM), rather than dual-port RAM, as a storage, and the circuit area of the FFT device is therefore reduced. In order to enhance the access efficiency of the memory and the use efficiency of a processor, the transformer adopts a modified in-place conflict-free addressing to achieve similar performance of a traditional Fast Fourier Transform device.

Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.

Abstract: A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed.

Abstract: A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Abstract: In a method for performing a fast-Fourier transform (FFT), input data samples are written to a storage instance in a data input step, then subjected to a processing step in which the stored input samples are read out of the storage instance and processed in accordance with a transformation algorithm. The resulting output data samples are written back to the storage instance and, in a transformed data output step, read out of the storage instance, successively received batches of the input data samples being fed cyclically to a plurality of such multiple-function storage instances. Each batch is fed to a respective storage instance such that, at any given time during performance of the method, the input, processing and output steps are being performed simultaneously in respect of different batches using different respective storage instances.

Abstract: A real-valued FFT processor implements Bergland's real-valued FFT and uses unique interstage switching/delay modules to reduce pipeline latency. Modified hybrid floating point arithmetic is also employed to provide maximum SNR. The real-valued FFT processor is particularly suited for a DMT engine and, in a multichannel CO ADSL application, the DMT engine can be multiplexed between the channels to provide an economic, low cost CO solution.

Abstract: The discrete Fourier transform (DFT) is computed in a plurality of parallel processors. A DFT of length N is divided into r partial DFTs of length (N/r), in which the r partial DFTs are calculated in separate parallel processors and then combined in a combination phase to form a complete DFT of length (N). The r partial FFTs are able to be computed in parallel multiprocessors by defining the mathematical model of the combination phase in such manner so as to allow the r parallel processors to operate independently and simultaneously. A second embodiment presents a radix-r fast Fourier algorithm that reduces the computational effort as measured by the number of multiplications and permits the N/r parallel processors to operate simultaneously and with a single instruction sequence.

Abstract: A general purpose network tone detection method and apparatus that allows the precise and accurate recognition of North American tones (MF, DTMF (Dual-Tone Multifrequency), and CPT (Call Progress Tones)) and international MF-R2 tones as well as taking into consideration other common tones such as Calling Card Service Prompt and Recall Dial. Through the use of the Discrete Fourier Transform (DFT) on small time windows and by providing phase continuity between these windows, the results of the successive DFTs may be combined and processed by a second DFT computation. This second DFT allows higher frequency resolution without requiring the re-computation of the DFT from the time samples. The resulting effect is a tone receiver with both high time and frequency resolution which consequently leads to robust and accurate tone recognition systems conforming even to the most stringent specification while maintaining low computational requirements.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A pipelined, real-time N-point transform processor contains a first butterfly triplet multiplicatively connected to an output portion by way of a complex multiplier. The butterfly triplet contains a first butterfly I unit (BFI), a butterfly II unit (BFII) and a butterfly III unit (BFIII), which are connected together in series. An input port of the first BFI serves as an input port of the triplet to accept complex numbers, and an output port of the BFIII serves as an output port of the triplet. The complex multiplier accepts a complex result from the output port of the first triplet, and a coefficient provided by a control unit to generate a complex product. The output portion contains at least a second BFI, an input port of the second BFI accepting the complex product from the complex multiplier, and the output portion provides the transformed complex numbers. The control unit contains a pipeline step-count register, and the ability to provide the coefficients to the complex multiplier.

Abstract: The post-processing of the transformation processing of an interleaved type is temporally nested with regards to two successive symbols, and includes storage in two separately addressable memories of identical size. The addressing of the two memories is performed successively and alternately in the natural and reverse order at the frequency with the symbol clock signal.

Abstract: A method and computer-readable medium is provided for designing control software for a module in a self-reconfigurable robot. A genetic method randomly selects a plurality of module software functions for creating a plurality of module control software programs. The plurality of control software programs are then evaluated against a series of tasks and respective fitness functions. The module control software is selected based on the software program having the highest fitness function value for a particular task.

Abstract: An electronic device for computing a Fourier transform having a pipeline architecture includes at least one processing stage with a radix equal to 4. Each processing stage includes elementary processing for performing process operations for Fourier transforms of size equal to 4 on data blocks. Each processing stage also includes an elementary storage that includes a random access memory. In particular, the random access memory is a single-access memory with a storage capacity equal to 3N/4 data bits. The size of the data block processed by this stage is equal to N.

Abstract: A pipelined FFT (fast Fourier transform) processor including a CBFP (convergent block floating point) algorithm, includes an inverse multiplexer for inverse-multiplexing an 8K-/2K-point input data, a first to sixth radix-4 operation circuit for receiving an output of the inverse multiplexer and performing a butterfly operation, a multiplexer connected between the first and second radix-4 operation circuits and for selectively outputting an output of the inverse multiplexer or a first butterfly unit, a radix-2 operation circuit connected to the sixth radix-4 operation circuits and for performing a butterfly operation, a convergent block floating point circuit connected to respective output terminals of the radix-4 operation circuit and the radix-2 operation circuit and for scaling a butterfly operation result, an addition circuit for accumulation and adding scaling indexes outputted from the convergent block floating point circuit, and a decoder for scaling an output of the radix-2 operation circuit in accorda

Abstract: A pipelined Fast Fourier Transform Processor includes, besides a memory arrangement, a cascade of a first arithmetic unit, a scratch memory and a second arithmetic unit. One of both arithmetic units can only perform at least one type of butterfly Fast Fourier Transform arithmetic calculations, whereas the other one can perform, besides this at least one type of butterfly Fast Fourier Transform arithmetic calculations, at least one second type of butterfly Fast Fourier Transform arithmetic calculations. This architecture optimises both timing as well as circuit restrictions.

Abstract: For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the stored data and of the other data of the block. Only half of the data bits received are stored in an auxiliary storage. All the data bits of the input block are reconstructed from the contents of the main and auxiliary storage to obtain a reconstructed data block, which is temporally delayed with respect to the input block.

Abstract: A high-speed discrete Fourier transform (DFT) apparatus utilizes a processor operating in parallel with data acquisition to calculate terms of a Fourier transform corresponding to the incoming data. Since the processor calculates the Fourier terms in real-time, overall transformation time is substantially reduced and is limited by only the data acquisition time. In another aspect, substantial reduction of the number of computations are achieved by transforming the plurality of terms in Fourier equations at the same time. In a further aspect, the high-speed DFT is advantageously applied to a network analyzer which obtains a transfer function of a device in a frequency domain and converts the transfer function to a time domain response to a simulated test signal.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-2.sup.2 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-2.sup.2 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.

Abstract: The Fast Fourier Transform (FFT) processor includes a plurality of pipelined, functionally identical stages, each stage adapted to perform a portion of an FFT operation on a block of data. The output of the last stage of the processor is the high-precision Fast Fourier Transform of the data block. Support functions are included at each stage. Thus, each stage includes a computational element and a buffer memory interface. Each stage also includes apparatus for coefficient generation.

Abstract: A method and apparatus for calculating fast Fourier transforms FFTs. An FFT of a given size is formatted using tensor product principles for implementation in apparatus or by software such that the same reconfigurable hardware or software can calculate FFTs of any dimension for the selected FFT size. The FFT is factored into an input permutation and successive stages for computing tensor products of dimensionless Fourier transforms of a relatively small base size and twiddle factors, with load-stride permutations between computation stages. The basic building blocks of the circuitry can be reconfigurable for maximizing use-flexibility of the hardware or software. Examples of digital circuit apparatus configured to compute dimensionless formatted FFTs are presented.

Abstract: Improved assistance is provided to an operator to balance an out-of-proof transaction at a balancing workstation of an image-based financial document processing system used to process transaction items including debit and credit items. A number of suspect tests are invoked. The suspect tests have been previously arranged in an order which is based upon at least one characteristic data collected over a previous time period. The invoked suspect tests are applied to the debit items and the credit items in the particular order to improve assistance to the operator to balance the out-of-proof transaction.