Fourier Patents (Class 708/403)
  • Patent number: 11941371
    Abstract: Systems, apparatuses, and methods related to bit string accumulation are described. A method for bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and modifying a quantity of bits of a result of the iteration of the recursive operation, wherein the modified quantity of bits is less than a threshold quantity of bits. The method can further include writing a first value comprising the modified bits indicative of the result of the iteration of the recursive operation to a first register and writing a second value indicative of the factor corresponding to the result of the iteration of the recursive operation to a second register.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Katie Blomster Park
  • Patent number: 11921848
    Abstract: The disclosed embodiments relate to a system that characterizes susceptibility of an inferential model to follow signal degradation. During operation, the system receives a set of time-series signals associated with sensors in a monitored system during normal fault-free operation. Next, the system trains the inferential model using the set of time-series signals. The system then characterizes susceptibility of the inferential model to follow signal degradation. During this process, the system adds degradation to a signal in the set of time-series signals to produce a degraded signal. Next, the system uses the inferential model to perform prognostic-surveillance operations on the set of time-series signals with the degraded signal. Finally, the system characterizes susceptibility of the inferential model to follow degradation in the signal based on results of the prognostic-surveillance operations.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: March 5, 2024
    Assignee: Oracle International Corporation
    Inventors: Zexi Chen, Kenny C. Gross, Ashin George, Guang C. Wang
  • Patent number: 11681775
    Abstract: Methods, systems and apparatus for simulating quantum systems. In one aspect, a method includes the actions of obtaining a first Hamiltonian describing the quantum system, wherein the Hamiltonian is written in a plane wave basis comprising N plane wave basis vectors; applying a discrete Fourier transform to the first Hamiltonian to generate a second Hamiltonian written in a plane wave dual basis, wherein the second Hamiltonian comprises a number of terms that scales at most quadratically with N; and simulating the quantum system using the second Hamiltonian.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 20, 2023
    Assignee: Google LLC
    Inventor: Ryan Babbush
  • Patent number: 11640549
    Abstract: Methods for preparing a Gibbs state in a qubit register of a quantum computer include applying one or more quantum gates to one or more qubits of the qubit register to prepare a trial quantum state spanning the one or more qubits, the trial quantum state being defined as a function of parameters {right arrow over (?)} and being selected to provide an initial estimate of the Gibbs state. The methods further include evaluating the Gibbs free energy of the trial quantum state, adjusting the parameters {right arrow over (?)}, re-applying the one or more quantum gates to the one or more qubits to refine the trial quantum state according to the parameters {right arrow over (?)} as adjusted, and re-evaluating the Gibbs free energy of the trial quantum state.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 2, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Guang Hao Low, Nathan O. Wiebe, Anirban Ch Narayan Chowdhury
  • Patent number: 11636374
    Abstract: The disclosure is in the technical field of circuit-model quantum computation. Generally, it concerns methods to use quantum computers to perform computations on classical spin models, where the classical spin models involve a number of spins that is exponential in the number of qubits that comprise the quantum computer. Examples of such computations include optimization and calculation of thermal properties, but extend to a wide variety of calculations that can be performed using the configuration of a spin model with an exponential number of spins. Spin models encompass optimization problems, physics simulations, and neural networks (there is a correspondence between a single spin and a single neuron). This disclosure has applications in these three areas as well as any other area in which a spin model can be used.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 25, 2023
    Assignee: QC Ware Corp.
    Inventors: Peter L. McMahon, Robert Michael Parrish
  • Patent number: 11563618
    Abstract: Methods, apparatuses, systems, devices, and computer program products directed to unique word (UW) discrete Fourier transform (DFT) spread and shaped orthogonal frequency division multiplexing (OFDM) (“UW DFT-S-S-OFDM”) based communications are provided. Among new methodologies and/or technologies provided is a method implemented in transmitter and includes any of: transforming a set of data symbols and a UW sequence into a frequency domain (“fDOM”) signal using a DFT; replicating the fDOM signal so as to form a plurality of fDOM signal instances, wherein the plurality of fDOM signal instances is inclusive of the fDOM signal; shaping one or more of the plurality of fDOM signal instances; combining the plurality of fDOM signal instances to form a combined fDOM signal; transforming the combined fDOM signal into a block-based signal using an inverse DFT (IDFT); and outputting the block-based signal.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 24, 2023
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Alphan Sahin, Erdem Bala, Rui Yang, Mihaela C. Beluri, Robert L. Olesen
  • Patent number: 11539566
    Abstract: Methods, systems, and devices for wireless communications are described. Generally, a user equipment (UE) may identify an angle parameter for encoding uplink messages using a fractional Fourier Transform (FrFFT). A base station may transmit a set of angle parameters or a single angle parameter that the UE is to use for encoding an uplink message. The UE may select an alpha value from the set of alpha values for the encoding. The UE may transmit an indication of a set of proposed angle parameters to the base station, and the base station may determine and indicate one of or a subset of the received set of proposed angle parameters to the UE. The base station may indicate a correspondence between angle parameters and beam configurations, and the UE may identify an alpha parameter value based on a subsequently indicated beam configuration.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 27, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Ahmed Elshafie, Yi Huang, Hwan Joon Kwon
  • Patent number: 11526794
    Abstract: Described herein are methods and systems for controlling an integrated optics control system for quantum computing using a quantum bios chip. A quantum bios chip, comprising one or more qubit connection geometries and one or more error correction codes associated with the qubit connection geometries, receives instructions associated with a quantum computing application. The quantum bios chip configures one or more switching elements of an integrated optics control system coupled to the quantum bios chip, the switching elements controlling entanglement of one or more qubits of a quantum computer and the switching elements configured based upon a selected one of the one or more qubit connection geometries and one of the one or more error correction codes that is compatible with the selected one of the one or more qubit connection geometries.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 13, 2022
    Assignee: Second Foundation
    Inventor: Michele Reilly
  • Patent number: 11121868
    Abstract: Fisher's exact test is efficiently computed through secure computation. A computation range determination part determines i0, i1, x0, x1. A preliminary computation part computes f(x0), . . . , f(x1), and generates an array M=(f(x0), . . . , f(x1)). A securing part secures the array M, and generates a secure text array <M>=(<f(x0)>, . . . , <f(x1)>). A batch-reading part generates a function value secure text (<f(ai)>, <f(bi)>, <f(ci)>, <f(di)>) (i0?i?i1).
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 14, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventor: Koki Hamada
  • Patent number: 11036830
    Abstract: A method for solving a computational problem reducible to a problem of summing probabilities over all solutions to a decision problem includes using a quantum computer to identify a coarse estimate of a sum of the probabilities over all solutions to the decision problem. The method also includes using the quantum computer to identify a finer estimate of the sum. The finer estimate is determined using a quantum amplitude estimation algorithm in which a number m in a number register controls a number R×m of quantum amplitude amplification iterations to be applied to a solution space register (where R is a specified multiple) and a quantum Fourier transform is applied to the number register. The method further includes using the coarse estimate to de-alias the finer estimate over all solutions. In addition, the method includes outputting a solution to the computational problem determined using the de-aliased finer estimate.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Goldman Sachs & Co. LLC
    Inventor: Paul Burchard
  • Patent number: 10853722
    Abstract: Aspects of processing data for Long Short-Term Memory (LSTM) neural networks are described herein. The aspects may include one or more data buffer units configured to store previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values. The aspects may further include multiple data processing units configured to parallelly calculate a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 1, 2020
    Assignee: Sanghai Cambricon Information Technology Co., Ltd.
    Inventors: Yunji Chen, Xiaobing Chen, Shaoli Liu, Tianshi Chen
  • Patent number: 10826845
    Abstract: The present disclosure provides methods, systems, and media for quantum computing, including allowing access to quantum ready and/or quantum enabled computers in a distributed computing environment (e.g., the cloud). Such methods and systems may provide optimization and computational services. Methods and systems of the present disclosure may enable quantum computing to be relatively and readily scaled across various types of quantum computers and users at various locations, in some cases without the need for users to have a deep understanding of the resources, implementation or the knowledge that may be required for solving optimization problems using a quantum computer. Systems provided herein may include user interfaces that enable users to perform data analysis in a distributed computing environment while taking advantage of quantum technology in the backend.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: November 3, 2020
    Assignee: 1QB INFORMATION TECHNOLOGIES INC.
    Inventors: Majid Dadashikelayeh, Arman Zaribafiyan, Sahar Karimi, Pooya Ronagh
  • Patent number: 10686635
    Abstract: A method for communicating using polynomial-based signals. In such a method, a set of basis polynomial functions used to generate waveforms may be identified, wherein each of the basis polynomial functions in the set of basis polynomial functions is orthogonal to each of the other basis polynomial functions in the set of basis polynomial functions in a coordinate space. The set of basis polynomial functions may be combined into a message polynomial. The message polynomial may be convolved with a reference polynomial to produce a transmission polynomial. From the transmission polynomial, a sequence of amplitude values may be generated. Finally, a signal may be transmitted based on the sequence of amplitude values, which may be further modified based on, for example, instantaneous spectral analysis. In some embodiments, orthogonal polynomials may include Chebyshev or Cairns polynomials.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Astrapi Corporation
    Inventor: Jerrold Prothero
  • Patent number: 10387118
    Abstract: An arithmetic operation unit includes: a first multiplier configured to multiply two first input data to calculate first arithmetic data; a second multiplier configured to multiply two second input data to calculate second arithmetic data; a first adder configured to add the first arithmetic data and the second arithmetic data to calculate third arithmetic data; a first arithmetic selector configured to select one of the first arithmetic data and the third arithmetic data; a second arithmetic selector configured to select one of the second arithmetic data and the third arithmetic data; a second adder configured to add third input data and arithmetic data selected by the first arithmetic selector to calculate first arithmetic result data; and a third adder configured to add input fourth data and arithmetic data selected by the second arithmetic selector to calculate second arithmetic result data.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: August 20, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masaki Ukai
  • Patent number: 10135599
    Abstract: Frequency domain compression of fronthaul interface for transporting frequency domain data over Ethernet includes applying Inverse Discrete Fourier Transform to frequency domain data contained in a frequency bandwidth to generate a time domain output signal in a time domain. The time domain output signal is compressed to generate a compressed time domain output signal. The compressed time domain output signal is transmitted over a fronthaul interface to a remote unit. The compressed time domain output signal is decompressable at the remote unit to generate a decompressed time domain output signal. Discreet Fourier Transform is applied to the decompressed time domain output signal at the remote unit to recover the frequency domain data.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 20, 2018
    Assignee: Nokia Technologies Oy
    Inventors: Gunter Wolff, Roy Yang
  • Patent number: 9880975
    Abstract: Provided is a digital filter device that causes the last data of an immediately precedent input block to overlap with the input block of a time domain and generates an overlap block. The overlap block and the immediately precedent input block are each converted into a frequency domain block, subjected to filter processing, and converted into first and second time domain blocks. Among the overlap section of the first time domain block and the second time domain block, the front-end data of the first time domain block and the rear-end data of the temporal axis of the second time domain block are removed as a section of data that is to be removed, and output data is generated. An overlap amount is controlled on the basis of a distortion amount that is determined by comparing the removed section of the data of the first time region domain with the output section of the data of the overlap section of the second time domain block other than the removed section of said overlap section.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: January 30, 2018
    Assignee: NEC CORPORATION
    Inventor: Atsufumi Shibayama
  • Patent number: 9875084
    Abstract: A circuit is disclosed that uses a four element dot product circuit (DP4) to approximate an argument t=x/pi for an input x. The argument is then input to a trigonometric function such as Sin Pi( ) or Cos Pi( ). The DP4 circuit calculates x times a representation of the reciprocal of pi. The bits of the reciprocal of pi that are used are selected based on the magnitude of the exponent of x. The DP4 circuit includes four multipliers, two intermediate adders, and a final adder. The outputs of the multipliers, intermediate adders, and final adder are adjusted such that the output of the final adder is a value of the argument t that will provide an accurate output when input to the trigonometric function.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 23, 2018
    Assignee: Vivante Corporation
    Inventors: Lefan Zhong, Guosong Li, Zhenyu Wang, Rui Zhao
  • Patent number: 9820074
    Abstract: A processor can be associated with a memory for storing convolution data. A plurality of M filters from a corresponding plurality of M input channels to a selected one output channel can be provided, wherein each filter can be represented by a corresponding index, m. Each of the M filters can be partitioned into K respective filter partitions, wherein each respective filter partition can be represented by a corresponding index, k. A frequency-domain representation of each filter partition can be provided, wherein each frequency-domain representation of a filter partition comprises N frequency bins and a corresponding frequency-domain filter coefficient, wherein each respective frequency bin can be represented by a corresponding index, n. The memory can store such information in an arrangement suitable for the processor to concurrently receive sufficient information to concurrently convolve a frame of each input signal with the respective filters.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 14, 2017
    Assignee: Apple Inc.
    Inventors: Joshua Atkins, Adam Strauss
  • Patent number: 9806789
    Abstract: An apparatus and method for full-duplex millimeter wave mobile wireless communication are provided. The apparatus includes a Spatial Division Duple (SDD) mobile communication system using millimeter waves, the SDD mobile communication system including a first wireless terminal having a first transmit antenna array having a plurality of first transmit antennas for transmitting a spatially beamformed first transmit beam, and a first receive antenna array having a plurality of first receive antennas for forming a spatially beamformed first receive beam and a second wireless terminal including a second transmit antenna array having a plurality of second transmit antennas for transmitting a spatially beamformed second transmit beam directed towards a receive beam of the first wireless terminal, and a second receive antenna array having a plurality of second receive antennas for forming a spatially beamformed second receive beam directed toward the transmit beam of the first terminal.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Farooq Khan, Zhouyue Pi
  • Patent number: 9310307
    Abstract: High-speed data processing is achieved by measuring spectral data using a multivariate analysis. This is accomplished by a determining sampling intervals or sampling data to be used in the multivariate analysis, obtaining a spectral data group of the determined sampling intervals, and carrying out the multivariate analysis using the obtained spectral data group.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: April 12, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Tanji
  • Patent number: 9229909
    Abstract: A method for designing a discrete Fourier transform (DFT) unit in a system on a target device includes identifying a number of DFT engines to implement in the DFT unit in response to a data throughput rate, a clock rate of the system, a size of a DFT, and radix of each of the DFT engines.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 5, 2016
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Patent number: 8984038
    Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Broadcom Corporation
    Inventors: Kuoruey (Ray) Han, Peiqing Wang, Linghsiao Wang, Kishore Kota, Arash Farhoodfar
  • Patent number: 8917588
    Abstract: An FFT/IFFT operating core capable of minimizing a required memory depth during operation is disclosed. The FFT/IFFT operating core includes an inputting buffer, a first multiplexer, an operating module, and a controlling module. The inputting buffer stores and outputs a first FFT input sequence. The first multiplexer is utilized to multiplex the first FFT input sequence and a third input sequence. The controlling module generates a process indicating signal and a bypass indicating signal. The operating module has a plurality of operating stages in series. The operating module transforms the first and third FFT input sequences into a first and third FFT output sequences, respectively, and it transforms a second IFFT input sequence into a second IFFT output sequence.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: December 23, 2014
    Assignees: Silicon Motion, Inc., FCI Inc.
    Inventor: Chang-ik Hwang
  • Patent number: 8909686
    Abstract: A discrete Fourier calculation device includes a twiddle factor table storage unit that stores therein a twiddle factor table that associates twiddle factors with phases of the corresponding twiddle factors; a correction value specifying unit that specifies first and second correction values for correcting a phase of an input signal in accordance with an amplitude of the input signal; a generating unit that corrects the phase of the input signal by using the specified first and second correction values to generate first and second phases; an addition unit that adds an arbitrary phase corresponding to an arbitrary twiddle factor stored in the twiddle factor table, to each of the generated first and second phases; and a rotation calculation unit that acquires, from the twiddle factor table, first and second twiddle factors corresponding to the first and second phases and sums the acquired first and second twiddle factors.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Limited
    Inventor: Jun Kameya
  • Patent number: 8898212
    Abstract: A data reordering system for determining addresses associated with a vector of transformed data and corresponding method of reordering transformed data, where the data reordering system includes: a first transform function coupled to a data vector and operable to provide the vector of transformed data; a reordering function, including a plurality of counters, that is operable to determine a plurality of offset addresses, with a, respective, offset address for each element in the vector of transformed data; and an adder operable to add a base address that corresponds to the first address to the each, respective, offset address to provide a sequence of addresses suitable for accessing the vector of transformed data to provide a re-sequenced vector of transformed data.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc
    Inventors: Ning Chen, Christopher J. Daniels, Leo G. Dehner, Gregory C. Ng, Wendy F. Reed
  • Publication number: 20140330879
    Abstract: A signal is decomposed into different components using a transform, with the components then being separately presented to a person in a manner that produces a different cognitive experience than would have resulted from either (a) presentation of the original signal, or (b) presentation of a fully synthesized (inverse transformed) signal.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventors: Don Wayne Estes, Randall Joseph Stack
  • Patent number: 8861649
    Abstract: Implementations related to power reduction in physical layer wireless communications are disclosed.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 14, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Thomas M. Conte
  • Patent number: 8819097
    Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Joyce Y. Kwong, Manish Goel
  • Patent number: 8788558
    Abstract: A method of operating a data-processing unit to produce a transform comprises calculating first and second output data values based at least on first and second input data values. The method comprises reading the first and second input data values from locations of a first buffer, the locations being determined by first and second read addresses based on first and second read indices. The method also comprises writing the first and second output data values to adjacent memory locations of a second buffer during a single write cycle. Furthermore, the method comprises reading third and fourth input data values from locations of the second buffer, the locations being determined by third and fourth read addresses determined by swapping at least two of the bits of the first and second read indices respectively. A data-processing unit for producing a transform, a transform-computation unit and an electronic apparatus are also described.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: July 22, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Per Persson
  • Publication number: 20140164460
    Abstract: A digital signal processing apparatus and a digital signal processing method are provided. The digital signal processing apparatus includes a memory, a control logic unit, a butterfly arithmetic unit, a selector, a first twiddle factor generator, a second twiddle factor generator and a twiddle factor latch. The first twiddle factor generator and the second twiddle factor respectively provide a first sub-twiddle factor and a second sub-twiddle factor. A weight value (twiddle factor) is produced by the butterfly arithmetic unit through performing a complex multiplication operation on the first sub-twiddle factor and the second sub-twiddle factor.
    Type: Application
    Filed: February 26, 2013
    Publication date: June 12, 2014
    Applicant: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Tsung-Hsien Hsieh
  • Publication number: 20140164455
    Abstract: A signal is decomposed into different components using a transform, with the components then being separately presented to a person in a manner that produces a different cognitive experience than would have resulted from either (a) presentation of the original signal, or (b) presentation of a fully synthesized (inverse transformed) signal.
    Type: Application
    Filed: June 5, 2013
    Publication date: June 12, 2014
    Inventors: Don Wayne Estes, Randall Joseph Stack
  • Patent number: 8738680
    Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: May 27, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Arunava Chaudhuri, Hemanth Sampath, Iwen Yao, Jeremy H. Lin, Raghu N. Challa, Min Wu
  • Patent number: 8718153
    Abstract: The present invention relates to a signal transmitting apparatus, a method thereof, and an inverse fast Fourier transform (IFFT) apparatus for a signal transmitting apparatus. A signal transmitting apparatus according to an embodiment of the present invention receives data, and performs inverse fast Fourier transform (IFFT) on the data on the basis of a twiddle factor for shifting output data by the size of a cyclic prefix. In addition, the signal transmitting apparatus sequentially stores data corresponding to the size of the cyclic prefix starting with initial data among the transformed data, and generates an OFDM symbol on the basis of the stored data and the transformed data. According to the embodiment of the present invention, it is possible to efficiently reduce a time delay and a memory use amount when a cyclic prefix is added at a transmitting end, without changing the size of hardware and power consumption.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: May 6, 2014
    Assignees: Samsung Electronics Co., Ltd., Electronics and Telecommunications Research Institute
    Inventors: Jun-Woo Kim, Dae-Ho Kim, Young-Ha Lee, Youn-Ok Park
  • Publication number: 20140122553
    Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (?0, ?1, . . . ?v-1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2??0, ej2??1, . . . ej2??v-1) that may be rearranged by a permutation unit (286) for use by vector data path.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Inventors: Leo G. Dehner, Oded Yishay
  • Publication number: 20140101219
    Abstract: Fourier transform computation for distributed processing environments is disclosed. Example methods disclosed herein to compute a Fourier transform of an input data sequence include performing first processing on the input data sequence using a plurality of processors, the first processing resulting in an output data sequence having more data elements than the input data sequence Such example methods also include performing second processing on the output data sequence using the plurality of processors, the output data sequence being permutated among the plurality of processors, each of the processors performing the second processing on a respective permutated portion of the output data sequence to determine a respective, ordered segment of the Fourier transform of the input data sequence.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Inventors: Ping Tak Peter Tang, Jong Soo Park, Vladimir Petrov
  • Patent number: 8694570
    Abstract: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup comprises groupings of elements taken from a plurality of selected dimensions of the input data set for subsequent multidimensional DFT operations.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: April 8, 2014
    Inventors: Arun Mohanlal Patel, Paul Chow
  • Publication number: 20140089365
    Abstract: Object detection receives an input image to detect an object of interest. It determines feature matrices based on the received image, wherein each matrix represents a feature of the received image. The plurality of matrices are Fourier transformed to Fourier feature matrices. Fourier filter matrices are provided, each representing a feature of an object transformed in Fourier space. Each filter matrix is point-wise multiplied with one of the feature matrices corresponding to the same feature. The plurality of matrices are summed, resulting by point-wise multiplying each Fourier filter matrix with the corresponding Fourier feature matrix to obtain a Fourier score matrix. An inverse Fourier transform of the Fourier score matrix is performed, resulting in a score matrix, which is used to detect the object in the input image.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: FONDATION DE I'INSTITUT DE RECHERCHE IDIAP
    Inventors: Charles DUBOUT, Francois FLEURET
  • Publication number: 20140052766
    Abstract: Based at least in part on one or more characteristics relating to a measurement system, a polygonal space in a Fourier domain is determined. A representation of a function that is bandlimited within the polygonal space is computed.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 20, 2014
    Applicant: WESTERNGECO L.L.C.
    Inventors: CAN EVREN YARMAN, RYAN DEAN LEWIS, LUCAS MONZON
  • Patent number: 8649255
    Abstract: A device and a method for Fast Fourier Transform (FFT) are disclosed. The device includes a data receiving module, an address translation module, a data storage module, a FFT module, a data extraction module and a data output module. The data receiving module is configured to receive the input data. The address translation module is configured to duplicate M/N copies of the received data and then send them to the data storage module. The data storage module is configured to store the received data sent by the address translation module to M/N different addresses. The FFT module is configured to perform M-point FFT on the stored data. The data extraction module is configured to extract one point in every several points of the transformed data, and send the extracted data to the data output module. The data output module is configured to output the received data.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: February 11, 2014
    Assignee: ZTE Corporation
    Inventors: Zhi Huang, Daibing Zeng, Xiaolei Sun
  • Patent number: 8639736
    Abstract: A method and apparatus for detecting a signal using a cyclo-stationary characteristic value is provided. A method of detecting a signal using a cyclo-stationary characteristic value includes: calculating cyclo-stationary characteristic values with respect to a cyclic frequency domain of an input signal; multiplying the calculated cyclo-stationary characteristic values with each other; and detecting the signal from the input signal based on the result of the multiplication.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: January 28, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sunmin Lim, Sang-Won Kim, Changhyun Park, Myung Sun Song, Gwangzeen Ko, Chang-Joo Kim
  • Patent number: 8634486
    Abstract: A signal receiving apparatus includes: a processing unit configured to carry out Fourier transform on Fourier-transform data serving as a Fourier-transform object and carry out Fourier transform on inverse-Fourier-transform data serving as an inverse-Fourier-transform object; and a control unit configured to output pieces of data obtained as a result of the Fourier transform carried out on the Fourier-transform data in an order, in which the pieces of data have been obtained, in a process of outputting the pieces of data and output other pieces of data obtained as a result of the Fourier transform carried out on the inverse-Fourier transform data by rearranging the other pieces of data in a process of outputting the other pieces of data.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: January 21, 2014
    Assignee: Sony Corporation
    Inventors: Ryoji Ikegaya, Hidetoshi Kawauchi, Suguru Houchi, Naoki Yoshimochi
  • Patent number: 8612499
    Abstract: We describe a method for using a classical computer to generate a sequence of elementary operations (SEO) that can be used to operate a quantum computer. A quantum computer operating under such a SEO can be used to evaluate certain quantum operator averages.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 17, 2013
    Inventor: Robert R. Tucci
  • Patent number: 8606839
    Abstract: A method for computing a fast Fourier transform (FFT) in a parallel processing structure uses an interleaved computation process. In particular, the interleaved FFT computation process intertwines the output of two different shifted Fourier matrices to obtain a Fourier transform of an input vector. Next, an even-odd extension process is applied to the transformed input vector, whereupon various terms are grouped in a computational tree. As such, the resulting segmentation of the computation allows the fast Fourier transform to be computed in a parallel manner.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: December 10, 2013
    Assignee: The University of Akron
    Inventors: Dale H. Mugler, Nilimb Misal
  • Patent number: 8601044
    Abstract: Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: December 3, 2013
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 8601046
    Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: December 3, 2013
    Assignee: LSI Corporation
    Inventor: David Noeldner
  • Patent number: 8595278
    Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: November 26, 2013
    Assignee: Broadcom Corporation
    Inventors: Kuoruey Han, Peiqing Wang, Linghsiao Wang, Kishore Kota, Arash Farhoodfar
  • Patent number: 8577946
    Abstract: There is provided a signal receiving apparatus including first to pth stage computers configured to apply, in a step-by-step manner, butterfly operations to 2N input values; and 2N registers configured to store values obtained by a p?1th stage computer wherein the pth stage computer includes (a) 2L butterfly operation circuits configured to transmit, from corresponding 2M output ports, values obtained by the butterfly operations based on values provided to 2M input ports and (b) 2L selecting circuits arranged corresponding to the butterfly operation circuits, each selecting circuit providing a value of a register corresponding to different one of 2L BFInOrder_i(j,t) (wherein, BFInOrder_i(j,t) denotes values obtained by converting BFOutOrder_i(j,t)=t+j*2(N?M)+i*2N?(M+L) or (2(N?(M+L))?1?t)+j*2(N?M)+i*2(N?(M+L)) expressed by base H to base 2M of (log2M 2N)?1 words, word-reversing the values converted to base 2M, and converting the word-reversed values to the base H).
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichiro Horikawa, Koichiro Ban
  • Patent number: 8572148
    Abstract: A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 29, 2013
    Assignee: Xilinx, Inc.
    Inventors: Gabor Szedo, Hemang Parekh
  • Patent number: 8572149
    Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: October 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Brian C. Banister, Surendra Boppana
  • Patent number: 8566382
    Abstract: Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: October 22, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Larry Pearlstein, Richard K. Sita