Abstract: A method of reading from a storage medium to recover a group of information sectors, each comprising a respective information payload. The medium stores redundancy data comprising a plurality of separate redundancy codes for the group, each code being a linear sum of terms, each term in the sum being the information payload from a different respective one of the information sectors in the group weighted by a respective coefficient of a set of coefficients for the redundancy code. The method comprises, after the redundancy data has already been stored on the medium: identifying a set of k? information sectors to be recovered; selecting k? of the redundancy codes; determining a square matrix E of the k? information sectors by the k? sets of coefficients of the selected codes; determining a matrix D being a matrix inverse of E; and recovering the k? information payloads from the inverse matrix D.

Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Abstract: Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Abstract: Apparatus and method to transform complex data including a processor that comprises: multiplier circuitry to multiply packed complex N-bit data elements with packed complex M-bit data elements to generate at least four real products; adder circuitry to subtract a first real product from a second real product to generate a first temporary result, subtract a third real product from a fourth real product to generate a second temporary result, add the first temporary result to a first packed N-bit data element to generate a first pre-scaled result, subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, add the second temporary result to a second packed N-bit data element to generate a third pre-scaled result, and subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; and scaling circuitry to scale the pre-scaled results.

Abstract: Provided are a video encoding method of adjusting a range of encoded output data to adjust a bit depth during restoring of encoded samples, and a video decoding method of substantially preventing overflow from occurring in output data in operations of a decoding process. The video decoding method includes parsing and restoring quantized transformation coefficients in units of blocks of an image from a received bitstream, restoring transformation coefficients by performing inverse quantization on the quantized transformation coefficients, and restoring samples by performing one-dimensional (1D) inverse transformation and inverse scaling on the quantized transformation coefficients. At least one from among the transformation coefficients and the samples has a predetermined bit depth or less.

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode are described.

Abstract: Provided are a video encoding method of adjusting a range of encoded output data to adjust a bit depth during restoring of encoded samples, and a video decoding method of substantially preventing overflow from occurring in output data in operations of a decoding process. The video decoding method includes parsing and restoring quantized transformation coefficients in units of blocks of an image from a received bitstream, restoring transformation coefficients by performing inverse quantization on the quantized transformation coefficients, and restoring samples by performing one-dimensional (1D) inverse transformation and inverse scaling on the quantized transformation coefficients. At least one from among the transformation coefficients and the samples has a predetermined bit depth or less.

Abstract: Provided are a video encoding method of adjusting a range of encoded output data to adjust a bit depth during restoring of encoded samples, and a video decoding method of substantially preventing overflow from occurring in output data in operations of a decoding process. The video decoding method includes parsing and restoring quantized transformation coefficients in units of blocks of an image from a received bitstream, restoring transformation coefficients by performing inverse quantization on the quantized transformation coefficients, and restoring samples by performing one-dimensional (1D) inverse transformation and inverse scaling on the quantized transformation coefficients. At least one from among the transformation coefficients and the samples has a predetermined bit depth or less.

Abstract: Methods are provided for reducing the size of a transpose buffer used for computation of a two-dimensional (2D) separable transform. Scaling factors and clip bit widths determined for a particular transpose buffer size and the expected transform sizes are used to reduce the size of the intermediate results of applying the 2D separable transform. The reduced bit widths of the intermediate results may vary across the intermediate results. In some embodiments, the scaling factors and associated clip bit widths may be adapted during encoding.

Abstract: Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

Abstract: The present invention provides technologies for implementing a high-speed Fast Fourier Transform (FFT) algorithm with a small memory. An information processing apparatus for performing a radix-2 FFT on a data sequence comprises storage means, reading means, a plurality of butterfly operation means, writing means, and control means, wherein each stage of the FFT operation includes a plurality of operation steps, and at every operation step the control means controls each of the means so that: the reading means reads from the storage means sets of data elements referred by storage addresses A, A+1, A+2m, and A+2m+1, the plurality of butterfly operation means perform radix-2 butterfly operation on the data elements in the sets, and the writing means writes the sets of the result data into the storage area referred by the storage addresses A, A+1, A+2m, and A+2m+1.

Abstract: A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided.

Abstract: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

Abstract: A method of operating a data-processing unit to produce a transform comprises calculating first and second output data values based at least on first and second input data values. The method comprises reading the first and second input data values from locations of a first buffer, the locations being determined by first and second read addresses based on first and second read indices. The method also comprises writing the first and second output data values to adjacent memory locations of a second buffer during a single write cycle. Furthermore, the method comprises reading third and fourth input data values from locations of the second buffer, the locations being determined by third and fourth read addresses determined by swapping at least two of the bits of the first and second read indices respectively. A data-processing unit for producing a transform, a transform-computation unit and an electronic apparatus are also described.

Abstract: A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: There is provided a signal receiving apparatus including first to pth stage computers configured to apply, in a step-by-step manner, butterfly operations to 2N input values; and 2N registers configured to store values obtained by a p?1th stage computer wherein the pth stage computer includes (a) 2L butterfly operation circuits configured to transmit, from corresponding 2M output ports, values obtained by the butterfly operations based on values provided to 2M input ports and (b) 2L selecting circuits arranged corresponding to the butterfly operation circuits, each selecting circuit providing a value of a register corresponding to different one of 2L BFInOrder_i(j,t) (wherein, BFInOrder_i(j,t) denotes values obtained by converting BFOutOrder_i(j,t)=t+j*2(N?M)+i*2N?(M+L) or (2(N?(M+L))?1?t)+j*2(N?M)+i*2(N?(M+L)) expressed by base H to base 2M of (log2M 2N)?1 words, word-reversing the values converted to base 2M, and converting the word-reversed values to the base H).

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A pipelined FFT circuit used for processing a sequential input data with a set of N samples comprises a data division unit, a data-preprocessing unit and M sets of data computation unit. The data division unit is used for dividing the sequential input data into a first input data stream and a second input data stream. The data-preprocessing unit receives the first and second input data streams and orders the first input data stream to an odd number-index data stream, the second input data stream to an even number-index data stream respectively. Each of the data computation units has a data switch and a butterfly computator connected with the data switch, where M=log2N, the data switch of the first data computation unit is connected with the data-preprocessing unit.

Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.

Abstract: An FFT engine implementing a cycle count method of applying twiddle multiplications in multi-stages. When implementing a multistage FFT, the intermediate values need to be multiplied by various twiddle factors. The FFT engine utilizes a minimal number of multipliers to perform the twiddle multiplications in an efficient pipeline. Optimizing a number of complex multipliers based on an FFT radix and a number of values in each row of memory allows the FFT function to be performed using a reasonable amount of area and in a minimal number of cycles. Strategic ordering and grouping of the values allows the FFT operation to be performed in a fewer number of cycles.

Abstract: A communication system includes: a sampling section that samples a reception signal; a preprocessing execution section that acquires a sampling value, which is obtained by the sampling section, while executing preprocessing for performing a Fast Fourier Transform in a divided manner; and a Fast Fourier Transform section that performs the Fast Fourier Transform in the divided manner on the basis of an output acquired from the processing execution section.

Abstract: A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Abstract: An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2M size data frame are provided. The data frame is split and fast Fourier transform (FFT) processed as three sub-frames. Radix-3 operations are performed on the FFT processed sub-frames over a number of stages with time shared hardware to compute the DFT of the data-frame. FFT operations are performed on the second and third sub-frames to produce respective sub-transforms. Concurrently with FFT processing of the first sub-frame, butterfly operations are performed on the sub-transforms of the second and third sub-frames. Through the use of time-shared hardware and arranging FFT operations to correspond with radix-3 operations at various stages of processing, the DFT is performed with existing FFT processors while reducing resource requirements and/or reducing DFT transform time over the full-parallel radix-3 implementation.

Abstract: A Fourier transform processor that is used in wireless communication includes: a Fourier transform mechanism including a butterfly unit and configured to perform a Fourier transform on data that is input to the Fourier transform processor; a first memory configured to store the data that is input to the Fourier transform mechanism; a first commutator configured to rearrange the data that is input to the first memory; and a second commutator configured to rearrange the data that is output from the first memory and that is input to the butterfly unit. This configuration allows the size and power consumption of the Fourier transform processor to be reduced.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.

Abstract: A high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same. The high-speed radix-4 butterfly module includes first to fourth add-compare-select (ACS) circuits. The first and the second ACS circuits receive first to fourth branch metric values and first to fourth previous-stage path metric values, and accordingly produces a first and a second path metric values. The third and the fourth ACS circuits receive fifth to eighth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a third and a fourth path metric values. The radix-4 butterfly unit of the invention uses the symmetric relation to reduce an amount of branch computation required for each radix-4 butterfly unit to a half. Thus, the circuit complexity of the typical radix-4 butterfly module and the hardware cost of the Viterbi decoder are reduced.

Abstract: The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.

Abstract: A Decimation In Frequency (DIF) Fast Fourier Transform (FFT) stage is used in an N bin FFT, wherein N is an even integer. The DIF FFT stage includes swap logic that receives a first input sample, x(v), and a second input sample, x(v+N/2), and selectively supplies either the first and second input samples at respective first and second swap logic output ports or alternatively the second and first input samples at the respective first and second swap logic output ports, wherein 0?v<N/2. The DIF FFT stage further includes a summing unit for adding values supplied by the first and second swap logic output ports; a differencing unit for subtracting values supplied by the first and second swap logic output ports; and twiddle factor logic that multiplies a value supplied by the differencing unit by a twiddle factor, WN(v+s)mod(N/2), where s is an integer representing an amount of circular shift of N input samples.

Abstract: An FFT butterfly instruction based on single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT butterfly operation (e.g., non-SIMD, 2-way SIMD, 4-way SIMD, etc.), at once, each instance operating over a set of complex values. A control register or variant opcode controls the behavior of the FFT butterfly operation. The contents of the control register or the variant opcode can be altered to configure the butterfly behavior to suit specific circumstances. The FFT butterfly instruction can be used in the software on a processor in a chip-set implementing the central-office modem end of a DSL link. The FFT butterfly instruction can also be used in other contexts where an FFT function is performed (and/or where an FFT butterfly operation is used) including systems that do not implement DSL or DMT.

Abstract: A method of processing a set of input data values comprises the steps of providing said input data values serially to circuitry comprising a number of memory elements; and performing in said circuitry a transform function to obtain a set of transformed data values. The method further comprises the steps of delaying a subset of said set of input data values under use of said memory elements; providing a modified set of data values by adding individual delayed data values to individual non-delayed data values from said set of input data values; and performing said transform function on said modified set of data values. In this way a transform function can be evaluated at fewer output data values than available input data values without increasing the memory requirements considerably.

Abstract: A wireless communication technique enables fast Fourier transforms (FFTs) and inverse fast Fourier transforms (IFFTs) to be performed with reduced latency and reduced memory requirements. In particular, an FFT/IFFT unit receives input data representative of a communication symbol. The FFT/IFFT unit applies an FFT operation to the input data to generate intermediate data. The FFT/IFFT unit stores the intermediate data in a random access memory (RAM). The intermediate data stored in the RAM may override data used as input to the FFT operation. The FFT/IFFT unit selectively addresses the RAM to retrieve the intermediate data in a desired output order. For example, the FFT/IFFT unit may output the intermediate data in the same sequential order as the FFT/IFFT unit received the input data.

Abstract: A method for the generation of addresses of successive pairs of input data values of stages of a Fast Fourier Transform calculation stored contiguously in a memory includes initializing at most once per stage a first base address pointer to an address of a first input data value of an initial butterfly calculation of the stage and a second base address pointer to an address of a second input data value of the initial butterfly calculation, and initializing at most once per stage a first constant and a second constant. Pairs of input data values of successive butterfly calculations in the stage are then addressed using the first base address pointer, the second base address pointer, the first constant and the second constant.

Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Abstract: A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline ?{square root over (N)} point fast Fourier transform (FFT) modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFTs, the modular pipeline FFT maintains the bandwidth of existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory configured to operate on sample data. The architecture further includes a programmable address generation unit coupled to the pipeline to enable the architecture to perform calculations independent of Fourier-based algorithms. A method for addressing memory banks for an FFT pipeline includes expressing an index in radix notation, computing a bank address for a bank memory, converting the bank address to a reduced size by ignoring one or more bits, and calculating the bank address within the reduced memory bank.

Abstract: A fast implementation of the 8-point transform is realized using a sequence of butterfly operations and matrix multiplies. A fast implementation of the inverse transform is realized by applying inverses of the butterfly operations with the matrix multiplies in reverse flow. These fast implementations permit scaling to be incorporated into the transform stages either at the end of both dimensions of filtering, or separately at each stage. These fast implementations of the transform can be used in encoders and decoders based on this transform in image compression and other signal processing systems.

Abstract: A data processing apparatus having data cache performs an N-point radix-R Fast Fourier Transform. If the data set is smaller than the data cache, the data processing apparatus performs the Fast Fourier Transform in logRN stages on all the data set in one pass. If the data set is larger than the data cache but smaller than R times the data cache, the data processing apparatus performs a first stage radix-R butterfly computation on all the input data producing R independent intermediate data sets. The data processing apparatus then successively performs second and all subsequent stage butterfly computations on each independent intermediate data set in turn producing corresponding output data. During the first stage radix-R butterfly computations, each of R continuous sets are separated in memory by memory locations equal to the size of a cache line.

Abstract: A fast Fourier transform processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel interleaver. The modified butterfly unit is obtained by the removal of complex variable multipliers, which is possible due to the simplification of twiddle factors in the stages that correspond to the modified butterfly unit.

Abstract: A high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same. The high-speed radix-4 butterfly module includes first to fourth add-compare-select (ACS) circuits. The first and the second ACS circuits receive first to fourth branch metric values and first to fourth previous-stage path metric values, and accordingly produces a first and a second path metric values. The third and the fourth ACS circuits receive fifth to eighth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a third and a fourth path metric values. The radix-4 butterfly unit of the invention uses the symmetric relation to reduce an amount of branch computation required for each radix-4 butterfly unit to a half. Thus, the circuit complexity of the typical radix-4 butterfly module and the hardware cost of the Viterbi decoder are reduced.

Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.

Abstract: A method of transferring data from a first device to a second device, the method including receiving information at the second device; and converting first data, from the first device, from the time domain to the frequency domain using butterfly computations to produce second data, wherein the butterfly computations used are a subset of the available butterfly computations and are selected using the received information.

Abstract: A method for improving precision in FFT calculations. For each iteration in an FFT implementation, a constant normalization multiplier is inserted such that the dynamic ranges of the input and output are the same. The final FFT output is multiplied by a constant normalization factor given by the number of iterations and the constant normalization multiplier.

Abstract: A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage; scales the butterfly outputs of this stage from a predicted normalization scale factor to obtain the maximum butterfly output without overflow from this stage; determines from the butterfly outputs of this stage the minimum normalizing exponent for the butterfly outputs of this stage and predicts a normalization scale factor of the next stage from the minimum normalizing exponent of this stage and a stage guard scale value to obtain the maximum butterfly output without overflow from that next stage.

Abstract: A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed.

Abstract: An FFT (Fast Fourier Transform) processor is disclosed which is a core block of an OFDM (Orthogonal Frequency Division Multiplexing) or DMT (Discrete Multi-tone) MODEM. The FFT processor simultaneously performs sequential input and output by applying an in-place algorithm for a mixed-radix multi-bank memory, thereby realizing continuous processing with only a 2N-word memory having 4 banks. The FFT processor minimizes its complexity while satisfying a high-speed calculation requirement.