Abstract: The embodiments of this application provide a method and device for optimizing neural network. The method includes: binarizing and bit-packing input data of a convolution layer along a channel direction, and obtaining compressed input data; binarizing and bit-packing respectively each convolution kernel of the convolution layer along the channel direction, and obtaining each corresponding compressed convolution kernel; dividing the compressed input data sequentially in a convolutional computation order into blocks of the compressed input data with the same size of each compressed convolution kernel, wherein the data input to one time convolutional computation form a data block; and, taking a convolutional computation on each block of the compressed input data and each compressed convolution kernel sequentially, obtaining each convolutional result data, and obtaining multiple output data of the convolution layer according to each convolutional result data.

Abstract: An apparatus for convolution operation is provided.

Abstract: In accordance with an aspect of the present disclosure, there is provided a convolution operation method.

Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.

Abstract: Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.

Abstract: In an approach to processing large high dimensional images in parallel without losing accuracy, one or more computer processors determine a required amount of graphics processing unit memory for an image. The one or more computer processors determine one or more coordinate partitions based on the determined required amount of graphics and one or more characteristics of the image. The one or more computer processors determine a padding size for each of the determined one or more coordinate partitions. The one or more computer processors partition the image based on the one or more determined coordinate partitions and the determined padding size. The one or more computer processors generate a prediction for the partitioned image utilizing a trained model.

Abstract: Artificial intelligence is an increasingly important sector of the computer industry. One of the most important applications for artificial intelligence is object recognition and classification from digital images. Convolutional neural networks have proven to be a very effective tool for object recognition and classification from digital images. However, convolutional neural networks are extremely computationally intensive thus requiring high-performance processors, significant computation time, and significant energy consumption. To reduce the computation time and energy consumption a “cone of dependency” and “cone of influence” processing techniques are disclosed. These two techniques arrange the computations required in a manner that minimizes memory accesses such that computations may be performed in local cache memory. These techniques significantly reduce the time to perform the computations and the energy consumed by the hardware implementing a convolutional neural network.

Abstract: Some embodiments perform, in a multi-layer neural network in a computing device, a convolution operation on input feature maps with multiple convolutional filters. The convolutional filters have multiple filter precisions. In other embodiments, electronic design automation (EDA) systems, methods, and computer-readable media are presented for adding such a multi-layer neural network into an integrated circuit (IC) design.

Abstract: An information processing method includes: inputting an input tensor indicating data to a processor having a memory; causing the processor to perform, after elements of the input tensor are subjected to precomputation for conversion into a power-of-two format and are stored in the memory, convolution operation processing with only addition and shift operations by using the precomputed elements of the input tensor stored in the memory and weight tensors that are pre-converted into the power-of-two format in accordance with a predetermined algorithm, that are stored in the memory, and that indicate weights having a possibility of being used for a convolution operation; and outputting, as an output tensor, the elements of the input tensor on which the convolution operation processing is performed.

Abstract: A system and method for convolutional layer in convolutional neural networks is provided. The convolution is performed via a transformation that includes relocating input, relocating convolution filters and performing an aggregate matrix multiply.

Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.

Abstract: A convolutional layer in a convolutional neural network uses a predetermined horizontal input stride and a predetermined vertical input stride that are greater than 1 while the hardware forming the convolutional layer operates using an input stride of 1. Each original weight kernel of a plurality of sets of original weight kernels is subdivided based on the predetermined horizontal and vertical input strides to form a set of a plurality of sub-kernels for each set of original weight kernels. Each of a plurality of IFMs is subdivided based on the predetermined horizontal and vertical input strides to form a plurality of sub-maps. Each sub-map is convolved by the corresponding sub-kernel for a set of original weight kernels using an input stride of 1. A convolved result of each sub-map and the corresponding sub-kernel is summed to form an output feature map.

Abstract: An arithmetic processing device according to the present embodiment includes: a first storage device including m (m?2) groups each including at least one first array; a second storage device including n (m>n?1) groups each including at least one second array; a third storage device including at least one third array; a fourth storage device including k (m>k?1) fourth arrays; and a processor, the processor selecting n groups of the first array from among the m groups of the first array, reading out data stored in memory elements of the first array included in the selected groups, storing the data in the memory elements of the second array of the second storage device, and the processor performing a convolution process to the third array using the data stored in the memory elements of the second array and storing a result of the convolution process in the fourth arrays.

Abstract: A convolutional neural network-based image processing method is provided. The method includes: receiving, in a second layer, multi-channel feature map images generated by applying a convolution operation to an input image of a convolutional neural network having a plurality of layers with a plurality of filter kernels of a first layer; analyzing a dynamic range of the multi-channel feature map images; re-ordering the multi-channel feature map images, based on the dynamic range; and processing the re-ordered multi-channel feature map images in the second layer.

Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.

Abstract: The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

Abstract: A system performs convolution computing in either a matrix mode or a filter mode. An analysis module generates a mode select signal to select the matrix mode or the filter mode based on results of analyzing convolution characteristics. The results include at least a comparison of resource utilization between the matrix mode and the filter mode. A convolution module includes processing elements, each of which further includes arithmetic computing circuitry. The convolution module is configured according to the matrix mode for performing matrix multiplications converted from convolution computations, and is configured according to the filter mode for performing the convolution computations.

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

Abstract: The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

Abstract: A convolution operation method includes the following steps of: performing convolution operations for data inputted in channels, respectively, so as to output a plurality of convolution results; and alternately summing the convolution results of the channels in order so as to output a sum result. A convolution operation device executing the convolution operation method is also disclosed.

Abstract: A system clock signal is distributed to computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers, include input and output ports on which system clock signals are propagated. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.

Abstract: Methods and devices for LTE cell search with large frequency offset are disclosed. In one embodiment of the invention, a UE divides the received signals into multiple frequency bins and transforms the signals into frequency domain through FFT. The UE performs correlating measures between the received signals and reference signals. The UE then performs an adaptive multi-try based peak selection such that the number of candidate is reduced. In one embodiment of the invention, the multi-try number is adaptively adjusted based on the channel condition. In one embodiment of the invention, the threshold of the peak selection is adaptively adjusted. In other embodiments of the invention, the UE performs non-coherent accumulation and selects a predefined number of coarse bin candidates. The number of non-coherent accumulation is adaptively adjusted. In another embodiment of the invention, the UE performs fractional frequency offset estimation and selects a fine bin candidate.

Abstract: In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative adders accumulate output from the plurality of multipliers, a third storage unit latches output from the plurality of cumulative adders at predetermined timing, a fourth storage unit stores data to be stored in the first and the second storage units and data output from the third storage unit, and a control unit sets data stored in the first and the second storage units to the first and the second shift registers at predetermined timing, causes the first and the second shift registers to perform shift operations in synchronization with an operation of the cumulative adder.

Abstract: A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution.

Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

Abstract: A system and method are provided for approximating a diffusion profile utilizing gathered lighting information associated with an occluded portion of an object. In use, the present technique gathers information associated with an occluded portion of an object that is illuminated with a two-dimensional pattern of light including an edge which defines an illuminated portion and the occluded portion of the object. To this end, a diffusion profile of the object is approximated, utilizing such information.

Abstract: A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution.

Abstract: A filtering apparatus for obtaining an output in a case where a discrete-time signal having a length of N (N is an integer) is input to an FIR filter with a filter coefficient having a length of M (M is an integer, N?M?1), including: a division unit for dividing the discrete-time signal; a first zero padding unit for padding zero after the discrete-time signals; a first fast Fourier transform unit for performing FFT on the zero padded data; a second zero padding unit for padding zero after the filter coefficient; a second fast Fourier transform unit for performing FFT on the zero padded data; a multiplication unit for multiplying the frequency domain data by the frequency domain data; an inverse fast Fourier transform unit for performing IFFT on the multiplication results; and an adder unit for adding the discrete-time signals.

Abstract: Convolutions are frequently used in signal processing. A method for performing an ordinal convolution is disclosed. In an embodiment of the disclosed subject matter, an ordinal mask may be obtained. The ordinal mask may describe a property of a signal. A representation of a signal may be received. A processor may convert the representation of the signal to an ordinal representation of the signal. The ordinal mask may be applied to the ordinal representation of the signal. Based upon the application of the ordinal mask to the ordinal representation of the signal, it may be determined that the property is present in the signal. The ordinal convolution method described herein may be applied to any type of signal processing method that relies on a transform or convolution.

Abstract: A method of modeling a room impulse response according to an embodiment of the invention includes receiving a sound pressure signal that is obtained by a microphone when an impulse-type sound source is excited and detecting a room impulse response; determining boundaries between a plurality of intervals of the room impulse response such that the room impulse response is divided into the plurality of intervals on a time domain; and modeling the room impulse response for each of the plurality of divided intervals using at least two different modeling schemes.

Abstract: A method of fast matrix multiplication and a method and apparatus for fast solving of a matrix equation are disclosed. They are useful in many applications including image blurring, deblurring, and 3D image reconstruction, in 3D microscopy and computer vision. The methods and apparatus are based on a new theoretical result—the Generalized Convolution Theorem (GCT). Based on GCT, matrix equations that represent certain linear integral equations are first transformed to equivalent convolution integral equations through change of variables. Then the resulting convolution integral equations are evaluated or solved using the Fast Fourier Transform (FFT). Evaluating a convolution integral corresponds to matrix multiplication and solving a convolution integral equation corresponds to solving the related matrix equation through deconvolution. Carrying-out these convolution and deconvolution operations in the Fourier domain using FFT speeds up computations significantly.

Abstract: A method for converting a sampling frequency of a digital signal sampled at a first sampling frequency includes receiving digital signal input samples, and forming output samples corresponding to a second sampling frequency based on the digital signal input samples and an interpolation filter. The first sampling frequency may be larger than the second sampling frequency. The method may further include delivering the output samples. Forming output samples includes, for each of the digital signal input samples, updating current values of N successive output samples with N contributions. The N contributions may be respectively calculated based on a value of a current input sample of the digital input samples weighted by values of N filter coefficients associated with the current input sample, N being fixed and identical for all the digital signal input samples regardless of a value of the conversion ratio between the first and second sampling frequencies.

Abstract: A digital image-processing device with a Bayer sensor and an image memory is provided in which the image data of the sensor is written into an image memory, and from this image memory, image data in the Bayer format with a length L and a width B is written continuously into a data buffer, and in which the sample values are combined by means of a computational device with the help of adders, in each case symmetrically to a central point of one or more (2n+1)×(2n+1) neighborhoods, and one or more (n+1)×(n+1) matrices are derived by means of the computational device, and from this (n+1)×(n+1) matrix or these matrices, with the help of additional adders, at least one n×n matrix is formed, and a first color component is in each case calculated from this by means of an adder network.

Abstract: Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value.

Abstract: A method of extracting a voice command produced in an enclosed or partially enclosed environment, includes providing an impulse response signal of the enclosed or partially enclosed environment; recording the voice command and ambient sounds; and using the impulse response signal to extract the recorded voice command.

Abstract: Provided is a deterministic component model determining apparatus that determines a type of a deterministic component included in a probability density function supplied thereto, comprising a standard deviation calculating section that calculates a standard deviation of the probability density function; a spectrum calculating section that calculates a spectrum of the probability density function; a null frequency detecting section that detects a null frequency of the spectrum; a theoretical value calculating section that calculates a theoretical value of a spectrum for each of a plurality of predetermined types of deterministic components, based on the null frequency; a measured value calculating section that calculates a measured value of the spectrum for the deterministic component included in the probability density function, based on the standard deviation and the spectrum; and a model determining section that determines the type of the deterministic component included in the probability density function

Abstract: There is provided a convolution operation circuit that performs a convolution operation on a provided digital signal. The convolution operation circuit includes a data dividing section that generates a plurality of divided data obtained by dividing respective amplitude data of the digital signal into a plurality of bit areas, an arithmetic section that performs a predetermined convolution operation on the respective divided data of the respective amplitude data in a time-sharing mode and outputs the result, and a coupling section that couples the divided data output from the arithmetic section for each of the amplitude data.

Abstract: A system and method for performing convolution in a single channel of a vector processing computer system takes advantage of the parallel computing capability of the vector processing system and the distributed properties of the discrete-time convolution sum by performing convolution on portions of an overall data stream, or data chunks, simultaneously. Partial solution are thereby obtained and superimposed to achieve an overall solution data stream. To simplify the convolution sum and eliminate the need for calculating products, a specialized data signal or vector containing a series of ones may be used in the convolution operation.

Abstract: The linear equalizer (LE) coefficients for code-division-multiplexed (CDM) pilot systems can be determined based upon frequency-domain calculations involving channel impulse responses. A channel impulse response can be formed at the mobile terminal by suitably filtering and despreading the received baseband signal with respect to the pilot Walsh channel. The channel frequency response is then determined based on the fast Fourier transform (FFT) of the channel impulse response. Frequency-domain equalizer coefficients can be determined from the channel frequency response. The frequency-domain equalizer coefficient can be utilized to determine time-domain equalizer coefficients to implement the equalizer in time domain, or be utilized to implement the equalizer in frequency domain.

Abstract: The device determines the weighting coefficients to be applied to N digital source signals to form a composite signal. The first- to third-order moments of the composite signal must respectively present mean value, variance and skewness characteristics predefined by a user. The device introduces an additional variable, in the form of a weighting matrix W. The vector w being the vector of the weighting coefficients and wT the transpose of the vector w, the difference W?wwT is a positive semidefinite matrix. Moreover, the device performs linearization, around a vector wref of reference weighting coefficients, of the skewness constraint on the third-order moments using a matrix A = [ W w w T 1 ] as further intermediate variable.

Abstract: A programming algorithm reduces from ? (2N2) to ? (N2) the number of multiply-and-accumulate (MAC) instructions required to perform a discrete-time convolution on a programmable digital signal processor. Through the use of a single repeat instruction along with a single repeat count register, the algorithm dynamically changes the number of times the multiply-accumulate instruction is repeated depending upon the current term being convolved. The avoids performing the multiply-accumulate when one term is zero. The nature of the discrete-time convolution calculation and the flexibility of a re-programmable single repeat count register offers permits this. Additional instructions are required for data pointer alignment. The trade-off between reduced multiply-accumulate operations and the overhead required to achieve it is examined.

Abstract: A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

Abstract: One or more embodiments are disclosed that involve computer implementable techniques for generating simulate-able waveforms without the need for repeatedly including and simulating a full channel model or testing the waveforms on a physical channel. Techniques according to such embodiments the invention comprise simulating the sending of a waveform across a channel and recording deviations from a simulated received waveform, which comprise differences between the ideal waveform as sent and the simulated received waveform. These deviations are then used to create simulate-able waveforms, which include the effects of noise and jitter, without the need for additional channel simulation. As an alternative to using channel simulation, deviations may also be collected from sending a waveform across a physical channel.

Abstract: A convolution integrator that can be used favorably to prepare, at high speed, a computer generated hologram that can reproduce a reproduction image formed by reproduction points at various distances and differing in initial phase is provided. A plurality of element processors PE are practically cascade-connected. Each element processor PE includes: a constant generator 91A, outputting a propagation function value that is generated based on a coordinate value Z and an initial phase value P; a multiplier 92, multiplying the propagation function value and a luminance value I and outputting the product value; an adder/subtractor 93, performing addition/subtraction on the product value and a hologram time series signal PDin and outputting the sum/difference value; and a register 94, receiving, holding, and then outputting the sum/difference value as a hologram time series signal PDout.

Abstract: There is provided a convolution operation circuit that performs a convolution operation on a provided digital signal. The convolution operation circuit includes a data dividing section that generates a plurality of divided data obtained by dividing respective amplitude data of the digital signal into a plurality of bit areas, an arithmetic section that performs a predetermined convolution operation on the respective divided data of the respective amplitude data in a time-sharing mode and outputs the result, and a coupling section that couples the divided data output from the arithmetic section for each of the amplitude data.

Abstract: A process for loading a signal data values and convolution filter coefficient values into a target processor (ct) in a set of processors (cutil) utilized to calculate a convolution. The coefficient values are mapped to cutil. An interleave of the data values and of the coefficient values determined for ct. The coefficient values are loaded in ct and the data values are loaded in ct, thereby preparing ct to participate in calculating the convolution.

Abstract: The embodiments herein provide a device and method to generate Pre-emphasized signal. In one embodiment herein an input file containing digital data representing a digital data pattern waveform is received and up-sampled by an Fs/Fd rate. The up-sampled digital data is used for generating step response. The generated step response is differentiated to generate coefficients of a pre-emphasis filter which are convolved with the digital data pattern waveform input signal to generate a pre-emphasized digital data pattern waveform file.

Abstract: An instrument for measuring the size and characteristics of a particle contained in a sample of particles. A particle sample is introduced into a sample chamber. The sample particles are subjected to centrifugal forces so that large particles travel in the sample chamber at velocities greater than small particles. Light is shown upon the particles as they travel in the sample chamber. The particles diffract the light. The diffracted light is then received by detectors that convert the diffracted light into corresponding electronic signals. The electronic signals are analyzed to determine the size and characteristics of the particles that caused the diffracted light.