Abstract: Provided are a method and apparatus for setting high address bits in a memory module. A memory module controller in the memory module, having pins to communicate on a bus, determines whether high address bits are available for the memory module, uses a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module, and uses values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

Abstract: The present invention relates to a method for processing a digital input signal by a Finite Impulse Response, FIR, filtering means, comprising partitioning the digital input signal at least partly in the time domain to obtain at least two partitions of the digital input signal; partitioning the FIR filtering means in the time domain to obtain at least two partitions of the FIR filtering means; Fourier transforming each of the at least two partitions of the digital input signal to obtain Fourier transformed signal partitions; Fourier transforming each of the at least two partitions of the FIR filtering means to obtain Fourier transformed filter partitions; performing a convolution of the Fourier transformed signal partitions and the corresponding Fourier transformed filter partitions to obtain spectral partitions; combining the spectral partitions to obtain a total spectrum; and inverse Fourier transforming the total spectrum to obtain a digital output signal.

Abstract: A circuit and method for computing the circular convolution of an input signal with a finite impulse response operates to store initial input samples of the input signal, perform convolution of the remaining input samples in the block of input samples and then supplying the stored initial input samples for convolution, thereby generating circular convolution output samples.

Abstract: A method for generating a transmit sequence in a single carrier frequency division multiple access (SC-FDMA) transmitter is disclosed. In one embodiment, the method includes generating a first time domain sequence, transforming the first time domain sequence to a first frequency domain sequence according to a first transform, distributing the first frequency domain sequence among a subset of subcarriers among a plurality of subcarriers in a second frequency domain sequence, transforming the second frequency domain sequence to a second time domain sequence, and adding a cyclic prefix to the second time domain sequence to form a transmit sequence. In one exemplary embodiment, the first time domain sequence is a plurality of pilot symbols that have known properties e.g., a constant amplitude, and zero autocorrelation (CAZAC).

Abstract: A method for receiving a pilot symbol in a receiver is disclosed. In one embodiment, the method includes removing a cyclic prefix from a received sequence to produce a modified sequence, transforming the modified sequence to a first frequency domain sequence according to a first transform, demapping a plurality of distributed subcarriers in the transformed modified sequence to extract a plurality of received symbols, deriving an intermediate channel estimate for each of the plurality of received symbols, and interpolating a final channel estimate based on the plurality of derived intermediate channel estimates. In one exemplary embodiment, the received symbols have one or more predefined characteristics such as a constant amplitude, and zero autocorrelation (CAZAC sequence).

Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).

Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).

Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. Substantially the same hardware can be utilized for processing in-phase and quadrature phase components of the data word (X0-XM-1). The coefficients (C0-CM-1) can represent real numbers and/or complex numbers. The coefficients (C0-CM-1) can be represented with a single bit or with multiple bits (e.g., magnitude). The coefficients (C0-CM-1) represent, for example, a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.

Abstract: A DTD-compliant XML document editor is disclosed. The XML document editor generates hints for required elements and required element slots automatically in the process of document creation and edition so as to guide the user to produce a valid document, while syntactic violations are avoided at the same time. The editor also suggests optional elements that may be added into the document to be edited. The user requires no knowledge about XML and DTD to edit DTD-compliant XML documents. The editing process is user-interface-neutral, being able to support user interfaces based on tree views, presentation views and forms. By combining the DTD-compliant editing process with the simplicity of forms, a simple XML document editor with forms as its user interface is developed.

Abstract: The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU.