Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

Abstract: Systems and methods for protocol processing using a systolic array (e.g., programmed in an FPGA). For example, protocol processing is performed for incoming data (e.g., received for storage) prior to encryption and/or sending to a remote storage device (e.g., cloud storage or server).

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: An electronic apparatus includes a processor configured to acquire a plurality of characteristic data of a plurality of users through a communication interface circuitry; identify a plurality of categories and reference characteristics for analyzing the plurality of characteristic data according to an input received through the communication interface circuitry; identify specific characteristic data that corresponds to the reference characteristics, among the plurality of characteristic data for each of the plurality of categories; identify a specific user having the specific characteristic data, among the plurality of users; and output an analysis result of the specific characteristic data of the specific user.

Abstract: A processor includes an internal memory and processing circuitry. The internal memory is configured to store a definition of a multi-dimensional array stored in an external memory, and indices that specify elements of the multi-dimensional array in terms of multi-dimensional coordinates of the elements within the array. The processing circuitry is configured to execute instructions in accordance with an Instruction Set Architecture (ISA) defined for the processor. At least some of the instructions in the ISA access the multi-dimensional array by operating on the multi-dimensional coordinates specified in the indices.

Abstract: A computer-implemented method is provided for performing bitonic merge operations. The computer-implemented includes receiving a plurality of first values in a first hardware register from a first input stream in ascending order, receiving a plurality of second values in a second hardware register from a second input stream in descending order, performing a bitonic merge operation on the first and second values in the first and second hardware registers, and reversing comparison operations performed by one or more comparators in the bitonic merge operation, outputs of the one or more comparators being loaded into the second hardware register so that output values of the second hardware register are arranged in descending order and placed into an output stream.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: In general, techniques are described for communicating state information in distribute operating system. A network device comprises a first hardware node and a second hardware node. The first hardware node may execute a first instance of a distributed operating system, and maintain a first data structure that stores a plurality of objects defining a portion of state information. The second hardware node may execute a second instance of the distributed operating system, and maintain a second data structure that stores synchronized versions of the plurality of objects. The first hardware node may further receive updated state information, update the first data structure to include the updated state information, and synchronize the updated first data structure with the second data structure. The second hardware node may synchronize the second data structure with the updated first data structure.

Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.

Abstract: A multiprocessor device includes external memory, processors, a memory aggregate unit, register memory, a multiplexer, and an overall control unit. The memory aggregate unit aggregates memory accesses of the processors. The register memory is prepared by a number equal to the product of the number of registers managed by the processors and the maximum number of processes of the processors. The multiplexer accesses the register memory according to a command given against register access of the processors. The overall control unit extracts a parameter from the command and provides the parameter to the processors and multiplexer, and controls them, as well as has a given number of processes consecutively processed using the same command while having addressing for the register memory changed by the processors, and when the given number of processes ends, has the command switched to a next command and processing repeated for a given number of processes.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a multi-party secure logistic regression model (SLRM). One of the methods includes receiving, at a plurality of secure computation nodes (SCNs), a plurality of random numbers from a random number provider; encrypting, at each SCN, data stored at the SCN using the received random numbers; iteratively updating a secure logistic regression model (SLRM) by using the encrypted data from each SCN; and after iteratively updating the SLRM, outputting a result of the SLRM, wherein the result is configured to enable a service to be performed by each SCN.

Abstract: This application discloses tools and mechanisms to convert a program from a sequentially-executable format into a parallel-executable format, and then modify the program in the parallel-executable format to either allow compilation for parallel execution or to speed-up the parallel execution by an accelerated processing unit. The tools and mechanisms can identify various features of the program, such as recursive calls, search loops, inline function calls, uncompressed data structures, memory utilization, and inter-dependent kernel instances. The tools and mechanisms can modify the program to replace or otherwise augment the identified features, which can allow the modified program to be compiled for parallel execution, or speed-up the parallel execution by an accelerated processing unit.

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.

Abstract: Systems, apparatuses and methods for utilizing enhanced macro scalar predicate operations which take enhanced predicate operands that designate the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition of the instruction. This enables additional parallelism when processing smaller-sized data. The instruction performs the requested operation on the elements specified by the enhanced control predicate, assuming an element-width also specified by the enhanced control predicate, and returns the result as an enhanced predicate of the same element width.

Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a source packed data operand to include Morton coordinates, a dimensionality of a multi-dimensional space having points that the Morton coordinates are to be mapped to, a given dimension of the multi-dimensional space, and a destination. The execution unit is coupled with the decode unit. The execution unit, in response to the decode unit decoding the instruction, stores a result packed data operand in the destination. The result operand is to include Morton coordinates that are each to correspond to a different one of the Morton coordinates of the source operand. The Morton coordinates of the result operand are to be mapped to points in the multi-dimensional space that differ from the points that the corresponding Morton coordinates of the source operand are to be mapped to by a fixed change in the given dimension.

Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.

Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline includes an instruction fetch stage to fetch an instruction. The instruction identifies an input vector operand whose input elements specify one or the other of two states. The instruction execution pipeline also includes an instruction decoder to decode the instruction. The instruction execution pipeline also includes a functional unit to execute the instruction and provide a resultant output vector. The functional unit includes logic circuitry to produce an element in a specific element position of the resultant output vector by performing an operation on a value derived from a base value using a stride in response to one but not the other of the two states being present in a corresponding element position of the input vector operand.

Abstract: An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits coupled to network circuitry to implement a vector sorting tree for a vector sorting instruction. Each of the compare-and-exchange circuits has a respective comparison circuit that compares a pair of inputs. Each of the compare-and-exchange circuits have a same sided first output for presenting a higher of the two inputs and a same sided second output for presenting a lower of the two inputs, said comparison circuit to also support said functional unit's execution of a prefix min and/or prefix add instruction.

Abstract: A processor of an aspect includes a plurality of packed data registers. The processor also includes a unit coupled with the packed data registers. The unit is operable, in response to a limited range vector memory access instruction. The instruction is to indicate a source packed memory indices, which is to have a plurality of packed memory indices, which are to be selected from 8-bit memory indices and 16-bit memory indices. The unit is operable to access memory locations, in only a limited range of a memory, in response to the limited range vector memory access instruction. Other processors are disclosed, as are methods, systems, and instructions.

Abstract: A method and a system for determining a product vector for computation of a Euclidean distance for performing dynamic time warping of a test signal and a template signal are provided. Low-rank factorized vectors for the test signal are determined. The low-rank factorized vectors are processed along with the template signal for determining the product vector. The product vector is thereafter usable for the determination of a Euclidean distance between the test signal and the template signal, and for performing dynamic time warping of the test signal and the template signal.

Abstract: A method and a system for determining a product vector for computation of a Euclidean distance for performing Dynamic Time Warping of a test signal and a template signal are provided. Low-rank factorized vectors are determined for the template signal. The low-rank factorized vectors are processed along with the test signal for determining the product vector. The product vector is thereafter usable for the determination of a Euclidean distance between the test signal and the template signal, and for performing dynamic time warping of the test signal and the template signal.

Abstract: Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

Abstract: A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the speed of the CORDIC function compared to prior-art CORDIC implementations.

Abstract: A method and an apparatus are described which determine at least one output value based on at least one input value. The input value is provided to a processing unit, wherein a combination of intermediate values is iteratively calculated. Each intermediate value is calculated during an iteration such that the intermediate value for each iteration is buffered, using a buffer storage. Based on the combination of the buffered intermediate values a storage is accessed, the storage storing a plurality of first output values, each first output value associated with a respective combination of the buffered intermediate values, so that the first output value is output.

Abstract: Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector to yield a rotated vector and to store rotation directions of the series of successive rotations, and at least one lookup table operable to yield an angle of rotation based on the rotation directions.

Abstract: An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N-1 reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals.

Abstract: Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.

Abstract: Parameterization of a CORDIC algorithm for providing a CORDIC engine is described. An aspect of the invention is a method in a digital processing system for generation of the CORDIC engine. Numbers of fractional output bits for a user-defined numerical result format are obtained. The numbers of fractional output bits are for each of a plurality of output variables associated with the CORDIC algorithm. Micro-rotations associated with each of the plurality of output variables are determined responsive to the numbers of fractional output bits. Quantizations associated with each of the plurality of output variables are determined responsive at least in part to the numbers of fractional output bits.

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract: Systems, methods, and software for determining a set of analytical or numerical polynomials that is orthonormal over circular or noncircular pupils are described. Closed-form orthonormal polynomials for circular, annular, hexagonal, elliptical, rectangular, and square pupils are derived. Such techniques can be applied to ray tracing as in the optical design and wavefront fitting from measurement as in the optical testing. These approaches can also be applied to wavefront reconstruction in adaptive optics.

Abstract: A system and method for solving a decision problem having Boolean combinations of linear and non-linear operations includes translating the non-linear real operations using a COordinate Rotation DIgital Computer (CORDIC) method programmed on a computer device into linear operations maintaining a given accuracy. Linear and translated linear operations are combined into a formula. Satisfiability of the formula is solved using a decision procedure for Boolean combinations of linear operations over integers and reals.

Abstract: Embodiments of present invention disclose a system and a method for determining a result of a function applied to a first vector and a second vector, wherein the function is a normalized sum-type function. The first vector is stored at a first processor, and the second vector is stored at a second processor. The system and the method determine a joint empirical probability distribution (JEPD) of the first vector and the second vector using a secure multi-party computation. The function is determined as a normalized summation of products of values of the JEPD with corresponding values of the function.

Abstract: The invention concerns a method and apparatus (28) for determining an angle (9) by means of a resolver (3). In the method, an excitation signal (29) of constant frequency is supplied to the resolver (3), the resolver response signals (13, 14) are measured, successive (16) measurements of each response signal are stored into a sample buffer (5), FIR filtering (10) is computed for the response signal values (16) present in the sample buffer (5) at the instant of computation, the computation points (23, 24) and the set of computation result values (18) corresponding to these points are stored in memory, at least two sets of values (18, 19) of computation results are compared to each other and of these the value set Amax (19) which contains the highest computation result as an unsigned value is selected, and FIR filtering (10) is repeatedly computed at the computation points (25, 26) corresponding to value set Amax (19).

Abstract: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

Abstract: A method of computing a vector angle by using a CORDIC and an electronic apparatus using the same are disclosed. The electronic apparatus mainly includes a phase error detector, a loop filter, a small-area iteration LUT module and a phase compensation circuit. The phase error can be locked by using the error function in the phase error detector, and even the phase error can be locked to the minimum so that the error oscillates up-and-down about the zero level. The first transfer function in the loop filter can determine the baseband and the converging speed. Moreover, if the shifting technique is used, the operation of the first transfer function is speeded up. By using a phase-locking loop in association with looking up the above-mentioned LUT, the method is able to get fast converging and higher accuracy for the computation.

Abstract: Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.

Abstract: This disclosure concerns a waveform corrector comprising a first portion calculating an offset value of an intermediate value between a maximum value and a minimum value of a signal with respect to a reference value; a second portion calculating an actual amplitude of the signal by subtracting the offset value from the maximum value or the minimum value; a third portion generating a first correction signal by subtracting the offset value from the digital signal; a fourth portion subtracting a value obtained by shifting a figure of the actual amplitude from the actual amplitude so that the actual amplitude converges into a reference amplitude; and a fifth portion subtracting a value obtained by shifting the first correction signal by an amount identical to a shift amount of the actual amplitude from the first correction signal so that the first correction signal converges into a second correction signal.

Abstract: This invention relates to a short message format that captures useful information embedded in a data vector of sequence of symbols or numbers. The data vector may represent many different forms of information generated by various electronic and information systems. This short message format is particularly useful when bandwidth limited communication links are used to transmit a data set that can be represented as a set of data vectors that is true for essentially all types of data. Described herein is an algorithm formulated to be useful for data communication problems associated with bandwidth limited communication links.

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract: Embodiments of present invention disclose a system and a method for determining a result of a function applied to a first vector and a second vector, wherein the function is a normalized sum-type function. The first vector is stored at a first processor, and the second vector is stored at a second processor. The system and the method determine a joint empirical probability distribution (JEPD) of the first vector and the second vector using a secure multi-party computation. The function is determined as a normalized summation of products of values of the JEPD with corresponding values of the function.

Abstract: Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.

Abstract: A Coordinate Rotation Digital Computer (CORDIC) circuit capable of performing precise vector rotation, including a pre-rotation stage configured to selectively rotate an input vector by ±90 degrees and to produce a pre-rotated vector. A first stage is configured to perform a first set of iterative CORDIC calculations on the pre-rotated vector and to produce a first rotated vector and a remaining rotation value. A second stage configured to perform a second set of iterative CORDIC calculations on the first rotated vector and to produce a second rotated vector, the second rotated vector corresponding to the input vector.

Abstract: A phase calculation apparatus using a binary search is provided. The phase calculation apparatus includes a quarter surface preprocessor determining the bigger one between an absolute value of I component data and an absolute value of Q component data as horizontal component data and the smaller one as perpendicular component data, and detecting information on a phase region indicating an mth (m=1 to 8) phase region (the mth phase region is between (m?1) ?/4 and m ?/4 in which the I/Q component data are located; a phase representative value detector detecting phase representative values x corresponding to the horizontal component data and the perpendicular component data; and a quarter surface postprocessor calculating phase values of the I/Q component data based on the detected information about the phase region and the detected phase representative values x. The phase can be calculated using a limited memory, low complexity of calculation and regardless of the number of bits of I/Q component data.

Abstract: A communications system for reducing bit errors in a received data sequence provides a method for generating candidate code-word sequences for evaluation by a CRC decoder. The system may determine a most-likely received sequence using the probable code-word list of candidate sequences. The number of candidate sequences may be reduced using computational complexity reduction methods. A communications device also provides a candidate sequence generator for use with a CRC decoder to determine a most-likely received sequence and to reduce bit errors in a received sequence.

Abstract: Disclosed herein is a system and method for extracting users of similar interests between various types of web servers. The system includes a user profile vector creation unit, a user similarity calculation unit, and a similar user extraction unit. The user profile vector creation unit collects tag data, performs standardization calculation on the degree of importance of each of one or more tags, and creates user profile vectors for respective users. The user similarity calculation unit calculates user similarity using the user profile vectors of the respective users created through the user profile vector creation unit. The similar user extraction unit extracts users of similar interests using the value of the user similarity calculated through the user similarity calculation unit.

Abstract: A method of computing a vector angle by using a CORDIC and an electronic apparatus using the same are disclosed. The electronic apparatus mainly includes a phase error detector, a loop filter, a small-area iteration LUT module and a phase compensation circuit. The phase error can be locked by using the error function in the phase error detector, and even the phase error can be locked to the minimum so that the error oscillates up-and-down about the zero level. The first transfer function in the loop filter can determine the baseband and the converging speed. Moreover, if the shifting technique is used, the operation of the first transfer function is speeded up. By using a phase-locking loop in association with looking up the above-mentioned LUT, the method is able to get fast converging and higher accuracy for the computation.

Abstract: Directed graph embedding is described. In one implementation, a system explores the link structure of a directed graph and embeds the vertices of the directed graph into a vector space while preserving affinities that are present among vertices of the directed graph. Such an embedded vector space facilitates general data analysis of the information in the directed graph. Optimal embedding can be achieved by measuring local affinities among vertices via transition probabilities between the vertices, based on a stationary distribution of Markov random walks through the directed graph. For classifying linked web pages represented by a directed graph, the system can train a support vector machine (SVM) classifier, which can operate in a user-selectable number of dimensions.