Solving Equation Patents (Class 708/446)
  • Patent number: 12572618
    Abstract: Embodiments relate to a system for solving partial differential equations. The system receives problem packages corresponding to problems to be solved, each comprising at least a partial differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using an array of point processors. Each point processor comprises a series of tiles, each having a computational element and a router, and are configured and connected based on a discretized form of the partial differential equation, to allow each point processor to receive a node of the domain and generate a value for the node for a next time step. Because all the data and computational requirements of the point processors are determined at compile time, no dynamic scheduling needs to be performed, allowing for more efficient usage of computational resources.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 10, 2026
    Assignee: Vorticity Inc.
    Inventors: Chirath Neranjena Thouppuarachchi, Ross Geoffrey Daly
  • Patent number: 12554894
    Abstract: A multi-domain masked AND gate includes inner-domain calculations, re-sharing, register stage, cross-domain calculations, and compression. The inner-domain multiplication and the re-sharing are calculated prior to storing the re-shared variables in the register stage. Thus, the inputs to the cross-domain multiplication and the compression are performed on variables that have been refreshed by additional randomness. This AND gate does not need statistically independent inputs, is secure in the probing model even in the presence of glitches, also known as the robust probing model. A two-domain input and two domain output AND gate can be implemented using six (6) registers, four (4) two input logical AND gates, and eight (8) exclusive-OR (XOR) gates. The AND gate may also be used to implement an AES S-box that has two (2) register stages and takes two (2) clock cycles per computation.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: February 17, 2026
    Assignee: CRYPTOGRAPHY RESEARCH, INC.
    Inventors: Michael Hutter, Victor Manuel Arribas Abril
  • Patent number: 12548675
    Abstract: This disclosure describes techniques for providing diagnosis and treatment recommendations using quantum computing. For example, a quantum computing device encodes diagnosis-relevant information of a patient as one or more patient diagnosis qubits. The quantum computing device implements a first quantum search algorithm using the patient diagnosis qubits to determine a diagnosis likelihood for each condition of a plurality of conditions. The quantum computing device further encodes the diagnosis data and treatment-relevant information of the patient as one or more patient treatment qubits. The quantum computing device implements a second quantum search algorithm using the treatment-relevant information of the patient to determine one or more treatment recommendations for the patient.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 10, 2026
    Assignee: Optum Services (Ireland) Limited
    Inventors: Lisa E. Walsh, Vicente Rubén Del Pino Ruiz, Paul J. Godden, Vikas Raj Paidimukkala
  • Patent number: 12541566
    Abstract: A system and method for estimating values of an operator, such as energy levels of a Hamiltonian, is disclosed. The estimation is performed in a way such that the runtime of performing the estimation is independent of a complexity of the operator, e.g., a number of terms in the Hamiltonian. Also, errors can be statistically suppressed by performing additional sampling, due to a lack of biased error in the estimator. Additionally, samples may be tested using only a single ancilla qubit.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 3, 2026
    Assignee: Amazon Technologies, Inc
    Inventors: Earl Terence Campbell, Mario Andrea Berta, Kianna Wan
  • Patent number: 12393641
    Abstract: Embodiments relate to a computing system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain, and to select a solver of a plurality of solvers, based upon availability of each of the plurality of solvers. A dispatch computer selects a solver by monitoring the plurality of solvers, and responsive to a solver becoming available, determines if a received problem package having at least a threshold priority level can be solved by the solver. Otherwise, the dispatch computer generates a plurality of solver scenarios each reflecting a permutation of received problem packages assigned to solvers estimated to become available within a threshold period of time, and assigns the problem packages in accordance with a solver scenario having a highest utilization score.
    Type: Grant
    Filed: January 12, 2024
    Date of Patent: August 19, 2025
    Assignee: Vorticity Inc.
    Inventor: Chirath Neranjena Thouppuarachchi
  • Patent number: 12393874
    Abstract: Embodiments of the present invention disclose a data processing apparatus. The apparatus is configured to: after calculating a set of gradient information of each parameter by using a sample data subset, delete the sample data subset, read a next sample data subset, calculate another set of gradient information of each parameter by using the next sample data subset, and accumulate a plurality of sets of calculated gradient information of each parameter, to obtain an update gradient of each parameter.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: August 19, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Changzheng Zhang, Xiaolong Bai, Dandan Tu
  • Patent number: 12299497
    Abstract: Various embodiments are provided for dynamically factoring and composing workflows in a computing environment by one or more processors in a computing system. Subgraphs (e.g., blocks) of workflows stored in a workflow library may be identified. The subgraphs may be functional blocks such as, for example, the functional blocks may perform a logical task. Similarities and relationships may be identified between one or more of the blocks of one or more workflows. One or more blocks may be suggested for use in workflow opportunities of target workflows based on the identified associated similarities and relationships.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: May 13, 2025
    Assignee: International Business Machines Corporation
    Inventors: Michael Johnston, Vasileios Vasileiadis
  • Patent number: 12242924
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate mapping conditional execution logic to different quantum computing resources are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a compiler component that maps a logical reference to a quantum bit data structure in an instruction, to a first engine component, and a deployment component that deploys the first engine component to a first block controller component operatively connected to a first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instruction.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 4, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Joseph Ruedinger, Thomas Arab Alexander, David C. Mckay
  • Patent number: 12093663
    Abstract: A system and methods for using carry chain logic, a product term splitting methodology, and a new Sum-of-Products (SOP) output multiplexer (mux) equation to build faster and larger sorting blocks.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: September 17, 2024
    Assignee: UNM RAINFOREST INNOVATIONS
    Inventors: Robert Bernard Kent, Marios Stephanou Pattichis
  • Patent number: 12000760
    Abstract: This invention relates to a resonant frequency vibrational test and a method of subjecting a component to such a resonant frequency vibrational test.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 4, 2024
    Assignee: Universite De Mons
    Inventors: Lassaad Ben Fekih, Olivier Verlinden, Georges Kouroussis
  • Patent number: 11921813
    Abstract: Embodiments relate to a computing system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain, and to select a solver of a plurality of solvers, based upon availability of each of the plurality of solvers. A dispatch computer selects a solver by monitoring the plurality of solvers, and responsive to a solver becoming available, determines if a received problem package having at least a threshold priority level can be solved by the solver. Otherwise, the dispatch computer generates a plurality of solver scenarios each reflecting a permutation of received problem packages assigned to solvers estimated to become available within a threshold period of time, and assigns the problem packages in accordance with a solver scenario having a highest utilization score.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: March 5, 2024
    Assignee: VORTICITY INC.
    Inventor: Chirath Neranjena Thouppuarachchi
  • Patent number: 11907682
    Abstract: This device comprises a fast sampler comprising: a truncated table associating with truncated random numbers rmsb coded on Nmsb bits, the only sample k for which, whatever the number rlsb belonging to the interval [0; 2Nr?Nmsb?1], the following condition is met: F(k?1)<(rmsb, rlsb)?F(k), where: (rmsb, rlsb) is the binary number coded on Nr bits and the Nmsb most significant bits of which are equal to the truncated random number rmsb and the (Nr?Nmsb) least significant bits of which are equal to the number rlsb, Nmsb is an integer number lower than Nr, a module for searching for a received truncated random number rmsb in the truncated table, and able to transmit the sample k, associated, by the truncated table, with the received truncated random number rmsb, by way of random number drawn according to the probability distribution ?.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 20, 2024
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Thomas Hiscock
  • Patent number: 11748707
    Abstract: Methods, systems, and apparatus for solving cost optimization problems. In one aspect, a method includes receiving data representing a bill of materials (BOM) optimization problem, the BOM optimization problem comprising a task of determining a BOM recommendation that satisfies one or more constraints, wherein each constraint comprises one or more constraint variables and a constraint constant; generating, based on the data representing the BOM optimization problem, a quadratic unconstrained binary optimization (QUBO) formulation, wherein the QUBO formulation comprises i) for each constraint variable in the one or more constraints, a binary representation of the constraint variable and ii) a first parameter that depends on a difference between a respective constraint constant and the binary representations of the constraint variables; and obtaining data representing a solution to the BOM optimization problem from a quantum computing resource.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: September 5, 2023
    Assignee: Accenture Global Solutions Limited
    Inventors: Rodrigo Morimoto Suguiura, Jair Antunes De Carvalho, Jr.
  • Patent number: 11693916
    Abstract: According to an aspect of an embodiment, operations include receiving a Quadratic Integer Programming (QIP) problem including an objective function and a set of constraints on integer variables associated with the objective function. The operations further include obtaining an approximation of the QIP problem by relaxing the QIP problem and generating an approximate solution by solving the obtained approximation. The operations further include generating a Quadratic Unconstrained Binary Optimization (QUBO) formulation of the QIP problem based on the generated approximate solution and the received QIP problem. The operations further include submitting the generated QUBO formulation to an optimization solver machine and receiving a solution of the submitted QUBO formulation from the optimization solver machine. The operations further include publishing an integral solution of the received QIP problem on a user device based on the received solution.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: July 4, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Avradip Mandal, Arnab Roy, Sarvagya Upadhyay, Hayato Ushijima-Mwesigwa
  • Patent number: 11620564
    Abstract: Method, apparatus and product for modeling of quantum circuits and usages thereof. A method comprises obtaining a model of a quantum circuit that comprises a set of decision variables, corresponding domains, and constraints, wherein the set of decision variables comprise gate assignment decision variables that define an assignment of a gate to a qubit in a cycle in the quantum circuit. The method comprises automatically determining a set of valuations for the set of decision variables. The set of valuations are selected from the corresponding domains and satisfy the constraints. Based on the set of valuations the quantum circuit is synthesized.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: April 4, 2023
    Assignee: CLASSIQ TECHNOLOGIES LTD.
    Inventors: Yehuda Naveh, Amir Naveh, Nir Minerbi, Ofek Kirzner, Adam Goldfeld, Shmuel Ur
  • Patent number: 11562239
    Abstract: A computer-implemented method for computing node embeddings of a sparse graph that is an input of a sparse graph neural network is described. Each node embedding corresponds to a respective node of the sparse graph and represents feature information of the respective node and a plurality of neighboring nodes of the respective node.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 24, 2023
    Assignee: Google LLC
    Inventors: Daniel S. Tarlow, Matej Balog, Bart van Merrienboer, Yujia Li, Subhodeep Moitra
  • Patent number: 11537995
    Abstract: A method, computer software product and system for solving cyclic scheduling problems. Specifically, the present disclosure significantly improves the method in a previous patent (H. K. Alfares, 2011, “Cyclic Combinatorial Method and System”, U.S. Pat. No. 8,046,316), by eliminating a time-consuming combinatorial procedure. A procedure is described which significantly decreases the number of iterations, and hence computational time and cost. The processes of the present disclosure have many applications in cyclic workforce scheduling, cyclic transportation system scheduling, cyclic scheduling of data packet transmitting as applied to networks having a plurality of nodes and cyclic production scheduling.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 27, 2022
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Hesham K. Alfares
  • Patent number: 11494462
    Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 8, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato Goto, Kosuke Tatsumura
  • Patent number: 11487699
    Abstract: Systems, apparatuses, and methods related to bit string accumulation in memory array periphery are described. Control circuitry (e.g., a processing device) may be utilized to control performance of operations using bit strings within a memory device. Results of the operations may be accumulated in circuitry peripheral to a memory array of the memory device. For instance, a method for bit string accumulation in memory array periphery can include performing a first operation using a first bit string and a second bit string and retrieving a third bit string from a memory array or a storage location located in the periphery of the memory array. The method can further include performing a second operation using the result of the first operation and the third bit string and storing the result of the second operation in the storage location located in the periphery of the memory array.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Vijay S. Ramesh
  • Patent number: 11403070
    Abstract: Embodiments relate to a system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using a systolic array comprising hardware for solving the particular type of the differential equation. The systolic array processes each node to generate a node for a subsequent time-step using a sub-array comprising a plurality of branches, each branch comprising a respective set of arithmetic units arranged in accordance with a corresponding term of the discretized form of the differential equation, and an aggregator configured to aggregate the corresponding terms from each branch to generate node data for the subsequent time-step.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 2, 2022
    Assignee: Vorticity Inc.
    Inventor: Chirath Neranjena Thouppuarachchi
  • Patent number: 11288589
    Abstract: Method, apparatus and product for modeling of quantum circuits and usages thereof. A method includes obtaining a model of a quantum circuit that comprises a set of decision variables, corresponding domains, and constraints, wherein the set of decision variables comprise gate assignment decision variables that define an assignment of a gate to a qubit in a cycle in the quantum circuit. The method includes automatically determining a set of valuations for the set of decision variables. The set of valuations are selected from the corresponding domains and satisfy the constraints. Based on the set of valuations the quantum circuit is synthesized.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: March 29, 2022
    Assignee: CLASSIQ TECHNOLOGIES LTD.
    Inventors: Yehuda Naveh, Amir Naveh, Nir Minerbi, Ofek Kirzner, Adam Goldfeld, Shmuel Ur
  • Patent number: 11144017
    Abstract: A system and approach for storing factors in a quadratic programming solver of an embedded model predictive control platform. The solver may be connected to an optimization model which may be connected to a factorization module. The factorization module may incorporate a memory containing saved factors that may be connected to a factor search mechanism to find a nearest stored factor in the memory. A factor update unit may be connected to the factor search mechanism to obtain the nearest stored factor to perform a factor update. The factorization module may provide variable ordering to reduce a number of factors that need to be stored to permit the factors to be updated at zero floating point operations per unit of time.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 12, 2021
    Assignee: Garrett Transportation I, Inc.
    Inventor: Ondrej Santin
  • Patent number: 11093817
    Abstract: An information processing device includes, a memory, and a processor coupled to the memory and the processor configured to, acquire a neural network, divide the neural network into divided neural networks, identify, based on input-output characteristics of the divided neural networks, parameters of each of polynomial neural networks corresponding to each of the divided neural networks, and output another neural network generated by linking the identified polynomial neural networks.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 17, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Tanabe
  • Patent number: 10997271
    Abstract: To improve efficiency for solving a system of equations, art equation solver uses variable reduction techniques to reduce a number of variables to be solved. The equation solver identifies derived variables and eliminates them from the system of equations. The equation solver considers the remaining variables to be primitive variables. The primitive variables may be rewritten into a representation of the system of equations or into a set of equations that may be used to solve for values of the primitive variables. The equation solver solves for values of the primitive variables. Prior to solving or during solving iterations, the equation solver may apply storage policies to further reduce the number of variables to be solved. The storage policies indicate parameters and techniques for eliminating primitive variables to be solved, such as primitive variables that are insignificant (i.e., have little effect on a solution for the system of equations).
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 4, 2021
    Assignee: Halliburton Energy Services, Inc.
    Inventor: Dinesh Ananda Shetty
  • Patent number: 10990072
    Abstract: Systems and methods are described herein for maintaining stability of a power grid by providing a continuous power system data stream. Power system data including one or more data packets is monitored to identify reliability of data transmission. A predicted data packet is continually generated, characterizing predicted power system data of the power grid based on filtering of the one or more past and most recent non-missing and reliable data packets. A substitution factor of the one or more data packets is determined. The predicted data packet is selectively substituted in place of the one or more data packets based on the substitution factor.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 27, 2021
    Assignee: PXiSE Energy Solutions, LLC
    Inventors: Sai Akhil Reddy Konakalla, Raymond A. de Callafon
  • Patent number: 10951326
    Abstract: Described is a method of setting up a plurality of quantum communications links, forming a quantum network providing provably secure communications and internet services over intercontinental distances without requiring direct line of sight communication or the intermediate use of the entanglement resource of satellites. Also described is a quantum communicator device for use in this method. Two or more quantum memory units are disposed at a first location, an entangled link is set up between at least two of the quantum memory units, at least one of the quantum memory units sharing in the entangled link is physically transported to a second location. The quantum communicator device comprises communications nodes, an optical interface to set up entanglement to other devices and storage nodes, each node in the form of a quantum memory unit capable of storing quantum information for a desired length of time, i.e. weeks or longer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Turing Inc.
    Inventor: Michele Reilly
  • Patent number: 10915075
    Abstract: A device for controlling an industrial system comprises an input block and a reference value predicter. The reference value predicter includes a disturbance predicter, a state predicter, and a model parameter predicter. A model updater updates the model of the industrial system based on the predicted state and the predicted parameters. A one-prediction-step calculator of the reference value predicter calculates a prediction step based on the predicted disturbances and the model of the system. The device further includes a matrix updater and a linear solver that includes a memory structure such that each row of Jacobian and gradient matrices may be processed in parallel, a pivot search block that determines a maximum element in a column of the Jacobian and gradient matrices, and a pivot row reading block. Moreover, the device further includes a solution updater that updates the solution for an iteration step and controls the iteration process and an output block that sends a solution to the industrial system.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: February 9, 2021
    Assignee: UNIVERSITY OF DAYTON
    Inventors: Zhenhua Jiang, Seyed Ataollah Raziei
  • Patent number: 10860679
    Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Goto, Kosuke Tatsumura
  • Patent number: 10762101
    Abstract: In one example in accordance with the present disclosure, a system comprises a computing node. The computing node comprises: a memory, and a processor to: execute a database in the memory, and invoke, with the database, singular value decomposition (SVD) on a data set. To invoke SVD, the processor may sparsify, with the database, the data set to produce a sparse data set, iteratively decompose, with the database, the data set to produce a set of eigenvalues, solve, with the database a linear system to produce a set of eigenvectors, and multiply, with the database, the eigenvectors with the data set to produce a data set of reduced dimension.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 1, 2020
    Assignee: MICRO FOCUS LLC
    Inventors: Meichun Hsu, Lakshminarayan Choudur
  • Patent number: 10746838
    Abstract: A wideband signal is enhanced or suppressed to the same extent at each frequency without increasing the size of an overall sensor array. To achieve this, there is provided a signal processing apparatus including a direction estimator that obtains a direction of arrival of a signal for signals received from a plurality of sensors and each containing a target signal and noise, a first gain calculator that calculates a first gain using the direction of arrival of the signal, an integrator that obtains an integrated signal by integrating the signals received from the plurality of sensors, and a multiplier that multiplies the first gain by the integrated signal.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 18, 2020
    Assignee: NEC CORPORATION
    Inventors: Akihiko Sugiyama, Ryoji Miyahara
  • Patent number: 10733765
    Abstract: The systems and methods described herein can pre-process a blendshape matrix via a global clusterization process and a local clusterization process. The pre-processing can cause the blendshape matrix to be divided into multiple blocks. The techniques can further apply a matrix compression technique to each block of the blendshape matrix to generate a compression result. The matrix compression technique can comprise a matrix approximation step, an accuracy verification step, and a recursive compression step. The compression result for each block may be combined to generate a compressed blendshape matrix for rendering a virtual entity.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 4, 2020
    Assignee: ELECTRONIC ARTS INC.
    Inventor: Dmitry Andreevich Andreev
  • Patent number: 10719354
    Abstract: A system for scheduling the execution of container workloads from a series of applications and a series of containers of each application. The system includes a processor and a non-transitory computer-readable storage medium having instructions stored thereon, which, when executed by the processor, cause the system to calculate a conflict penalty matrix including a conflict penalty for each potential combination of container workloads of the plurality of containers, and calculate a minimum total conflict penalty of the container workloads and a number of workload batches for executing the container workloads. The number of workload batches is associated with the minimum total conflict penalty. The instructions, when executed by the processor, further cause the system to assign the container workloads to the workload batches based on the minimum total conflict penalty and the number of the workload batches.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Janki Sharadkumar Bhimani, Anand Subramanian, Jingpei Yang, Vijay Balakrishnan
  • Patent number: 10713332
    Abstract: Systems and methods for finding the solution to a system of linear equations include use of a reconfigurable hardware based real-time computational solver. The solver apparatus solves systems of linear equations by applying Gauss-Jordan Elimination to an augmented matrix in parallel on reconfigurable hardware consisting of parallel data processing modules, reusable memory blocks and flexible control logic units, which can greatly accelerate the solution procedure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: University of Dayton
    Inventors: Zhenhua Jiang, Seyed Ataollah Raziei
  • Patent number: 10691772
    Abstract: A method includes storing a sparse triangular matrix as a compressed sparse row (CSR) dataset. For each factor of a plurality of factors in a first vector, a value of the factor is calculated by identifying for the factor a set of one or more antecedent factors in the first vector, where the value of the factor is dependent on each of the one or more antecedent factors. In response to a completion array indicating that all of the one or more antecedent factor values are solved, the value of the factor is calculated based on one or more elements in a row of the matrix and a product value corresponding to the row. In the completion array, a first completion flag for the factor is asserted, indicating that the factor is solved.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 23, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Joseph Lee Greathouse
  • Patent number: 10412767
    Abstract: A method for operating a user equipment (UE) in a millimeter wave (mmWave) communications system includes receiving a first wide beam beam-formed reference signal from a mmWave evolved NodeB (eNB) during an initial time interval, the first wide beam beam-formed reference signal carrying timing information, detecting a wide beam boundary between the first wide beam beam-formed reference signal and a second wide beam beam-formed reference signal during a subsequent time interval, wherein both the first wide beam beam-formed reference signal and the second wide beam beam-formed reference signal are rotated by a narrow beam beam-width during each intermediate time interval between the initial time interval and the subsequent time interval, and informing the mmWave eNB of an indication that the UE detected the wide beam boundary during the subsequent time interval, the indication being used to assign a narrow beam direction to the UE.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 10, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Bin Liu, Richard Stirling-Gallacher
  • Patent number: 10235341
    Abstract: Method for solving the decomposition-coordination calculation based on Block Bordered Diagonal Form (BBDF) model by using data center. During the solving process, partitioning the electric power system network by using the existing network partitioning method to achieve the grid partition, and setting the parameters of virtual memories firstly, thus to establish the bin-packing model with the priority of energy efficiency; and then, setting each calculating step of the decomposition-coordination calculation based on BBDF as a task. Through the manners that servers host VMs and VMs map tasks, the decomposition-coordination algorithm can be executed in data center, and the running time and energy consumption of data center can be calculated. The calculating time of decomposition-coordination algorithm is shortened and the energy consumption in data center.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 19, 2019
    Assignee: Tianjin University
    Inventors: Ting Yang, Wenping Xiang, Yingmin Feng, Haibo Pen, Mingyu Xu, Jinkuo You, Hongtao Wang
  • Patent number: 10096133
    Abstract: The systems and methods described herein can pre-process a blendshape matrix via a global clusterization process and a local clusterization process. The pre-processing can cause the blendshape matrix to be divided into multiple blocks. The techniques can further apply a matrix compression technique to each block of the blendshape matrix to generate a compression result. The matrix compression technique can comprise a matrix approximation step, an accuracy verification step, and a recursive compression step. The compression result for each block may be combined to generate a compressed blendshape matrix for rendering a virtual entity.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 9, 2018
    Assignee: ELECTRONIC ARTS INC.
    Inventor: Dmitry Andreevich Andreev
  • Patent number: 9941740
    Abstract: Systems, apparatus and methods for quantifying and identifying diversion of electrical energy are provided. Bypass and tap diversions may be identified in an electric utility power distribution inventory zone having both bypass and tap diversions. Bypass diversion factors for consumer nodes in an inventory zone are determined by finding a solution to a system of load balance equations having slack variables representing aggregate tap loads for the inventory zone and in which consumer load profile data is scaled by the bypass diversion factors, which solution minimizes an objective function whose value is positively related to the sum of the slack variables representing the aggregate tap loads.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 10, 2018
    Assignee: MBH CONSULTING LTD.
    Inventor: Michael Brent Hughes
  • Patent number: 9779374
    Abstract: The method includes determining an assignment completion time distribution based on a task set defining a project, determining a project completion time distribution based on the assignment completion time distribution and the task set, determining a project cost based on assignments of the task set, and generating a list of project task assignments based on the project cost and the project completion time distribution.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 3, 2017
    Assignee: SAP SE
    Inventors: Tianyu Luwang, Wen-Syan Li
  • Patent number: 9734262
    Abstract: A query answer engine converts a query and answers into a non-natural language forming units that correspond to words, symbols, numbers and spaces and combinations of the above, and establishes the contextual meaning of the units utilizing read, recognize and relate processes to populate a query matrix and an answer matrix with 3-valued points corresponding to the read, recognize and relate values of a unit. The two matrices are cross correlated to yield a robust answer to a query taking into account context. The conversion of text to units uses contextual meaning parametric tables, databases, libraries, rules and an engine for determining the focal point of a query or an answer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: August 15, 2017
    Inventor: Patrick Delefevre
  • Patent number: 9734144
    Abstract: In some examples, a computing system may access multiple information files, generate term-passage matrix data based on the multiple information files, and decompose the term-passage matrix data to generate a reduced-dimensional semantic space, which may be used for information retrieval.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: August 15, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Mihai Dasc{hacek over (a)}lu, David Walter Ash
  • Patent number: 9600446
    Abstract: A preconditioner processor and a method of computing a preconditioning matrix. In one embodiment, the preconditioner processor has parallel computing pipelines including: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an incomplete lower triangle, upper triangle factorization (ILU) computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning matrix, and (2b) compute non-zero elements of the ILU preconditioning matrix according to the sparsity pattern, and (3) a memory communicably couplable to the parallel computing pipelines and configured to store the ILU preconditioning matrix.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 21, 2017
    Assignee: Nvidia Corporation
    Inventors: Robert Strzodka, Julien Demouth, Patrice Castonguay
  • Patent number: 9547882
    Abstract: Disclosed herein is a shared memory systems that use a combination of SBR and MRRR techniques to calculate eigenpairs for dense matrices having very large numbers of rows and columns. The disclosed system allows for the use of a highly scalable tridiagonal eigensolver. The disclosed system likewise allows for allocating a different number of threads to each of the different computational stages of the eigensolver.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 17, 2017
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Cheng Liao
  • Patent number: 9523635
    Abstract: Apparatus and methods of spectral searching that employ wavelet coefficients as the basis for the searching. The disclosed apparatus and methods employ a wavelet lifting scheme to transform spectroscopic data corresponding to an unknown pure material/mixture to a vector of wavelet coefficients, compare the wavelet coefficient vector for the unknown pure material/mixture with a library of wavelet coefficient vectors for known pure materials/mixtures, and identify the closest match to the unknown pure material/mixture based on the comparison of wavelet coefficient vectors.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: December 20, 2016
    Assignee: Rigaku Raman Technologies, Inc.
    Inventor: Scott B. Tilden
  • Patent number: 9514415
    Abstract: A target quantum circuit expressed in a first quantum gate basis may be transformed into a corresponding quantum circuit expressed in a second quantum gate basis, which may be a universal set of gates such as a V gate basis set. The target quantum circuit may be expressed as a linear combination of quantum gates. The linear combination of quantum gates may be mapped to a quaternion. The quaternion may be factorized, based at least in part on an amount of precision between the target quantum circuit and the corresponding quantum circuit expressed in the second quantum gate basis, into a sequence of quaternion factors. The sequence of quaternion factors may be mapped into a sequence of quantum gates of the second quantum gate basis, where the sequence of sequence of quantum gates is the corresponding quantum circuit.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 6, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Alexei V. Bocharov, Yuri Gurevich, Krysta M. Svore
  • Patent number: 9418045
    Abstract: Systems, apparatus and methods for quantifying and identifying diversion of electrical energy are provided. Bypass and tap diversions may be identified in an electric utility power distribution inventory zone having both bypass and tap diversions. Bypass diversion factors for consumer nodes in an inventory zone are determined by finding a solution to a system of load balance equations having slack variables representing aggregate tap loads for the inventory zone and in which consumer load profile data is scaled by the bypass diversion factors, which solution minimizes an objective function whose value is positively related to the sum of the slack variables representing the aggregate tap loads.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 16, 2016
    Assignee: MBH CONSULTING LTD.
    Inventor: Michael Brent Hughes
  • Patent number: 9143325
    Abstract: A non-linear transformation including a plurality of non-linear logical operations is masked to a second or higher order. The masking includes receiving a set of random bits, and machine-masking two or more of the plurality of non-linear logical operations with a same random bit from the set of random bits.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 22, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Zhimin Chen, Jay Scott Fuller
  • Patent number: 9128763
    Abstract: A system and computer-implemented method for generating an optimized allocation of a plurality of tasks across a plurality of processors or slots for processing or execution in a distributed computing environment. In a cloud computing environment implementing a MapReduce framework, the system and computer-implemented method may be used to schedule map or reduce tasks to processors or slots on the network such that the tasks are matched to processors or slots in a data locality aware fashion wherein the suitability of node and the characteristics of the task are accounted for using a minimum cost flow function.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 8, 2015
    Assignee: Infosys Limited
    Inventors: Santonu Sarkar, Naveen Chandra Tewari, Rajarshi Bhose
  • Patent number: 9036661
    Abstract: Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: May 19, 2015
    Assignee: ViaSat, Inc.
    Inventors: Donald W. Becker, Matthew D. Nimon, William H. Thesling
  • Patent number: 9032006
    Abstract: Apparatus and method for processing linear systems of equations and finding a n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an n×1 vector xl satisfying Alxl=bl where Al, bl are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an n×1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an n×1 update vector u. The data elements of the current solution vector x are updated such that x=x+u.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Konstantinos Bekas, Alessandro Curioni