Solving Equation Patents (Class 708/446)
  • Patent number: 10951326
    Abstract: Described is a method of setting up a plurality of quantum communications links, forming a quantum network providing provably secure communications and internet services over intercontinental distances without requiring direct line of sight communication or the intermediate use of the entanglement resource of satellites. Also described is a quantum communicator device for use in this method. Two or more quantum memory units are disposed at a first location, an entangled link is set up between at least two of the quantum memory units, at least one of the quantum memory units sharing in the entangled link is physically transported to a second location. The quantum communicator device comprises communications nodes, an optical interface to set up entanglement to other devices and storage nodes, each node in the form of a quantum memory unit capable of storing quantum information for a desired length of time, i.e. weeks or longer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Turing Inc.
    Inventor: Michele Reilly
  • Patent number: 10915075
    Abstract: A device for controlling an industrial system comprises an input block and a reference value predicter. The reference value predicter includes a disturbance predicter, a state predicter, and a model parameter predicter. A model updater updates the model of the industrial system based on the predicted state and the predicted parameters. A one-prediction-step calculator of the reference value predicter calculates a prediction step based on the predicted disturbances and the model of the system. The device further includes a matrix updater and a linear solver that includes a memory structure such that each row of Jacobian and gradient matrices may be processed in parallel, a pivot search block that determines a maximum element in a column of the Jacobian and gradient matrices, and a pivot row reading block. Moreover, the device further includes a solution updater that updates the solution for an iteration step and controls the iteration process and an output block that sends a solution to the industrial system.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: February 9, 2021
    Assignee: UNIVERSITY OF DAYTON
    Inventors: Zhenhua Jiang, Seyed Ataollah Raziei
  • Patent number: 10860679
    Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Goto, Kosuke Tatsumura
  • Patent number: 10762101
    Abstract: In one example in accordance with the present disclosure, a system comprises a computing node. The computing node comprises: a memory, and a processor to: execute a database in the memory, and invoke, with the database, singular value decomposition (SVD) on a data set. To invoke SVD, the processor may sparsify, with the database, the data set to produce a sparse data set, iteratively decompose, with the database, the data set to produce a set of eigenvalues, solve, with the database a linear system to produce a set of eigenvectors, and multiply, with the database, the eigenvectors with the data set to produce a data set of reduced dimension.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 1, 2020
    Assignee: MICRO FOCUS LLC
    Inventors: Meichun Hsu, Lakshminarayan Choudur
  • Patent number: 10746838
    Abstract: A wideband signal is enhanced or suppressed to the same extent at each frequency without increasing the size of an overall sensor array. To achieve this, there is provided a signal processing apparatus including a direction estimator that obtains a direction of arrival of a signal for signals received from a plurality of sensors and each containing a target signal and noise, a first gain calculator that calculates a first gain using the direction of arrival of the signal, an integrator that obtains an integrated signal by integrating the signals received from the plurality of sensors, and a multiplier that multiplies the first gain by the integrated signal.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 18, 2020
    Assignee: NEC CORPORATION
    Inventors: Akihiko Sugiyama, Ryoji Miyahara
  • Patent number: 10733765
    Abstract: The systems and methods described herein can pre-process a blendshape matrix via a global clusterization process and a local clusterization process. The pre-processing can cause the blendshape matrix to be divided into multiple blocks. The techniques can further apply a matrix compression technique to each block of the blendshape matrix to generate a compression result. The matrix compression technique can comprise a matrix approximation step, an accuracy verification step, and a recursive compression step. The compression result for each block may be combined to generate a compressed blendshape matrix for rendering a virtual entity.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 4, 2020
    Assignee: ELECTRONIC ARTS INC.
    Inventor: Dmitry Andreevich Andreev
  • Patent number: 10719354
    Abstract: A system for scheduling the execution of container workloads from a series of applications and a series of containers of each application. The system includes a processor and a non-transitory computer-readable storage medium having instructions stored thereon, which, when executed by the processor, cause the system to calculate a conflict penalty matrix including a conflict penalty for each potential combination of container workloads of the plurality of containers, and calculate a minimum total conflict penalty of the container workloads and a number of workload batches for executing the container workloads. The number of workload batches is associated with the minimum total conflict penalty. The instructions, when executed by the processor, further cause the system to assign the container workloads to the workload batches based on the minimum total conflict penalty and the number of the workload batches.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Janki Sharadkumar Bhimani, Anand Subramanian, Jingpei Yang, Vijay Balakrishnan
  • Patent number: 10713332
    Abstract: Systems and methods for finding the solution to a system of linear equations include use of a reconfigurable hardware based real-time computational solver. The solver apparatus solves systems of linear equations by applying Gauss-Jordan Elimination to an augmented matrix in parallel on reconfigurable hardware consisting of parallel data processing modules, reusable memory blocks and flexible control logic units, which can greatly accelerate the solution procedure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: University of Dayton
    Inventors: Zhenhua Jiang, Seyed Ataollah Raziei
  • Patent number: 10691772
    Abstract: A method includes storing a sparse triangular matrix as a compressed sparse row (CSR) dataset. For each factor of a plurality of factors in a first vector, a value of the factor is calculated by identifying for the factor a set of one or more antecedent factors in the first vector, where the value of the factor is dependent on each of the one or more antecedent factors. In response to a completion array indicating that all of the one or more antecedent factor values are solved, the value of the factor is calculated based on one or more elements in a row of the matrix and a product value corresponding to the row. In the completion array, a first completion flag for the factor is asserted, indicating that the factor is solved.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 23, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Joseph Lee Greathouse
  • Patent number: 10412767
    Abstract: A method for operating a user equipment (UE) in a millimeter wave (mmWave) communications system includes receiving a first wide beam beam-formed reference signal from a mmWave evolved NodeB (eNB) during an initial time interval, the first wide beam beam-formed reference signal carrying timing information, detecting a wide beam boundary between the first wide beam beam-formed reference signal and a second wide beam beam-formed reference signal during a subsequent time interval, wherein both the first wide beam beam-formed reference signal and the second wide beam beam-formed reference signal are rotated by a narrow beam beam-width during each intermediate time interval between the initial time interval and the subsequent time interval, and informing the mmWave eNB of an indication that the UE detected the wide beam boundary during the subsequent time interval, the indication being used to assign a narrow beam direction to the UE.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 10, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Bin Liu, Richard Stirling-Gallacher
  • Patent number: 10235341
    Abstract: Method for solving the decomposition-coordination calculation based on Block Bordered Diagonal Form (BBDF) model by using data center. During the solving process, partitioning the electric power system network by using the existing network partitioning method to achieve the grid partition, and setting the parameters of virtual memories firstly, thus to establish the bin-packing model with the priority of energy efficiency; and then, setting each calculating step of the decomposition-coordination calculation based on BBDF as a task. Through the manners that servers host VMs and VMs map tasks, the decomposition-coordination algorithm can be executed in data center, and the running time and energy consumption of data center can be calculated. The calculating time of decomposition-coordination algorithm is shortened and the energy consumption in data center.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 19, 2019
    Assignee: Tianjin University
    Inventors: Ting Yang, Wenping Xiang, Yingmin Feng, Haibo Pen, Mingyu Xu, Jinkuo You, Hongtao Wang
  • Patent number: 10096133
    Abstract: The systems and methods described herein can pre-process a blendshape matrix via a global clusterization process and a local clusterization process. The pre-processing can cause the blendshape matrix to be divided into multiple blocks. The techniques can further apply a matrix compression technique to each block of the blendshape matrix to generate a compression result. The matrix compression technique can comprise a matrix approximation step, an accuracy verification step, and a recursive compression step. The compression result for each block may be combined to generate a compressed blendshape matrix for rendering a virtual entity.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 9, 2018
    Assignee: ELECTRONIC ARTS INC.
    Inventor: Dmitry Andreevich Andreev
  • Patent number: 9941740
    Abstract: Systems, apparatus and methods for quantifying and identifying diversion of electrical energy are provided. Bypass and tap diversions may be identified in an electric utility power distribution inventory zone having both bypass and tap diversions. Bypass diversion factors for consumer nodes in an inventory zone are determined by finding a solution to a system of load balance equations having slack variables representing aggregate tap loads for the inventory zone and in which consumer load profile data is scaled by the bypass diversion factors, which solution minimizes an objective function whose value is positively related to the sum of the slack variables representing the aggregate tap loads.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 10, 2018
    Assignee: MBH CONSULTING LTD.
    Inventor: Michael Brent Hughes
  • Patent number: 9779374
    Abstract: The method includes determining an assignment completion time distribution based on a task set defining a project, determining a project completion time distribution based on the assignment completion time distribution and the task set, determining a project cost based on assignments of the task set, and generating a list of project task assignments based on the project cost and the project completion time distribution.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 3, 2017
    Assignee: SAP SE
    Inventors: Tianyu Luwang, Wen-Syan Li
  • Patent number: 9734262
    Abstract: A query answer engine converts a query and answers into a non-natural language forming units that correspond to words, symbols, numbers and spaces and combinations of the above, and establishes the contextual meaning of the units utilizing read, recognize and relate processes to populate a query matrix and an answer matrix with 3-valued points corresponding to the read, recognize and relate values of a unit. The two matrices are cross correlated to yield a robust answer to a query taking into account context. The conversion of text to units uses contextual meaning parametric tables, databases, libraries, rules and an engine for determining the focal point of a query or an answer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: August 15, 2017
    Inventor: Patrick Delefevre
  • Patent number: 9734144
    Abstract: In some examples, a computing system may access multiple information files, generate term-passage matrix data based on the multiple information files, and decompose the term-passage matrix data to generate a reduced-dimensional semantic space, which may be used for information retrieval.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: August 15, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Mihai Dasc{hacek over (a)}lu, David Walter Ash
  • Patent number: 9600446
    Abstract: A preconditioner processor and a method of computing a preconditioning matrix. In one embodiment, the preconditioner processor has parallel computing pipelines including: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an incomplete lower triangle, upper triangle factorization (ILU) computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning matrix, and (2b) compute non-zero elements of the ILU preconditioning matrix according to the sparsity pattern, and (3) a memory communicably couplable to the parallel computing pipelines and configured to store the ILU preconditioning matrix.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 21, 2017
    Assignee: Nvidia Corporation
    Inventors: Robert Strzodka, Julien Demouth, Patrice Castonguay
  • Patent number: 9547882
    Abstract: Disclosed herein is a shared memory systems that use a combination of SBR and MRRR techniques to calculate eigenpairs for dense matrices having very large numbers of rows and columns. The disclosed system allows for the use of a highly scalable tridiagonal eigensolver. The disclosed system likewise allows for allocating a different number of threads to each of the different computational stages of the eigensolver.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 17, 2017
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Cheng Liao
  • Patent number: 9523635
    Abstract: Apparatus and methods of spectral searching that employ wavelet coefficients as the basis for the searching. The disclosed apparatus and methods employ a wavelet lifting scheme to transform spectroscopic data corresponding to an unknown pure material/mixture to a vector of wavelet coefficients, compare the wavelet coefficient vector for the unknown pure material/mixture with a library of wavelet coefficient vectors for known pure materials/mixtures, and identify the closest match to the unknown pure material/mixture based on the comparison of wavelet coefficient vectors.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: December 20, 2016
    Assignee: Rigaku Raman Technologies, Inc.
    Inventor: Scott B. Tilden
  • Patent number: 9514415
    Abstract: A target quantum circuit expressed in a first quantum gate basis may be transformed into a corresponding quantum circuit expressed in a second quantum gate basis, which may be a universal set of gates such as a V gate basis set. The target quantum circuit may be expressed as a linear combination of quantum gates. The linear combination of quantum gates may be mapped to a quaternion. The quaternion may be factorized, based at least in part on an amount of precision between the target quantum circuit and the corresponding quantum circuit expressed in the second quantum gate basis, into a sequence of quaternion factors. The sequence of quaternion factors may be mapped into a sequence of quantum gates of the second quantum gate basis, where the sequence of sequence of quantum gates is the corresponding quantum circuit.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 6, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Alexei V. Bocharov, Yuri Gurevich, Krysta M. Svore
  • Patent number: 9418045
    Abstract: Systems, apparatus and methods for quantifying and identifying diversion of electrical energy are provided. Bypass and tap diversions may be identified in an electric utility power distribution inventory zone having both bypass and tap diversions. Bypass diversion factors for consumer nodes in an inventory zone are determined by finding a solution to a system of load balance equations having slack variables representing aggregate tap loads for the inventory zone and in which consumer load profile data is scaled by the bypass diversion factors, which solution minimizes an objective function whose value is positively related to the sum of the slack variables representing the aggregate tap loads.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 16, 2016
    Assignee: MBH CONSULTING LTD.
    Inventor: Michael Brent Hughes
  • Patent number: 9143325
    Abstract: A non-linear transformation including a plurality of non-linear logical operations is masked to a second or higher order. The masking includes receiving a set of random bits, and machine-masking two or more of the plurality of non-linear logical operations with a same random bit from the set of random bits.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 22, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Zhimin Chen, Jay Scott Fuller
  • Patent number: 9128763
    Abstract: A system and computer-implemented method for generating an optimized allocation of a plurality of tasks across a plurality of processors or slots for processing or execution in a distributed computing environment. In a cloud computing environment implementing a MapReduce framework, the system and computer-implemented method may be used to schedule map or reduce tasks to processors or slots on the network such that the tasks are matched to processors or slots in a data locality aware fashion wherein the suitability of node and the characteristics of the task are accounted for using a minimum cost flow function.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 8, 2015
    Assignee: Infosys Limited
    Inventors: Santonu Sarkar, Naveen Chandra Tewari, Rajarshi Bhose
  • Patent number: 9036661
    Abstract: Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: May 19, 2015
    Assignee: ViaSat, Inc.
    Inventors: Donald W. Becker, Matthew D. Nimon, William H. Thesling
  • Patent number: 9032006
    Abstract: Apparatus and method for processing linear systems of equations and finding a n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an n×1 vector xl satisfying Alxl=bl where Al, bl are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an n×1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an n×1 update vector u. The data elements of the current solution vector x are updated such that x=x+u.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Konstantinos Bekas, Alessandro Curioni
  • Patent number: 8959128
    Abstract: Wiberg minimization operates on a system with two sets of variables described by a linear function and in which some data or observations are missing. The disclosure generalizes Wiberg minimization, solving for a function that is nonlinear in both sets of variables, U and V, iteratively. In one embodiment, defining a first function ƒ(U, V) that may be defined that may be nonlinear in both a first set of variables U and a second set of variables V. A first function ƒ(U, V) may be transformed into ƒ(U, V(U)). First assumed values of the first set of variables U may be assigned. The second set of variables V may be iteratively estimated based upon the transformed first function ƒ(U, V(U)) and the assumed values of the first set of variables U such that ƒ(U, V(U)) may be minimized with respect to V. New estimates of the first set of variables U may be iteratively computed.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: February 17, 2015
    Assignee: Google Inc.
    Inventors: Dennis Strelow, Jay Yagnik
  • Publication number: 20150039663
    Abstract: A dynamical method and system generate a global optimal solution to a mixed integer nonlinear programming (MINLP) problem, where a part or all of optimization variables of the MINLP problem are restricted to have discrete values. The method computes a first integer solution to the MINLP problem with a given starting point using an MINLP solver; computes a set of stable equilibrium points (SEPs) of a nonlinear dynamical system associated with a relaxed continuous problem of the MINLP problem, where the SEPs surround the first integer solution and form one or more tiers; identifies from the SEPs a set of new starting points for the MINLP problem; computes integer solutions to the MINLP problem with progressively tightened bounds, starting from the new starting points using the MINLP solver; and generates the global optimal solution based on the integer solutions after one or more iterations.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Bigwood Technology Inc.
    Inventors: Hsiao-Dong Chiang, Tao Wang, Bin Wang
  • Publication number: 20150039664
    Abstract: Systems and techniques are described for solving a gate-sizing optimization problem using a constraints solver. Some embodiments can create a constraints problem based on a gate-sizing optimization problem for a portion of a circuit design. Specifically, the constraints problem can comprise a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem. Next, the embodiments can solve the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver. Specifically, prior to each invocation of the constraints solver, the upper bound can be increased or decreased based at least on a result returned by a previous invocation of the constraints solver.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Publication number: 20150006605
    Abstract: Provided are techniques for interaction detection for generalized linear models. Basic statistics are calculated for a pair of categorical predictor variables and a target variable from a dataset during a single pass over the dataset. It is determined whether there is a significant interaction effect for the pair of categorical predictor variables on the target variable by: calculating a log-likelihood value for a full generalized linear model without estimating model parameters; calculating the model parameters for a reduced generalized linear model with a recursive marginal mean accumulation technique using the basic statistics; calculating a log-likelihood value for the reduced generalized linear model; calculating a likelihood ratio test statistic using the log-likelihood value for the full generalized linear model and the log-likelihood value for the reduced generalized linear model; calculating a p-value of the likelihood ratio test statistic; and comparing the p-value to a significance level.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Yea J. Chu, Sier Han, Jing-Yun Shyr
  • Patent number: 8909688
    Abstract: Disclosed is a method of seeking semianalytical solutions to multispecies transport equations coupled with sequential first-order network reactions under conditions wherein a groundwater flow velocity and a dispersion coefficient vary spatially and temporally and boundary conditions vary temporally.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Korea Institute of Geoscience and Minerals Resources
    Inventors: Heejun Suk, Kyoochul Ha
  • Publication number: 20140358980
    Abstract: The invention relates to a method for generating a prime number, implemented in an electronic device, the method including steps of generating a prime number from another prime number using the formula Pr=2P·R+1, where P is a prime number having a number of bits lower than that of the candidate prime number, and R is an integer, and applying the Pocklington primality test to the candidate prime number, the candidate prime number being proven if it passes the Pocklington test. According to the invention, the size in number of bits of the candidate prime number is equal to three times the size of the prime number, to within one unit, the generated candidate prime number being retained as candidate prime number only if the quotient of the integer division of the integer by the prime number is odd.
    Type: Application
    Filed: December 12, 2012
    Publication date: December 4, 2014
    Inventors: Benoît Feix, Christophe Clavier, Pascal Paillier, Loïc Thierry
  • Patent number: 8874629
    Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 28, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: William Macready, Geordie Rose, Herbert J. Martin
  • Publication number: 20140258355
    Abstract: Provided are techniques for interaction detection for generalized linear models. Basic statistics are calculated for a pair of categorical predictor variables and a target variable from a dataset during a single pass over the dataset. It is determined whether there is a significant interaction effect for the pair of categorical predictor variables on the target variable by: calculating a log-likelihood value for a full generalized linear model without estimating model parameters; calculating the model parameters for a reduced generalized linear model with a recursive marginal mean accumulation technique using the basic statistics; calculating a log-likelihood value for the reduced generalized linear model; calculating a likelihood ratio test statistic using the log-likelihood value for the full generalized linear model and the log-likelihood value for the reduced generalized linear model; calculating a p-value of the likelihood ratio test statistic; and comparing the p-value to a significance level.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: International Business Machines Corporation
    Inventors: Yea J. Chu, Sier Han, Jing-Yun Shyr
  • Publication number: 20140258356
    Abstract: Optimization processes, which are parameter driven for solving interdiction problems, for example, power grid interdiction problems, are provided. An algorithm of the subject invention can include column-and-constraint generation and can be used to solve a set of system interdiction, vulnerability analysis, and reliability based design problems, including a power grid vulnerability analysis problem and an edge-interdiction minimum dominating set problem. An algorithm can be provided on a computer-readable medium, a computer, a portable computing device, or other machine.
    Type: Application
    Filed: December 13, 2013
    Publication date: September 11, 2014
    Applicant: University of South Florida
    Inventors: Bo Zeng, Long Zhao
  • Patent number: 8824603
    Abstract: A method and a system is provided for Coordinate Rotation Digital Computer (CORDIC) based matrix inversion of input digital signal streams from multiple antennas using an bi-directional ring-bus architecture. The bi-directional ring bus includes a first ring bus having signals flow in a clockwise direction, and a second ring bus having signals flow in a counter-clockwise direction. An I/O controller is coupled to the first and the second ring bus, respectively. A plurality of processing elements (PEs), where each of the plurality of PEs is coupled to the first and the second ring bus, respectively, wherein each of the plurality of PEs includes at least one CORDIC core for performing CORDIC iterations on the plurality of input digital stream signals to produce inversed matrix signals.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: September 2, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yiqun Ge, Qifan Zhang, Peter Man Kin Sinn
  • Patent number: 8805910
    Abstract: Method and apparatus for processing continuous-time models (CTM) in a digital processing architecture is disclosed. The discrete state-space technique maps the CTM into the discrete-time model (DTM) and stores the states of the system in a sample time independent discrete state space set of matrices. The resulting state-space matrices can be processed in software or directly in hardware. The method disclosed is particularly suited to be used in automatic synthesis algorithms where a digital circuit is generated from an algorithm described in a high level language or model representation such as, for example, data flow or bond graph into a hardware description language (HDL), and the HDL model can be synthesized using system specific tools to generate an application specific integrated circuit (ASIC) or an FPGA configuration.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: August 12, 2014
    Assignee: Kylowave Inc.
    Inventors: Julio C. G. Pimentel, Emad Gad
  • Patent number: 8805911
    Abstract: Efficient and scalable circuitry for performing Cholesky decomposition is based on two types of processing elements. A first type of processing element provides inverse square root and multiplication operations. A second type of processing element includes a first computation path for outputting an inner product difference element and a second computation path for outputting an inner product element. Processing elements of the first and second type may be cascaded to achieve a decomposition of a matrix of an arbitrary size. The circuitry is flexible to allow different throughput requirements, and can be optimized to reduce latency and resource consumption.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: August 12, 2014
    Assignee: Altera Corporation
    Inventors: Lei Xu, Martin Langhammer
  • Patent number: 8805912
    Abstract: When a Cholesky decomposition or a modified Cholesky decomposition is performed on a sparse symmetric positive definite matrix using a shared memory parallel computer, the discrete space in a problem presented by the linear simultaneous equations expressed by the sparse matrix is recursively sectioned into two sectioned areas and a sectional plane between the areas. The sectioning operation is stopped when the number of nodes configuring the sectional plane reaches the width of a super node. Each time the recursively halving process is performed, a number is sequentially assigned to the node in the sectioned area in order from a farther node from the sectional plane. The node in the sectional plane is numbered after assigning a number to the sectioned area each time the recursively halving process is performed.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Limited
    Inventor: Makoto Nakanishi
  • Patent number: 8788559
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: July 22, 2014
    Assignee: Empire Technology Development LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 8775147
    Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: July 8, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Alireza Pakyari, Brian K. Ogilvie
  • Patent number: 8762442
    Abstract: A system and method are provided for a parallel processing of the Hamilton-Jacobi equation. A numerical method is provided to solve the Hamilton-Jacobi equation that can be used with various parallel architectures and an improved Godunov Hamiltonian computation.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 24, 2014
    Assignee: University of Utah Research Foundation
    Inventors: Won-ki Jeong, Ross Whitaker
  • Patent number: 8719303
    Abstract: This invention proposed a new algorithm. By multiply the proposed weight coefficients of this invention, CSP and CSS can be computed without computing for the mean(s) of the data. After the proposed weight coefficients of this invention undergo factorization, it can promote a new recursive and real time updatable computation method. To test the accuracy of the new invention, the StRD data were separately tested using SAS ver 9.0, SPSS ver15.0 and EXCEL 2007 for comparison. The results showed that the accuracy of the results of the proposed invention exceeds the level of accuracy of SAS ver9.0, SPSS ver15.0 and EXCEL 2007. Aside from an accurate computation, this new invented algorithm can also produce efficient computations.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: May 6, 2014
    Inventors: Juei-Chao Chen, Kuo-Hung Lo, Tien-Lung Sun
  • Patent number: 8711146
    Abstract: Methods and apparatuses for constructing a multi-level solver, comprising decomposing a graph into a plurality of pieces, wherein each of the pieces has a plurality of edges and a plurality of interface nodes, and wherein the interface nodes in the graph are fewer in number than the edges in the graph; producing a local preconditioner for each of the pieces; and aggregating the local preconditioners to form a global preconditioner.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: April 29, 2014
    Assignee: Carnegie Mellon University
    Inventors: Gary Lee Miller, Ioannis Koutis
  • Patent number: 8700686
    Abstract: A computer-implemented method for estimating a time-varying parameter of a nonlinear system includes receiving input data for the nonlinear system, the input data including a desired state and a desired state derivative of the nonlinear system for a number of time points, generating for one of the plurality of time points an approximate time-varying parameter based on at least the desired state, the desired state derivative, an approximate state of the nonlinear system, and a Lyapunov function, and providing the approximate time-varying parameter for the one of the plurality of time points.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 15, 2014
    Assignee: The MathWorks, Inc.
    Inventor: Shrikant V. Savant
  • Patent number: 8682950
    Abstract: An input polynomial, in symbolic form, is received, classified, pre-processed, and factored. The input polynomial is classified as a constant, a univariate polynomial, or a multivariate polynomial. Various pre-processing is performed depending on the classification. After the input polynomial is pre-processed, the remaining polynomial is factored using a polynomial factoring algorithm. By pre-processing the input polynomial, the complexity of the polynomial to be factored is reduced, which reduces the computational expense of the polynomial factoring algorithm.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 25, 2014
    Assignee: Microsoft Corporation
    Inventors: Xu Yang, Xiaolin Quan, Zhihui Ba, Dongmei Zhang
  • Publication number: 20140067892
    Abstract: Methods for finding (i) the parameter var(?2), representing the variance of a prior historical distribution ?C (?2) of hidden error variances ?2; (ii) the parameter “a” defining the rate of change of the mean ensemble variance response to changes in true error variance; (iii) the parameter ?min2 representing a prior historical minimum of true error variance; (iv) the parameter k?1, representing the relative variance of the stochastic component of variance prediction error; and (v) the parameter M, representing the effective ensemble size.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 6, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Craig H. Bishop, Elizabeth Ann Satterfield
  • Publication number: 20140046993
    Abstract: A system and method for preconditioning or smoothing (e.g., multi-color DILU preconditioning) for iterative solving of a system of equations. The method includes accessing a matrix comprising a plurality of coefficients of a system of equations and accessing coloring information corresponding to the matrix. The method further includes determining a diagonal matrix based on the matrix and the coloring information corresponding to the matrix. The determining of the diagonal matrix may be determined in parallel on a per color basis. The method may further include determining an updated solution to the system of equations where the updated solution is determined in parallel on a per color basis using the diagonal matrix.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Patrice Castonguay, Robert Strzodka
  • Patent number: 8649508
    Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 11, 2014
    Assignee: Tata Consultancy Services Ltd.
    Inventor: Natarajan Vijayarangan
  • Publication number: 20140025720
    Abstract: One embodiment sets forth a method for solving linear equation systems that include the same matrix A coupled with multiple right-hand-side vectors. For each new right-hand-side vector, a solver expands an existing Krylov subspace based on the Krylov subspace and data associated with the previous right-hand-side vector. The solver then uses the expanded Krylov subspace to approximately solve the linear equation system for the new right-hand-side vector. By expanding the Krylov subspace for each new right-hand-side vector, the solver continually leverages the information from the preceding right-hand-side vectors. Advantageously, expanding the Krylov subspace is typically computationally quicker than prior art-techniques, such as creating a new Krylov subspace or transforming an existing Krylov subspace. Consequently, by implementing the disclosed techniques, the likelihood of exceeding time constraints associated with algorithms that include solving certain classes of linear equation systems may be decreased.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 23, 2014
    Inventor: Robert STRZODKA
  • Patent number: 8626815
    Abstract: In a matrix multiplication in which each element of the resultant matrix is the dot product of a row of a first matrix and a column of a second matrix, each row and column can be broken into manageable blocks, with each block loaded in turn to compute a smaller dot product, and then the results can be added together to obtain the desired row-column dot product. The earliest results for each dot product are saved for a number of clock cycles equal to the number of portions into which each row or column is divided. The results are then added to provide an element of the resultant matrix. To avoid repeated loading and unloading of the same data, all multiplications involving a particular row-block can be performed upon loading that row-block, with the results cached until other multiplications for the resultant elements that use the cached results are complete.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: January 7, 2014
    Assignee: Altera Corporation
    Inventor: Martin Langhammer