Residue Number Patents (Class 708/491)

Patent number: 10735026Abstract: Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.Type: GrantFiled: July 22, 2019Date of Patent: August 4, 2020Assignee: IDENSIFY LLCInventors: Dan E. Tamir, Dan Bruck

Patent number: 10691416Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an nbit integer, y is an mbit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first mbit integer ? and a second mbit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum rightshifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.Type: GrantFiled: July 2, 2019Date of Patent: June 23, 2020Assignee: Imagination Technologies LimitedInventor: Thomas Rose

Patent number: 10601582Abstract: The invention relates to the field of computer engineering and cryptography and, in particular, to methods for implementing linear transformations that operate with a specified speed and require minimum amount of memory, for further usage in devices for cryptographic protection of data. The technical result enables the selection of interrelated parameters (performance and required amount of memory) for a particular computing system when implementing a highdimensional linear transformation. The use of the present method allows for a reduction of the amount of consumed memory at a given word size of processors employed. To this end, based on a specified linear transformation, a modified linear shift register of Galoistype or Fibonaccitype is generated according to the rules provided in the disclosed method, and the usage thereof enables to obtain the indicated technical result.Type: GrantFiled: July 26, 2016Date of Patent: March 24, 2020Assignee: Joint Stock Company “InfoTeCS”Inventors: Nikolay Pavlovich Borisenko, Alexey Viktorovich Urivskiy

Patent number: 10601578Abstract: A method for protecting against faults in a computation of a point multiplication Q=[k]P on an elliptic curve E defined over a prime field p, including: defining an integer r and a group ?={?()?/r} represented with elements having a group law that coincides with a group law used in the representation for E(p) and isomorphic to an additive group (/r)+ through isomorphism ?; forming a combined group E(p)×?E(p)×(/r)+ which is isomorphic to a cross product of the groups E(p) and (/r)+; selecting an element in /r and defining an element P?=?() in group ?; forming a combined element {circumflex over (P)}=CRT(P,P?) in the group E(p)×?; calculating {circumflex over (Q)}=[k]{circumflex over (P)} in the combined group E(p)×?; calculating k in /r; and checking whether {circumflex over (Q)}?Q?(mod r) where Q?=?(k).Type: GrantFiled: October 26, 2017Date of Patent: March 24, 2020Assignee: NXP B.V.Inventor: Marc Joye

Patent number: 10599398Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplieraccumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.Type: GrantFiled: October 12, 2018Date of Patent: March 24, 2020Assignee: Olsen IP Reserve, LLCInventor: Eric B. Olsen

Patent number: 10579335Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.Type: GrantFiled: June 20, 2017Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Sudhir K. Satpathy, Sanu K. Mathew, Vikram B. Suresh, Raghavan Kumar

Patent number: 10528325Abstract: Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and leftshifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a predefined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.Type: GrantFiled: September 13, 2018Date of Patent: January 7, 2020Assignee: Imagination Technologies LimitedInventor: Simon Fenney

Patent number: 10505712Abstract: A modular reduction calculation on a first number and a second number is protected from sidechannel attacks, such as timing attacks. A first intermediate modular reduction result is calculated. A value corresponding to four times the first number is added to the first intermediate modular reduction result, generating a second intermediate modular reduction result. A value corresponding to the first number multiplied by a most significant word of the second intermediate modular reduction result plus 1, is subtracted from the second intermediate modular reduction result, generating a third intermediate modular reduction result. A cryptographic operation is performed using a result of the modular reduction calculation.Type: GrantFiled: November 30, 2017Date of Patent: December 10, 2019Assignee: STMICROELECTRONICS S.R.L.Inventor: Ruggero Susella

Patent number: 10496372Abstract: An electronic calculating device for performing arithmetic in a commutative ring includes a storage configured to store an increment table defined for an increment ring element, the increment table mapping an input ring element to an output integerlist encoding an output ring element, such that the output ring element equals the increment ring element ringadded to the input ring element. Using the increment table, a ring addition unit adds a first additioninput integerlist encoding a first additioninput ring element and a second additioninput integer list encoding a second additioninput ring element. The device may include a ring multiplication unit also using the increment table.Type: GrantFiled: September 30, 2015Date of Patent: December 3, 2019Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Leandro Marin, Alphons Antonius Maria Lambertus Bruekers, Paulus Mathias Hubertus Mechtildis Antonius Gorissen

Patent number: 10474431Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.Type: GrantFiled: November 6, 2015Date of Patent: November 12, 2019Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZINSTITUT FUR INNOVATIVE MIKROELEKTRONIKInventors: Zoya Dyka, Peter Langendorfer

Patent number: 10423417Abstract: A fault tolerant multithreaded processor uses the temporal and/or spatial separation of instructions running in two or more different threads. An instruction is fetched, decoded and executed by each of two or more threads to generate a result for each of the two or more threads. These results are then compared using comparison hardware logic and if there is a mismatch between the results obtained, then an error or event is raised. The comparison is performed on an instruction by instruction basis so that errors are identified (and hence can be resolved) quickly.Type: GrantFiled: June 17, 2015Date of Patent: September 24, 2019Assignee: MIPS Tech, LLCInventor: Julian Bailey

Patent number: 10372420Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an nbit integer, y is an mbit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first mbit integer ? and a second mbit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum rightshifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.Type: GrantFiled: May 9, 2016Date of Patent: August 6, 2019Assignee: Imagination Technologies LimitedInventor: Thomas Rose

Patent number: 10374790Abstract: The subject of the invention is a countermeasure method for an electronic component implementing a publickey cryptography algorithm on an elliptic curve E defined over a field and comprising an iterative scalar multiplication operation making it possible to obtain a point [k]P on the basis of a point P of the curve E and of an integer k that must remain secret, the electrical consumption of the electronic component being dependent on the value taken by at least one socalled critical point used during said operation to iteratively determine the point [k]P.Type: GrantFiled: February 12, 2015Date of Patent: August 6, 2019Assignee: SECUREIC SASInventors: Cédric Murdica, Sylvain Guilley

Patent number: 10331840Abstract: Methods are disclosed to determine if wiring resources are available in the neighborhood of a physically routed net in all three dimensions. Such a method can select a wire trait based on an amount of usage of each wire segment in the net and the total percentage usage of the net. The method can also reroute a net using new wiring resources after determining that wiring resources are available. The new resources can provide improved RC (delay) characteristics and reduced signal coupling. The method can be applied to a VLSI design with multiple fails.Type: GrantFiled: January 15, 2016Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alice H. Lee, Adam P. Matheny, Jose Luis Pontes Neves

Patent number: 10216483Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.Type: GrantFiled: September 5, 2017Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: T. J. O'Dwyer, Pierre Laurent

Patent number: 10216480Abstract: An aspect includes fetching a computer instruction, the fetching by an instruction fetch unit. It is determined that the instruction is a decimal divide instruction that specifies a decimal divisor and a decimal dividend. The decimal divisor is converted into a floatingpoint divisor and the decimal dividend is converted into a floatingpoint dividend. A floatingpoint division of the floatingpoint dividend by the floatingpoint divisor is performed by an instruction execution unit. It is determined that the floatingpoint division resulted in a quotient overflow. A reduced size floatingpoint dividend is generated based on the quotient overflow, the floatingpoint divisor, and the floatingpoint dividend. The floating point division of the reduced size floatingpoint dividend by the floatingpoint divisor is performed by the instruction execution unit, and a specified number of rightmost bits of the result is output as the quotient.Type: GrantFiled: January 27, 2017Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric M. Schwarz, Craig M. Slegel, Timothy J. Slegel

Patent number: 10175950Abstract: A Montgomery modular multiplication device and an embedded security chip. The Montgomery modular multiplication device includes a first Montgomery modular multiplication module, a power calculation module and a second Montgomery modular multiplication module. The first Montgomery modular multiplication module obtains a first operation result A according to two first preset parameters. The power calculation module obtains a second operation result B according to the first operation result A output by the first Montgomery modular multiplication module, the first preset parameters, the second preset parameter and a power calculation function. The first Montgomery modular multiplication module further obtains a Montgomery modular multiplication conversion coefficient according to the first operation result A and the second operation result B.Type: GrantFiled: September 26, 2016Date of Patent: January 8, 2019Assignee: SHENZHEN STATE MICRO TECHNOLOGY CO., LTD.Inventors: Songliang Yu, Jinqiang Chen, Hao Xu

Patent number: 10162599Abstract: In some applications, such as randomization and cryptography, remainder computation for a number is required. The remainder computation is also used in modulo arithmetic. The remainder computation can be simplified when the divisor belongs to a certain class of numbers. A method and apparatus are disclosed that enable low complexity implementation of remainder computation of any number when the divisor belongs to a type of numbers that can be represented as 2k+1.Type: GrantFiled: September 8, 2017Date of Patent: December 25, 2018Assignee: MBIT WIRELESS, INC.Inventors: Bhaskar Patel, Arumugam Govindswamy

Patent number: 10101970Abstract: Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and leftshifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a predefined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.Type: GrantFiled: May 25, 2016Date of Patent: October 16, 2018Assignee: Imagination Technologies LimitedInventor: Simon Fenney

Patent number: 10084599Abstract: A decryption method includes receiving encrypted data, in which the encrypted data is encrypted by an RSA public key; and performing at least one multiplication operation and at least one square operation according to an RSA private key and the encrypted data to acquire decrypted data. A false square operation is performed in performing one of the at least one multiplication operation, or a false multiplication operation is performed in performing one of the at least one square operation.Type: GrantFiled: April 1, 2016Date of Patent: September 25, 2018Assignee: Realtek Semiconductor CorporationInventor: TzungJuei Wu

Patent number: 10041783Abstract: A technology is provided that makes it possible for even a beginner to determine whether a measurement result is correct, to thereby prevent the use of incorrect measurement data, and to improve the reliability of an analysis result. In a threedimensional shape measurement apparatus 100 that measures a threedimensional shape of a specimen 3 in a noncontacting manner, a score that evaluates the reliability of measurement data is calculated for each measurement point by use of information obtained during a process of estimating the height of the specimen 3 or the estimated height. Measurement data is processed according to a result of evaluating the measurement data for each measurement point by use of the score.Type: GrantFiled: March 1, 2016Date of Patent: August 7, 2018Assignee: OLYMPUS CORPORATIONInventors: Akihiro Fujii, Yosuke Tani

Patent number: 10020438Abstract: A magnetic topological nanowire structure comprises a superconductor and a quasi1D magnetic nanowire. The quasi1D magnetic nanowire is coupled to or embedded in the superconductor to produce a selfcontained interaction resulting in a spatially separated pair of Majorana fermions. The pair of Majorana fermions corresponds to the topological superconductor and each of the pair of the Majorana fermions are localized near a respective endpoint of the nanowire.Type: GrantFiled: August 4, 2015Date of Patent: July 10, 2018Assignee: The Trustees of Princeton UniversityInventors: Ali Yazdani, Andrei Bernevig

Patent number: 9942038Abstract: Various embodiments relate to a device for generating code which implements modular exponentiation, the device including: a memory used to store a lookup table; and a processor in communication with the memory, the processor configured to: receive information for a generated randomized addition chain; output code for implementing the modular exponentiation which loads elements from the lookup table including intermediate results which utilize the information for a generated randomized addition chain; and output code for implementing the modular exponentiation which uses the loaded elements to compute the next element.Type: GrantFiled: November 4, 2015Date of Patent: April 10, 2018Assignee: NXP B.V.Inventor: Joppe Willem Bos

Patent number: 9904516Abstract: Various embodiments relate to a method of encoding data and a related device and nontransitory machine readable storage medium, including: determining a plurality of factors of a value, b, to be exponentiated; retrieving, from a lookup table, a plurality of lookup table entries associated with the plurality of factors; calculating a product of the plurality of lookup table entries; and calculating a residue of the product using a cryptographic key modulus, N, to produce an exponentiated value, s.Type: GrantFiled: April 17, 2015Date of Patent: February 27, 2018Assignee: NXP B.V.Inventors: Joppe Bos, Michaël Peeters

Patent number: 9887833Abstract: Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes identifying a process to obtain timing information of a processorbased device, and in response to identifying the process to obtain the timing information, delaying delivery of the timing information for a timedelay period. In some embodiments, identifying the process to obtain the timing information may include identifying a request to obtain the timing information of the processorbased device. In some embodiments, identifying the process to obtain the timing information may include identifying a memoryaccess process.Type: GrantFiled: February 27, 2013Date of Patent: February 6, 2018Assignee: The Trustees of Columbia University in the City of New YorkInventors: Lakshminarasimhan Sethumadhavan, Robert Martin, John Demme

Patent number: 9870201Abstract: The procedure of finding the remainder of a division is referred to as modulo operation. Modulo arithmetic is used in many applications. A method and apparatus are disclosed that enable faster and less complex implementation of modulo arithmetic for a certain class of numbers.Type: GrantFiled: March 4, 2016Date of Patent: January 16, 2018Assignee: MBIT WIRELESS, INC.Inventors: Angelin Jeyachandra, Bhaskar Patel

Patent number: 9794315Abstract: A method, computer program product and client electronic device for storing, in a memory of a client electronic device, a location of at least one remote media data file available to stream from a server device. A location of at least one local media data file available on the client electronic device is stored in the memory of the client electronic device. A playlist is compiled that defines the location of the at least one remote media data file and the location of the at least one local media data file. The at least one local media data file and the at least one remote media data file in the playlist are rendered and metadata concerning the at least one local media data file rendered is transmitted to the server device.Type: GrantFiled: November 15, 2016Date of Patent: October 17, 2017Assignee: Intel CorporationInventor: Bryna L. Bank

Patent number: 9742261Abstract: The present application relates to AC power supplies and in particular to power factor correction circuits in ACDC converters. The application provides an active power factor correction circuit in which zero voltage switching is inherently achieved using a passive snubbing approach employing a saturable transformer.Type: GrantFiled: March 14, 2014Date of Patent: August 22, 2017Assignee: Icergi LimitedInventor: George Young

Patent number: 9588696Abstract: Disclosed is a Montgomery modular multiplicationbased data processing method. The method includes: a CPU initializing a fifth random access memory, and performing the following operations on content in a unit of a word in a second random access memory, namely: (1) calling a multiplying and adding module to multiply one word of the content of the second random access memory and content of a first random access memory and add the product to content of the fifth random access memory; (2) extracting one word from an operation result of the step (1) and multiplying the word with content of a constant register, and writing a loworder word of the multiplied result into a fourth register; (3) calling the multiplying and adding module to multiply content of a fourth register with content of a third random access memory and add the product to the content of the fifth random access memory; and finally, outputting the content of the fifth random access memory according to the content of the third memory.Type: GrantFiled: December 2, 2013Date of Patent: March 7, 2017Assignee: FEITIAN TECHNOLOGIES CO., LTD.Inventors: Zhou Lu, Huazhang Yu

Patent number: 9535656Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: GrantFiled: March 14, 2014Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck

Patent number: 9417816Abstract: A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.Type: GrantFiled: January 2, 2014Date of Patent: August 16, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventor: David A. Roberts

Patent number: 9183076Abstract: Systems and methods for using carryless multiplication (CLMUL) to implement erasure code are provided. An embodiment method of using CLMUL to implement erasure code includes initiating, with a processor, a first CLMUL call to calculate a first product of a data bit word and a constant, partitioning, with the processor, the first product into a high portion and a low portion, and initiating, with the processor, a second CLMUL call to calculate a second product of the high portion and a hexadecimal number portion, a bit size of the second product less than a bit size of the first product. The second product, or a third product generated by a third CLMUL call, is used to calculate a parity bit. Because the second product or the third product has a number of bits equivalent to the number of bits used by the processor, the erasure codes are more efficiently implemented.Type: GrantFiled: April 19, 2013Date of Patent: November 10, 2015Assignee: Futurewei Technologies, Inc.Inventor: James Hughes

Patent number: 9179406Abstract: A method and apparatus for optimizing the yield of tested electronics devices is provided. A sample device is characterized to derive a specification for each device in the group. The sample size is chosen to provide reliable data and to minimize the effect of outlier devices on the characterization. After characterization, boundaries are set for the group of tested devices. Boundaries may be set based on voltages optimized for power consumption. The group of devices may be further subdivided into subgroups based on the results of testing. The subgroups are each assigned a unique code that reflects the results of the testing. This code is programmed into automated test equipment and is also stored in system software in order to ensure consistent values across the group of tested devices. The automated test equipment and system software are correlated using the same code to ensure higher test yield.Type: GrantFiled: October 17, 2012Date of Patent: November 3, 2015Assignee: QUALCOMM IncorporatedInventors: Sachin D Dasnurkar, Prasannakumar Seeram, Prasad Rajeevalochanam Bhadri

Patent number: 9098381Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.Type: GrantFiled: January 4, 2013Date of Patent: August 4, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoungmoon Ahn, Jonghoon Shin, Yong Ki Lee, JiSu Kang, SunSoo Shin

Patent number: 9081608Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.Type: GrantFiled: May 19, 2012Date of Patent: July 14, 2015Assignee: Digital System Research Inc.Inventor: Eric B. Olsen

Patent number: 9047167Abstract: A method for calculating the modular inverse of a value in relation to a module is used for cryptographic calculations on a portable data carrier. The method includes determining a breakdown of the module into at least two factors, calculating a respective auxiliary value for each of the factors, wherein each auxiliary value is the modular inverse of the value in relation to the respective factor as module, and calculating the modular inverse of the value in relation to the module using the calculated auxiliary values. The method offers an increase in efficiency, with greater efficiency obtained the stronger the computing outlay depends on the length of the module in the inversion method. The method is suitable for execution by relatively lowpower processors, and security of the calculation against spying attacks is not impaired. If security requirements are high, combining the method with suitable measures against spying presents no problems.Type: GrantFiled: May 5, 2003Date of Patent: June 2, 2015Assignee: Giesecke & Devrient GmbHInventor: Helmut Kahl

Patent number: 9043377Abstract: A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.Type: GrantFiled: January 30, 2012Date of Patent: May 26, 2015Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Young Sik Kim, Kyoung Moon Ahn, Jong Hoon Shin, SunSoo Shin, JiSu Kang

Patent number: 8984039Abstract: A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.Type: GrantFiled: February 6, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Maarten Jakob Boersma, Juergen Haess

Patent number: 8984040Abstract: A method and apparatus for performing modular exponentiation using iterative modular multiplications steps and taking as input a first modulus N, a secret exponent d and a base x. During at least one modular multiplication step aiming at computing a result c from two values a, b and the first modulus N so that c=a·b mod N, a processor takes as input the two values a, b and the first modulus N from which are obtained two operands a?, b? and a second modulus N? using operations with at most linear complexity—at least one of the two operands a?, b? is different from the two values a, b, and the two operands a?, b? are different when a is equal to b—so that the modular multiplication c=a·b mod N from a sidechannel viewpoint behaves like a modular squaring except for when a? equals b? . An intermediate result c?=a?·b? mod N? is computed, and the result c is derived from the intermediate result c? using an operation with at most linear complexity; and the result c is used in the modular exponentiation.Type: GrantFiled: May 11, 2012Date of Patent: March 17, 2015Assignee: Thomson LicensingInventor: Marc Joye

Patent number: 8965943Abstract: The subject invention pertains to a method and apparatus for performing computations using residue arithmetic. The subject method and apparatus can utilize logic gates for performing calculations such as multiplication by a constant, computing a number theoretic logarithm of a residue for a given base ?i and modulus pi, and computing the product of two residues, modulo pi. The use of logic gates can offer advantages when compared with the use of ROMs for table lookup functions in integrated RNS digital signal processor implementations.Type: GrantFiled: May 14, 2012Date of Patent: February 24, 2015Assignee: The Athena Group, Inc.Inventor: Jonathon D. Mellott

Patent number: 8958555Abstract: In one exemplary embodiment of the invention, a method for computing a resultant and a free term of a scaled inverse of a first polynomial v(x) modulo a second polynomial fn(x), including: receiving the first polynomial v(x) modulo the second polynomial fn(x), where the second polynomial is of a form fn(x)=xn±1, where n=2k and k is an integer greater than 0; computing lowest two coefficients of a third polynomial g(z) that is a function of the first polynomial and the second polynomial, where g(z)?i=0n?1(v(?i)?z), where ?0, ?1, . . . , ?n?1 are roots of the second polynomial fn(x) over a field; outputting the lowest coefficient of g(z) as the resultant; and outputting the second lowest coefficient of g(z) divided by n as the free term of the scaled inverse of the first polynomial v(x) modulo the second polynomial fn(x).Type: GrantFiled: June 19, 2013Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: Craig B. Gentry, Shai Halevi

Patent number: 8935310Abstract: A remainder by division of a sequence of bytes interpreted as a first number by a second number is calculated. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division.Type: GrantFiled: June 13, 2012Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Michael Hirsch, Shmuel T. Klein, Yair Toaff

Patent number: 8930431Abstract: A remainder by division of a sequence of bytes interpreted as a first number by a second number is calculated. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division.Type: GrantFiled: December 15, 2010Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Michael Hirsch, Shmuel T. Klein, Yair Toaff

Patent number: 8909689Abstract: According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundantbinaryrepresented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bitshifted by the first shift amount, the integer p, and the integer y which has been bitshifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.Type: GrantFiled: January 30, 2012Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Shimizu, Yuichi Komano, Koichi Fujisaki, Shinichi Kawamura

Patent number: 8880577Abstract: The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2n<N?2n+1; performing an initialization operation by initializing a constant a to the smallest integer greater than or equal to half of N; performing a first operation by subtracting, when C is greater than or equal to N·a (product of N and a), the value of C by the value of N·a; and performing a second operation by assigning the smallest integer greater than or equal to half of a to the value of a, wherein the value of C is output as the result of modulo operation after the first operation and the second operation are repeated n times. In the first operation, when C is less than N·a, the value of C is unchanged.Type: GrantFiled: June 10, 2010Date of Patent: November 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Uk Woo, In Tae Kang, Yun Ju Kwon, Dong Min Kim

Patent number: 8862651Abstract: A modulo reduction is performed on a value a represented as an ordered sequence of computer readable words. The lowest order words are eliminated by substituting an equivalent value represented by higher order words for each of the lower order words. The lowest order words are eliminated until the sequence has a word length corresponding to the modulus. Carries and borrows resulting from the substitution are propagated from lower order words to higher order words. Further reduction is performed to maintain the word length of the sequence to that of the modulus. The further reduction may be determined by examination of a carryover bit or may be performed a predetermined number of times without examination.Type: GrantFiled: October 30, 2009Date of Patent: October 14, 2014Assignee: Certicom Corp.Inventor: Robert John Lambert

Publication number: 20140280410Abstract: A binary logic circuit is provided for determining a rounded value of px q , where p and q are coprime constant integers with p<q and q?2i, i is any integer, and x is an integer variable between 0 and integer M where M?2q, the binary logic circuit implementing in hardware the optimal solution of the multiplyadd operation ax + b 2 k where a, b and k are fixed integers.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: IMAGINATION TECHNOLOGIES LIMITEDInventor: Thomas Rose

Patent number: 8819098Abstract: Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number is provided. A pseudoremainder by division associated with a first subsequence of the sequence of bytes is calculated. A property of this pseudoremainder is that the first subsequence of the sequence of bytes, interpreted as a third number, and the pseudoremainder by division have the same remainder by division when divided by the second number. A second subsequence of the sequence of bytes interpreted as the first number is appended to the pseudoremainder, interpreted as a sequence of bytes, so as to create a sequence of bytes interpreted as a fourth number. The first number and the fourth number have the same remainder by division when divided by the second number.Type: GrantFiled: November 23, 2010Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Michael Hirsch, Shmuel T. Klein, Yair Toaff

Patent number: 8799343Abstract: Embodiments of techniques and systems for sidechannelprotected modular exponentiation are described. In embodiments, during a modular exponentiation calculation, Montgomery Multiplication (“MM”) results are produced. These MM results are scattered through a table for storage, such that storage of the values may not lead to discovery of a secret exponent value by a spy process through a sidechannel attack. The scattering may be performed in order to reduce a number of perresult memory operations performed during each MM result storage or retrieval. In embodiments, a window size of 4 may be used in the modular exponentiation, along with partitioning of the MM result into 32bit partition values which are scattered with offsets of 64bytes. In embodiments, while use of a window size of 4 may result in additional MM calculations during modular exponentiation than other window sizes, the reduction in memory operations may provide a positive performance offset.Type: GrantFiled: September 22, 2011Date of Patent: August 5, 2014Assignee: Intel CorporationInventors: Shay Gueron, Vlad Krasnov

Patent number: 8793300Abstract: A circuit for calculating a sum of products, each product having a qbit binary operand and a kbit binary operand, where k is a multiple of q, includes a qinput carrysave adder (CSA); a multiplexer (10) by input of the adder, having four kbit channels respectively receiving the value 0, a first (Yi) of the kbit operands, the second kbit operand (M[63:0], mi), and the sum of the two kbit operands, the output of a multiplexer of rank t (where t is between 0 and q?1) being taken into account by the adder with a tbit left shift; and each multiplexer having first and second path selection inputs, the bits of a first of the qbit operands being respectively supplied to the first selection inputs, and the bits of the second qbit operand being respectively supplied to the second selection inputs.Type: GrantFiled: April 11, 2012Date of Patent: July 29, 2014Assignee: INSIDE SecureInventor: Michael Niel