Abstract: A cryptographic system (CS) is provided. The CS (800) comprises a data stream receiving means (DSRM), a generator (702), a mixed radix converter (MRC) and an encryptor (908). The DSRM (902) is configured to receive a data stream (DS). The generator is configured to selectively generate a random number sequence (RNS) utilizing a punctured ring structure. The MRC (704) is coupled to the generator and configured to perform a mixed radix conversion to convert the RNS from a first number base to a second number base. The encryptor is coupled to the DSRM and MRC. The encryptor is configured to generate an altered data stream by combining the RNS in the second number base with the DS. The punctured ring structure and the MRC are configured in combination to produce an RNS in the second number base which contains a priori defined statistical artifacts after the mixed radix conversion.

Abstract: A cryptographic system (CS) is provided. The CS (500) is comprised of a data stream receiving device (DSRD), a chaotic sequence generator (CSG) and an encryptor. The DSRD (602) is configured to receive an input data stream. The CSG (300) includes a computing means (3020, . . . , 302N-1) and a mapping means (304). The computing means is configured to use RNS arithmetic operations to respectively determine solutions for polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The mapping means is configured to determine a series of digits in the weighted number system based on the RNS residue values. The encryptor is coupled to the DSRD and CSG. The encryptor is configured to generate a modified data stream by incorporating or combining the series of digits with the input data stream.

Abstract: A special form of a modulus and a modified Barrett reduction method are used to perform modular arithmetic in a cryptographic system. The modified Barrett reduction is a method of reducing a number modulo another number without the use of any division. By pre-computing static values used in the Barrett reduction method and by using a special form of the modulus, the calculation of reducing a number modulo another number can be reduced. This can result in a decrease in computation time, speeding up the overall cryptographic process.

Abstract: During high performance renormalization for video encoding, renormalization may involve detecting a leading number of ‘0’s in a range value of an input stream of symbols, a run of ‘1’s in an offset value of the input stream of symbols, and a run of ‘0’s following the run of ‘1’in the offset value. A bitstream may be outputted based on an iteration window for a number of renormalization iterations. The iteration window may comprise a bit range after the run of ‘1’s in the offset value, and the number of renormalization iterations may be based on the leading number of ‘0’s in the range value. A run of ‘1’s followed by one or more ‘0’s may be identified as a particular pattern.

Abstract: Systems and methods for effectively protecting data against differential fault analysis involved in Rivest, Shamir, and Adleman (“RSA”) cryptography using the Chinese Remainder Theorem (“CRT”) are described herein. A CRT RSA component facilitates modular exponentiation of a received message, and a verification component reconstructs the received message. An exponentiation component performs a first modular exponentiation and a second modular exponentiation of the received message. A recombination component performs a recombination step utilizing CRT computation as a function of the first and second modular exponentiations. A modular exponentiation component performs first and second public exponent derivations as a function of a private exponent. The verification component can reconstructs the received message as a function of the first and second public exponent derivations. The verification component calculates the received message utilizing Chinese Remainder Theorem computation.

Abstract: Apparatus for calculating a result of a modular multiplication of a first operand and a second operand with regard to a modulus, each having a length of 2 n bits, the operands and the modulus are split into sub-operands of half the length and are fed to controller controlling MMD unit for performing a MultModDiv operation in accordance with a predetermined step sequence with corresponding input operands and MMD moduli to obtain integer quotient values and residual values with regard to the MMD modulus at an output. The combiner is operable to combine integer quotient values and residual values from predetermined steps of the step sequence to obtain the result.

Abstract: A description of techniques of determining a modular remainder with respect to a polynomial of a message comprised of a series of segments. An implementation can include repeatedly accessing a strict subset of the segments and transforming the strict subset of segments to into a smaller set of segments that are equivalent to the strict subset of the segments with respect to the modular remainder. The implementation can also include determining the modular remainder based on a set of segments output by the repeatedly accessing and transforming and storing the determined modular remainder.

Abstract: In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

Abstract: A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=to M?2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yi+1,i of the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.

Abstract: A method of reducing power consumption and/or enhancing computation speed in the modulus multiplication operation of a Montgomery modulus multiplication module. A coding scheme reduces the need for an adder or memory element for obtaining multiple modulus values, and the use of carry save addition with carry propagation addition enhances the computational speed of the multiplication module.

Abstract: An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.

Abstract: A method of performing modular multiplication of integers X and Y to produce a result R, where R=X.Y mod N, in a multiplication engine. X is fragmented into a first plurality of words xn each having a first predetermined number of bits, k and Y is fragmented into a second plurality of words yn each having a second predetermined number of bits, m. Multiples of a word xn of X are derived in a pre calculation circuit and subsequently used to derive products of the word xn of X with each of the plurality of words yn of Y. An intermediate result Rjis calculated as a cumulating sum derived from said pre-calculated multiples and the steps repeated for each successive word of X so as to generate successive intermediate results, Rj, for each of the first plurality of words xn. The final result, R is obtained from the last of the intermediate results Rn?1.

Abstract: A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.

Abstract: The subject invention pertains to a method and apparatus for performing computations using residue arithmetic. The subject method and apparatus can utilize logic gates for performing calculations such as multiplication by a constant, computing a number theoretic logarithm of a residue for a given base ?i and modulus pi, and computing the product of two residues, modulo pi. The use of logic gates can offer advantages when compared with the use of ROMs for table look-up functions in integrated Residue Number System digital signal processor implementations.

Abstract: Provided are a modular multiplication method with an improved arithmetic operation, a modular multiplier and a cryptograph calculating system having the modular multiplier. The modular multiplication method comprises performing a first arithmetic operation including a first multiplication on a first bit string of a multiplicand and a first bit string of a multiplier and a first reduction for eliminating partial bits of the first multiplication result, performing a second arithmetic operation including a second multiplication on a second bit string of the multiplicand and a second bit string of the multiplier and a second reduction for eliminating partial bits of the second multiplication result, and calculating a modular multiplication result using the result of the first arithmetic operation and the result of the second arithmetic result. The first arithmetic operation and the second arithmetic operation are independently performed.

Abstract: A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines method wherein two lines DATAFALSE and DATATRUE are used to represent one binary data such that in order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSE line, and a logical low signal is applied to the DATATRUE line. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSE line, and a logical high signal is applied to the DATATRUE line. That is, when the data is represented by the asynchronous dual rail lines method, whatever the binary data value is, the same number of logical high states and logical low states are generated. As a result, whatever binary data is to be operated, the power consumption difference of the circuit is minimized.

Abstract: This invention concerns an improved modular reduction device. The modular reduction device includes a multiplier using an alternative of the Montgomery multiplication process using a high numeration base r with r being equal to or greater than 4. It applies more particularly to the calculation components used for asymmetrical cryptography.

Abstract: An elliptic curve processing apparatus that performs operations on elliptic curves specified over binary polynomial fields includes a functional unit that has a digit serial multiplier with a digit size of at least two bits. The elliptic curve processing apparatus performs reduction for respective generic curves using arbitrary irreducible polynomials, which correspond to respective ones of the generic curves. The elliptic curve processing apparatus may include hardwired reduction circuits in the functional unit for use with respective named curves. A storage location in the elliptic curve processing apparatus may be used to specify whether an operation is for one of the named curves or for one of the generic curves.

Abstract: Methods and apparatus for an encryption processor for performing accelerated computations to establish secure network sessions. The encryption processor includes an execution unit and a decode unit. The execution unit is configured to execute Montgomery operations and including at least one adder and at least two multipliers. The decode unit is configured to determine if a square operation or a product operation needs to be performed and to issue the appropriate instructions so that certain multiply and/or addition operations are performed in parallel in the execution unit while performing either the Montgomery square or Montgomery product operation.

Abstract: Methods to create an implementation for a multi-input n-state logic function with at least one inverter at an input by modifying the truth table according to the inverter into a reduced truth table are provided. Implementations of the reduced truth table by gates and inverters are also disclosed. Applying reduced truth tables in n-state multiplications are also provided. N-state multiplications may be used in filters, Digital Signal Processing or in Linear Feedback Shift Registers (LFSRs). Using implementations of reduced truth tables in n-state multiplications are disclosed.

Abstract: Generation a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a first partial remainder, which has a fixed width greater than or equal to the width of the second polynomial, from the first polynomial excepting a least significant portion. The first adder is adapted to generate a sum of the least significant portion of the first polynomial and a most significant portion of the first partial remainder. The second sub-circuit is adapted to generate a second partial remainder from the sum. The second adder is adapted to generate the remainder from the second partial remainder and the first partial remainder excepting the most significant portion.

Abstract: A scalar multiplication can be performed on an elliptic curve cryptosystem at a high speed. P is set as an initial value of Q[0], and 2×P is set as an initial value of Q[1]. An elliptic curve doubling ECDBL of Q[d[i]] is performed, and an arithmetic result is stored in Q[2]. An elliptic curve addition ECADD of Q[0] and Q[1] is performed, and an arithmetic result is stored in Q[1]. Q[2?d[i]] is stored in Q[0]. Q[1+d[i]] is stored in Q[1]. The elliptic curve addition ECADD and the elliptic curve doubling ECDBL are concurrently performed in the respective processors.

Abstract: A device for converting a term comprising a product of a first operand and a second operand into a representation having an integer quotient regarding a modulus and a remainder, the integer quotient being defined by T/N, T being the term and N being the modulus, and the remainder being defined by T mod N, N being the modulus. The device modularly reduces the term using the modulus on the one hand and modularly reduces the term using an auxiliary modulus, which is greater than the modulus, on the other hand to obtain the remainder on the one hand and the auxiliary remainder on the other hand. Both the remainder and the auxiliary remainder are combined to obtain the integer quotient. The inventive device makes it possible to calculate even the integer quotient, that is the result of the divide (DIV) operation, by performing a command for a modular multiplication existing on conventional cryptoprocessors two times.

Abstract: A method is provided for coherently demodulating a chaotic sequence spread spectrum signal at a receiver (104). The method includes receiving a chaotic sequence spread spectrum signal including a plurality of information symbols. The method also includes generating a first string of discrete time chaotic samples. The first string of discrete time chaotic samples is identical to a second string of discrete time chaotic samples generated at a transmitter. The method further includes processing the chaotic sequence spread spectrum signal at the receiver to identify a time offset and a frequency offset relative to the first string of discrete time chaotic samples. Each of the discrete time chaotic samples of the first string of discrete time chaotic samples has a shorter sample time interval than the duration of the information symbols.

Abstract: In an arithmetic device which performs a multiplication of a multiplicand A and a multiplier B expressed by bit patterns using a secondary Booth algorithm, an encoder selects a partial product indicating ?A when the value of i specifying three consecutive bits of B is 0, and selects a partial product indicating 0 when the value of i is not 0. An addition circuit generates a two's complement of A from the partial product indicating ?A, and outputs it as a multiplication result.

Abstract: Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.

Abstract: The computation time to perform scalar point multiplication in an Elliptic Curve Group is reduced by modifying the Barrett Reduction technique. Computations are performed using an N-bit scaled modulus based a modulus m having k-bits to provide a scaled result, with N being greater than k. The N-bit scaled result is reduced to a k-bit result using a pre-computed N-bit scaled reduction parameter in an optimal manner avoiding shifting/aligning operations for any arbitrary values of k, N.

Abstract: Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.

Abstract: A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.

Abstract: In a circuit which adds a partial product {?(Aj*B)*2^j (j=0, . . . , m?1)} to a provisional remainder u by using a value of inferior m bits (m is an integer not less than 2) of a number to be multiplied A and a multiplier factor B, there is provided a multiplication remainder calculator which shifts inferior m bits of a provisional remainder u by continuously connecting m stages of processing circuits which perform addition of a modulus N and one-bit shift, and calculates a Montgomery product of the number to be multiplied A and the multiplier factor B by repeating this processing, wherein a multiple number of the multiplier factor can be calculated by inhibiting one-bit shift of the processing circuits.

Abstract: A method is provided for masking a process used in generating a number sequence. The method includes generating a first sequence of numbers contained within a Galois field GF[M]. The method also includes performing a first modification to a first number in the first sequence of numbers. The first modification includes summing the first number with a result of a modulo P operation performed on a second number of the first sequence that proceeds the first number. M is relatively prime with respect to P. The method further includes performing a second modification to the first random number. The second modification is comprised of a modulo P operation. This second modification is performed subsequent to the first modification. The method includes repeating the first and second modification for a plurality of numbers comprising the first sequence of numbers to generate a second sequence of numbers.

Abstract: A method is provided for generating a coherent chaotic sequence spread spectrum communications system. The method includes phase modulating a carrier with information symbols. The method also includes generating a string of discrete time chaotic samples. The method further includes modulating the carrier in a chaotic manner using the string of discrete time chaotic samples. Each of the discrete time chaotic samples has a shorter sample time interval than the duration of the information symbols. The generating step includes selecting a plurality of polynomial equations. The generating step also includes using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The generating step further includes determining a series of digits in the weighted number system based on the RNS residue values.

Abstract: Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.

Abstract: A method is provided for extending a sequence repetition period of a random number generator in systems based on the availability of random sequences. The method includes performing RNS arithmetic operations to express a random number in a sequence as RNS residue values. Each generated random number has a value between zero and n!?1. The method also includes converting each of the RNS residue values to a relatively prime base number system so that each of the RNS residue values includes at least one digit. The method further includes generating an arbitrary permutation ordering of output sequence numbers using a select combination of digits associated with each of the RNS residue values. The arbitrary permutation ordering is applied to a cyclic structure having n elements. Each of the n elements has an associated output sequence number.

Abstract: A method is provided for generating a chaotic sequence. The method includes selecting a plurality of polynomial equations. The method also includes using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The method further includes determining a series of digits in a weighted number system (e.g., a binary number system) based on the RNS residue values. According to an aspect of the invention, the method includes using a Chinese Remainder Theorem process to determine a series of digits in the weighted number system based on the RNS residue values. According to another aspect of the invention, the determining step comprises identifying a number in the weighted number system that is defined by the RNS residue values.

Abstract: A method of factoring numbers in a non-binary computation scheme and more particularly, a method of factoring numbers utilizing a digital multistate phase change material. The method includes providing energy in an amount characteristic of the number to be factored to a phase change material programmed according to a potential factor of the number. The programming strategy provides for the setting of the phase change material once for each time a multiple of a potential factor is present in the number to be factored. By counting the number of multiples and assessing the state of the phase change material upon execution of the method, a determination of whether a potential factor is indeed a factor may be made. A given volume of phase change material may be reprogrammed for different factors or separate volumes of phase change material may be employed for different factors.

Abstract: A computer hardware implemented cryptography method computes a modular exponentiation, M:=Cd (mod p·q) upon a message data value C using a Chinese Remainder Theorem (CRT) based technique. To secure against cryptanalysis,, the private key moduli p and q are transformed by multiplication with a generated random value s, so that p?:=p·s and q?:=q·s. The CRT steps of the modular exponentiation are applied using the transformed moduli p? and q? to obtain a random intermediate message data value M?. A final reduction of M? modulo p·q yields the final message data value M. Values needed for the computation are loaded into data storage and accessed as needed by electronic processing hardware.

Abstract: In side-channel attack-resistant encoding methods, a return value (r) is determined as the modular inverse of an input value (a), by a module (M). A resistance to side-channel attack can be achieved with minimal restrictions on implementation on determination of the modular inverse with minimal technical complexity. To this end, in a first sub-step, a first product (d) of the input value (a) and a random number is generated (c), in a second sub-step, the modular inverse (e) of the first product (d) is determined by the module (M), in a third sub-step, a second product (b) of the random number (c) is determined by the modular inverse (e) and in a fourth sub-step the return value (r) is set to the same as the second product (b).

Abstract: Systems and methods provide a content encryption schema for integrating digital rights management (DRM) in a multicast/broadcast encryption system. In one implementation, an exemplary integrated key schema provides content encryption keys that can be employed by a multicast or broadcast process, while providing DRM protection of recorded multicast content via a single DRM decryption secret. The integrated key schema provides high security and allows encrypted multicast content to be saved directly to local files. A license server can efficiently manage and generate DRM keys to be delivered to clients because only a single key needs to be delivered per license to a client. The integrated key schema can be applied together with conventional broadcast or multicast encryption techniques.

Abstract: A data processing system, which is particularly useful for carrying out modular multiplication, especially for cryptographic purposes, comprises a plurality of independent, serially connected processing elements which are provided with data in a cyclical fashion via a control mechanism that is capable of transferring data from a set of registers to earlier ones in the series of the serially connected processing elements, at the end of a predetermined number of cycles.

Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: A method for the secure application of a cryptographic algorithm of the RSA type in an electronic component obtains the value of a public exponent e from a given set of probable values, without a priori knowledge of that value. Having determined the value for the public exponent e, the application of countermeasures using the value of e, to block error attacks and side channel attacks, particularly of the DPA and SPA type, are carried out on the application of a private operation of the cryptographic algorithm.

Abstract: A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomised to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

Abstract: The method for high-speed modulo multiplication is a method for multiplying integers A and B modulus N that is optimized for high speed implementation in an electronic device, which may be implemented in software, but is preferably implemented in hardware. The multiplication is performed on devices requiring no more than k+2 bits, where k is the number of significant bits in A, B, and N. The method computes the running product biiAW, where AW is either A when the previous running product is negative, or W when the previous running product is positive, W being the N-conjugate of A formed by A?N. On each iteration, the magnitude of the running product is reduced by a scaling factor no greater than 2N according to the state of the two most significant bits of the running product when carry propagate adders are used.

Abstract: A modular multiplication method implemented in an electronic digital processing system takes advantage of the case where one of the operands W is known in advance or used multiple times with different second operands V to speed calculation. The operands V and W and the modulus M may be integers or polynomials over a variable X. A possible choice for the type of polynomials can be polynomials of the binary finite field GF(2N). Once operand W is loaded into a data storage location, a value P=?W·Xn+?/M? is pre-computed by the processing system. Then when a second operand V is loaded, the quotient q? for the product V·W being reduced modulo M is quickly estimated, q?=?V·P/Xn+??, optionally randomized, q?=q??E, and can be used to obtain the remainder r?=V·W?q?·M, which is congruent to (V·M) mod M. A final reduction can be carried out, and the later steps repeated with other second operands V.

Abstract: A data cryptographer encrypts and decrypts character data of any given length using derivative equations and factors. The use of factors and derivative equations introduces the randomness required for effective encryption without the use of complex mathematics. A set of equations determined by the user is used in a manner similar to a key but with random results. Only a portion of the key is exposed to decrypt the encrypted information. The data cryptographer may be configured using either simple or complex equations and may be implemented in an unlimited number of variations. The data cryptographer is portable, and can be implemented in any programming language that supports cyclical character manipulation. The data cryptographer also supports input from a variety of sources, allowing control from the administrator side, string value side, or any other input that may be extracted from the desired programming language.

Abstract: A modular arithmetic apparatus has a plurality of base parameter sets in read only memories. A base selection unit in the modular arithmetic apparatus selects one of the base parameters sets according to an input modulus p. A plurality of operation units 30, in the modular arithmetic apparatus, perform an arithmetic operation according to the selected base parameter set in parallel and obtain an arithmetic result.

Abstract: The invention relates to method of performing a modular multiplication using numbers with 2n bits. The method includes the steps of breaking the numbers (A, B) down into a 2n base or a U base, U being a suitable integer; and, subsequently, performing MultModDiv—and/or MultModDivlnit-type elementary operations on the numbers with n bits resulting from the first step. The invention also relates to a method of calculating a Euclidean multiplication/division. The invention can be used for cryptographic calculations.

Abstract: An apparatus and method for single instruction multiple data (SIMD) modular multiplication are described. In one embodiment, the method includes selection of modular multiplication method available from an operating environment. Once the multiplication method is selected, a data access pattern for processing of data is selected. Finally, the selected modular multiplication method is executed in order to process data according to the selected data access pattern. In a further embodiment, a SIMD modular multiplication instruction is provided in order to enable simultaneous modular multiplication of multiplicand and multiplier operands, which may be vertically or horizontally accessed from memory, as indicated by a selected data access pattern. Alternatively, modular multiplication is implemented utilizing a SIMD byte shuffle operation, which enables modular multiplication of a constant multiplicand value to varying data multiplier values.