Abstract: An exponent calculation apparatus calculates xe based on input two integers x and e. A pre-calculation module pre-calculates x^{l_i} for each of candidate exponents {l_i} (0?i?L?1) stored in a candidate exponents storing unit, the number of the candidate exponents being L, and stores the obtained values x^{l_i} in a pre-calculated values storing unit. A dividing module divides the integer e into a plurality of values {f_i} (0?i?F?1) so that each of the values {f_i} corresponds to one of the candidate exponents {l_i}. A sequential processing module sequentially updates a calculation result c, which is stored in a calculation result storing unit, for each of the values {f_i} by using each of the values x^{l_i}. The updated calculation result c for each of the values {f_i} is output as xe. Accordingly, the amount of pre-calculation and table size can be reduced and thus the number of calculations can be reduced.

Abstract: A communications protocol is used to provide data privacy, message integrity, message freshness, and user authentication to telemetric traffic, such as to and from implantable medical devices in a body area network. In certain embodiments, encryption, message integrity, and message freshness are provided through use of token-like nonces and ephemeral session-keys derived from device identification numbers and pseudorandom numbers.

Abstract: Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extract a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent scaling value. The residuary subset bitfield value is part of a range of contiguous bits that is associated with upper and lower boundary bit-position values that are part of the compound exponent scaling value. The methods and apparatus determine the remainder value based on the residuary subset bitfield value.

Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.

Abstract: A system and method for computing A mod (2n?1), where A is an m bit quantity, where n is a positive integer, where m is greater than or equal to n. The quantity A may be partitioned into a plurality of sections, each being at most n bits long. The value A mod (2n?1) may be computed by adding the sections in mod(2n?1) fashion. This addition of the sections of A may be performed in a single clock cycle using an adder tree, or, sequentially in multiple clock cycles using a two-input adder circuit provided the output of the adder circuit is coupled to one of the two inputs. The computation A mod (2n?1) may be performed as a part of an interleaving/deinterleaving operation, or, as part of an encryption/decryption operation.

Abstract: The present invention aims at providing a novel enciphering and deciphering apparatus and an enciphering and deciphering method related thereto, which are respectively capable of contracting the time required for enciphering and deciphering processes and decreasing the number of logic gates provided in the apparatus. Essentially based on an equation Xki=1+?((J=1, i)iCj·Xk?1j) and also based on an initial value consisting of a group of power raising values Xk0j corresponding to j=1 through m in relation to k?1=k0, an arithmetic operating unit 21 seeks a second expression Yk1 by serially computing a group of power raising values Xki corresponding to i=1 through m in relation to one unit of k shown in the above equation in a range from k=k0+1 up to k=k1 by applying binomial coefficients stored in a coefficient memory unit 17.

Abstract: Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulis-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.

Abstract: Methods for determining whether an arbitrary elliptic curve over a binary field is secure, by using a novel non-converging Arithmetic-Geometric Mean iteration to determine the exact number of points on the curve. The methods provide rapid generation of secure curves for Elliptic-Curve Cryptography by selecting a secure curve from among candidate curves with the new method. The secure curve chosen is a curve whose number of points, is found to be divisible by a large prime number. The number of points on candidate curves is computed by a first phase, which lifts the curve to a certain related curve, followed by a second phase, which computes a certain norm that yields the result. The new Arithmetic-Geometric Mean iteration is used for the lifting phase or for the norm phase or for both.

Abstract: An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register position. Values of the working register are shifted multiple positions during a single loop iteration, and a shifted result is subtracted and compared to zero to determine subsequent contents of the working register.

Abstract: A modular multiplication apparatus comprises a calculation unit which comprises processing units including a multiplier-adder unit and performs a modular multiplication by carrying out pipeline processes by the processing units; and a calculator configured to, before a first pipeline process, carry out a predetermined calculation for a processing result of one of the processing units in a pipeline process immediately before the first pipeline process, and when the first pipeline processes supply a calculation result of the predetermined calculation to a processing unit at an initial stage of the first pipeline process.

Abstract: Integrated circuit parallel multiplication circuits, including multipliers that deliver natural multiplication products and multipliers that deliver polynomial products with coefficients over GF(2). A parallel multiplier hardware architecture arranges the addition of partial products so that it begins in a first group of adder stages that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms is deferred until a second group of adder stages arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product to be extracted from the results of the first group of additions, and the natural product to be extracted from the results of the second group of additions.

Abstract: A method and a circuit for masking digital data handled by an algorithm and factorized by a residue number system based on a finite base of numbers or polynomials prime to one another, comprising making the factorization base variable.

Abstract: In a device for calculating a result of a modular exponentiation, the Chinese Residue Theorem (CRT) is used, wherein two auxiliary exponentiations are calculated using two auxiliary exponents and two sub-moduli. In order to improve the safety of the RSA CRT calculations against cryptographic attacks, a randomization of the auxiliary exponents and/or a change of the sub-moduli are performed. Thus, there is a safe RSA decryption and RSA encryption, respectively, by means of the calculating time efficient Chinese Residue Theorem.

Abstract: A method and apparatus for efficiently deriving modulo arithmetic solutions for frequency selection in transceivers. A frequency for communication between a wireless user interface device and a wirelessly enabled host is generated by calculating a modulo solution for an input variable. In some embodiments of the invention, the communication between the user input device and the wirelessly enabled host complies with the Bluetooth wireless communication standard. For the embodiments of the present invention relating to communications systems implementing the Bluetooth standard, a method and apparatus is disclosed for generating communication frequencies based on modulo 23 and modulo 79 solutions input variables. The method and apparatus of the present invention can generate the communication frequency with a minimum number of calculations using simple binary addition, as opposed to prior art methods that generally require numerous iterations and complex calculations.

Abstract: A method, apparatus, and article of manufacture provide the ability to rapidly generate a large prime number to be utilized in a cryptographic key of a cryptographic system. A candidate prime number is determined and a mod remainder table is initialized for the candidate prime number using conventional mod operations. If all mod remainder entries in the table are non-zero, the candidate number is tested for primality. If the candidate prime number tests positive for primality, the candidate number is utilized in a cryptographic key of a cryptographic system. If any of the table entries is zero, the candidate number and each mod remainder entry are decremented/incremented. If any mod remainder entry is less than zero or greater than the corresponding prime number, the corresponding prime number is added/subtracted to/from the mod remainder. The process then repeats until a satisfactory number is obtained.

Abstract: A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

Abstract: A data encryption method performed with ring arithmetic operations wherein a modulus C is be chosen of the form 2w?L, wherein C is a w-bit number and L is a low Hamming weight odd integer less than 2(w?1)/2. And in some of those embodiments, the residue mod C is calculated via several steps. P is split into 2 w-bit words H1 and L1. S1 is calculated as equal to L1+(H12x1)+(H12x2)+ . . . +(H12xk)+H1. S1 is split into two w-bit words H2 and L2. S2 is computed as being equal to L2+(H22x1)+(H22x2)+ . . . +(H22xk)+H2. S3 is computed as being equal to S2+(2x1+ . . . +2xk+1). And the residue is determined by comparing S3 to 2w. If S3<2w, then the residue equals S2. If S3?2w, then the residue equals S3?2w.

Abstract: To provide a modular multiplication method and a calculating device that do not rely on the Montgomery technique, wherein the number of times of multiply-add calculations is reduced to shorten a calculation time for calculation speed-up, there is no limitation in input value, and it is possible to execute a remainder calculation exceeding the calculable maximum bit length of a multiply-add unit that is used. Assuming that N=2n?M and X=?×2n+?, a relation of XmodN=(?×M+?)modN is derived, which is utilized. n represents a maximum bit number where “1” is assigned in N, a solution of 2n+1modN is set as b, A×B is set as X, XmodN is transferred to (X/2n+1×b+Xmod2n+1)modN and further transferred to (X·n/2n+1×b+X·nmod2n+1)modN, calculations of X·n/2n+1×b+X·nmod2n+1 are repeated until a bit length of X·n becomes n+1, X·n?N is derived and a derived result is set as a solution of “A×BmodN”.

Abstract: A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

Abstract: A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent of the number of bits of the divisor in the modulo operation. Two requirements of the non-iterative technique are that the value of the divisor D should be equal to 2n?1 (where n is the number of bits of the divisor D) and the value of the dividend N should be less than or equal to (D?1)2, but greater than or equal to zero. If these two conditions are met, the remainder R of N mod D is determined by summing the upper n 2 and lower n 2 bits of the dividend N.

Abstract: A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A?B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction is accomplished in the processor by successively subtracting the largest possible multiple of the modulus N obtainable by bit shifting prior to subtraction.

Abstract: A method of modular exponentiation includes receiving as input a first number, a second number, and a modulus for calculating a residue of a product of the first number times the second number modulo the modulus; partitioning the first number into a selected number of pieces; calculating a first product of one of the pieces times the second number; adding a previous intermediate result to the first product to generate a first sum; shifting the first sum by a selected number of bit positions to generate a second product; and reducing a bit width of the second product to generate an intermediate result wherein the intermediate result has a bit width that is less than a bit width of the second product and has a residue that is identical to a residue of the second product modulo the modulus.

Abstract: A division operation is simulated by performing multiple subtractions, in parallel, each of which represents the subtraction of a different multiple of the divisor from the dividend. Each subtraction produces a possible remainder value, but only one subtraction will result in a valid remainder—the one representing the divisor multiplied by the actual quotient that would result from the division operation—and that remainder is then identified as the modulo output of the division operation.

Abstract: A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to be discarded appears during the calculation, a write into K register is performed, so that current in a write operation flows thereby improving immunity against Power Analysis.

Abstract: An emod operation is a computational substitute for a traditional modulus operation, one that is computationally less expensive but also less precise. Where a modulus operation may be defined for some base number n, the emod operation determines a modulus of an operand using a “phantom modulus,” one that is an integer multiple of n. The phantom modulus is chosen to make emod calculations computationally inexpensive when compared to a modulus operation. Thus, the emod operation is particularly useful for multiplications or exponential operations using very large operands. Upon conclusion of interstitial processing associated with the multiplications or exponential operations, a single, traditional modulus operation may be used to obtain a final result.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi–mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus.

Abstract: An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x?2n/2m is satisfied. When an arithmetic precision of 2n1 bits (where n1?n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1?2n1/2m (where x1 is a natural number and is variable) is satisfied.

Abstract: A residue computing device on a Galois Field, for calculating a residue of a product of a multiplier factor and a multiplicand under a modulo, includes a gate for allowing the multiplier factor to pass therethrough when a leading bit of the multiplicand is 1, an adder for adding a temporary residue and a value obtained by the passage, a gate for allowing the modulo to pass therethrough when a leading bit of a summed value of the adder is 1, and a subtractor for subtracting the modulo from the summed value of the adder when the leading bit of the summed value is 1, wherein a process for setting a value obtained by shifting a subtracted value of the subtractor by one bit, as the temporary residue on the basis of the next clock is repeatedly performed for each clock to thereby calculate the residue.

Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.

Abstract: Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner.

Abstract: Methods and apparatus for modular arithmetic operations with respect to a modulus p include representing operands as a series of s w-bit numbers, wherein s = ? k w ? . Operations are executed word by word and a carry, borrow, or other bit or word is obtained from operations on most significant words of the operands. Depending on the value of this bit or word, an operation-specific correction factor is applied. Cryptographic systems include computer executable instructions for such methods. Bit-level operations are generally avoided and the methods and apparatus are applicable to systems based on, for example, public-key cryptographic algorithms defined over the finite field GF(p).

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: Cryptographic methods and apparatus are provided for determination of multiplicative inverses. A Montgomery radix is selected based on a wordsize, permitting word-wise Montgomery multiplication. Using word-wise Montgomery multiplication, methods and apparatus determine various multiplicative inverses with reduced computation time.

Abstract: Scalable Montgomery multiplication methods and apparatus are provided that are reconfigurable to perform Montgomery multiplication on operands having arbitrary data precision. The methods perform Montgomery multiplication by combining bit-wise and word-wise operations and exhibit pipelined and parallel operation. Apparatus include a control unit that directs bits of an operand to processing elements that receive words of a second operand and a modulus, and produce intermediate values of a Montgomery product. After an intermediate value of a word of a Montgomery product is obtained in a first processing element based on a selected bit of the first operand, the intermediate value is directed to a second processing element and is updated based on another selected bit of the first operand.

Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.

Abstract: A method and apparatus for Montgomery multiplication comprising adding at least one multiplicand bit from a first multiplicand add multiplexer in a main array of a Montgomery multiplier with at least one modulus bit from a first modulus-add multiplexer in the main array; adding at least one modulus bit from a first modulus-add multiplexer in a quotient pre-calculation array with at least one modulus bit from a second modulus-add multiplexer in the quotient pre-calculation array; pre-calculating the quotient during a first cycle; and sending at least one value to control the first modulus-add multiplexer in the main array, the first modulus-add multiplexer in the quotient pre-calculation array, and the second modulus-add multiplexer in the quotient pre-calculation array so that the value of the quotient is evenly divisible by the radix during a second cycle through the Montgomery multiplier.

Abstract: In a data processing method, a remainder R that is produced during the division of an integer A by a prescribed integer B is calculated recursively. For this purpose, a data symbol word representing the integer A is decomposed into K data symbol part-words W0, W1, . . . , WK?1 of word length L, and in each recursion step a function F determined by the numbers B and L is applied to an argument that depends on the function value Fi?1 obtained in the preceding recursion step, and on a data symbol part-word WK?i.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: A method for determining a result of a group operation performed an integral number of times on a selected element of the group, the method comprises the steps of representing the integral number as a binary vector; initializing an intermediate element to the group identity element; selecting successive bits, beginning with a left most bit, of the vector. For each of the selected bits; performing the group operation on the intermediate element to derive a new intermediate element; replacing the intermediate element with the new intermediate element; performing the group operation on the intermediate element and an element, selected from the group consisting of: the group element if the selected bit is a one; and an inverse element of the group element if the selected bit is a zero; replacing the intermediate element with the new intermediate element.

Abstract: For calculating the result of an exponentiation Bd, B being a base and d being an exponent which can be described by a binary number from a plurality of bits, a first auxiliary quantity X is at first initialized to a value of 1. Then a second auxiliary quantity Y is initialized to the base B. Then, the bits of the exponent are sequentially processed by updating the first auxiliary quantity X by X2 or by a value derived from X2 and by updating the second auxiliary quantity Y by X*Y or by a value derived from X*Y, if a bit of the exponent equals 0. If a bit of the exponent equals 1, the first auxiliary quantity X is updated by X*Y or by a value derived from X*Y and the second auxiliary quantity Y is updated by Y2 or by a value derived from Y2. After sequentially processing all the bits of the exponent, the value of the first auxiliary quantity X is used as the result of the exponentiation. Thus a higher degree of security is obtained by homogenizing the time and current profiles.

Abstract: In a method for modular multiplication of a multiplicand by a multiplier using a modulus, l multiplication shift values are initially determined by means of a multiplication-lookahead method while taking into account l blocks of consecutive digits of the multiplier. Subsequently, l reduction shift values are determined by means of a reduction-lookahead method for the l blocks of digits of the multiplier. The l multiplication shift values and the l reduction shift values are applied to an intermediate result from a previous iteration step, to the modulus or to a value derived from the modulus, and to the multiplicand, so as to obtain the 2l+1 operands. By means of a multi-operands adder, the 2l+1 operands are combined to obtain an updated intermediate result for an iteration step following the previous iteration step, the iteration being continued for such time until all digits of the multiplier have been processed.

Abstract: A fast, scalable, systolic modular multiplier based on projection onto planar ring structures is presented. Systolic paradigms of limited fan-out on all signal paths and nearest neighbor interconnections guarantee optimally fast clock rates. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.

Abstract: A modular arithmetic apparatus has a plurality of base parameter sets in read only memories. A base selection unit in the modular arithmetic apparatus selects one of the base parameters sets according to an input modulus p. A plurality of operation units 30, in the modular arithmetic apparatus, perform an arithmetic operation according to the selected base parameter set in parallel and obtain an arithmetic result.

Abstract: A mobile terminal for use in a mobile communications system includes a SIM card storing subscriber related data. For security, the SIM card performs secret cryptographic calculations with secret numbers. Secret information is hidden from outside observation by scheduling the calculations using a precomputed, fixed randomization schedule in such a way that externally observable parameters of the device cannot be associated to particular pieces, bits, symbols or values of the secret information.

Abstract: A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathematic argument to obtain one or more final partial modulo products. The final partial modulo product is post-processed to obtain the final result.

Abstract: The disclosed technology of the present invention relates to an information processing device such as an IC card, and specifically to the overflow processing which occurs in a modular multiplication operation during crypto-processing. Such overflow processing exhibits a particular pattern of consumption current. It is the subject of the present invention to decrease the relationship between the data processing and the pattern of the consumption current. In the processing procedures for performing a modular exponentiation operation according to the 2 bit addition chain method, the modular multiplication operation to be executed is selected at random, the selected modular multiplication operation is executed for each 2 bits, the correction of the result is performed, and the result of the calculation (i.e, a corrected value or uncorrected value) is outputted.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: A method of factoring numbers in a non-binary computation scheme and more particularly, a method of factoring numbers utilizing a digital multistate phase change material. The method includes providing energy in an amount characteristic of the number to be factored to a phase change material programmed according to a potential factor of the number. The programming strategy provides for the setting of the phase change material once for each time a multiple of a potential factor is present in the number to be factored. By counting the number of multiples and assessing the state of the phase change material upon execution of the method, a determination of whether a potential factor is indeed a factor may be made. A given volume of phase change material may be reprogrammed for different factors or separate volumes of phase change material may be employed for different factors.

Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.