Abstract: A method of encrypting and decrypting multiple individual pieces or sets of data in which a computing device randomly selects a group of seeds that it then uses to generate irrational numbers. Sections of the generated irrational numbers can be used as one-time pads or keys to encrypt the corresponding data sets. Intended recipients can then reverse the process using their allowed keys to access data for which they have authorization.

Abstract: A processor to facilitate execution of a single-precision floating point operation on an operand is disclosed. The processor includes one or more execution units, each having a plurality of floating point units to execute one or more instructions to perform the single-precision floating point operation on the operand, including performing a floating point operation on an exponent component of the operand; and performing a floating point operation on a mantissa component of the operand, comprising dividing the mantissa component into a first sub-component and a second sub-component, determining a result of the floating point operation for the first sub-component and determining a result of the floating point operation for the second sub-component, and returning a result of the floating point operation.

Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.

Abstract: An improved phasor estimation method for M-class phasor measurement units (PMUs) with a low computational burden is described. The method contains three steps: 1) A phasor measurement filter is designed by selecting parameters of Taylor weighted least square method to prioritize dynamic phasor accuracy and a high level of suppression on high-frequency interferences; 2) A finite impulse response lowpass filter is designed by the equal-ripple method is put forward to suppress low-frequency interferences; and 3) Phasor amplitude is corrected under off-nominal conditions.

Abstract: Disclosed are a Multiple-Input Multiple-Output (MIMO) system-based signal detection method. The method includes: performing a scaling calculation on a first covariance matrix according to first main diagonal elements in the first covariance matrix to obtain a second covariance matrix; obtaining a whitening matrix according to the second covariance matrix; taking the whitening matrix, a vector of a receiving signal and a channel matrix as input parameters, and inputting the parameters into a mathematical model for a whitening operation and perform a whitening calculation to obtain an operation result; and detecting a transmit signal in a MIMO system according to the operation result to obtain a detection result. Also disclosed are a MIMO system-based signal detection device and a computer storage medium.

Abstract: An apparatus and method for performing a reciprocal square root. For example one embodiment of a processor comprises: a decoder to decode a reciprocal square root instruction to generate a decoded reciprocal square root instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal square root execution circuitry to execute the decoded reciprocal square root instruction, the reciprocal square root execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal square root execution circuitry to generate a reciprocal square root of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.

Abstract: The present embodiments relate to integrated circuits with circuitry that efficiently performs mixed-precision floating-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. The specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing blocks may implement fixed-point addition, floating-point addition, fixed-point multiplication, floating-point multiplication, sum of two multiplications in a first floating-point precision, with or without casting to a second floating-point precision and the latter followed by a subsequent addition in the second floating-point precision, if desired, just to name a few.

Abstract: The present disclosure provides a quick operation device for a nonlinear function, and a method therefor. The device comprises: a domain conversion part for converting an input independent variable into a corresponding value in a table lookup range; a table lookup part for looking up a slope and an intercept of the corresponding piecewise linear fitting based on the input independent variable or an independent variable processed by the domain conversion part; and a linear fitting part for obtaining, a final result in a way of linear fitting based on the slope and the intercept obtained, by means of table lookup, by the table lookup part. The present disclosure solves the problems of slow operation speed, large area of the operation device, and high power consumption caused by the traditional method.

Abstract: A binary logic circuit is provided for determining a rounded value of px q , where p and q are coprime constant integers with p<q and q?2i, i is any integer, and x is an integer variable between 0 and integer M where M?2q, the binary logic circuit implementing in hardware the optimal solution of the multiply-add operation ax + b 2 k where a, b and k are fixed integers.

Abstract: A target object may be identified by estimating a distribution of a plurality of orientations of a periphery of a target object, and identifying the target object based on the distribution.

Abstract: A reciprocal unit for computing an estimated reciprocal of a number represented by a bit string. The unit comprises a first lookup table configured to receive one or more of the bits in the bit string and to output an initial estimate of the reciprocal of the number. The unit further comprises a second lookup table configured to receive one or more of the bits in the bit string and to output the square of the initial estimate of the reciprocal of the number. The unit still further comprises a multiplier circuit configured to multiply the square of the initial estimate by the number, and an adder-subtractor circuit for subtracting the product of the multiplication from a scaled value of the initial estimate to determine a final estimate of the reciprocal of the number.

Abstract: The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are organized into specially ordered vectors, which are multiplied together to produce a portion of a product matrix.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: Systems and methods are provided for implementing a sparse deterministic direct solver. The deterministic direct solver is configured to identify at least one task for each of a plurality of dense blocks, identify operations on which the tasks are dependent, store in a first data structure an entry for each of the dense blocks identifying whether a precondition must be satisfied before tasks associated with the dense blocks can be initiated, store in a second data structure a status value for each of the dense blocks that is changeable by multiple threads, and assign the tasks to a plurality of threads, wherein the threads execute their assigned task when the status of the dense block corresponding to their assigned task indicates that the assigned task is ready to be performed and the precondition associated with the dense block has been satisfied if the precondition exists.

Abstract: Methods and circuitry for evaluating reciprocal, square root, inverse square root, logarithm, and exponential functions of an input value, Y. In one embodiment, an approximate value, RA, of the reciprocal of Y is generated. One Newton-Raphson iteration is performed as a function of RA and Y, resulting in a truncated approximate value, R. R is multiplied by Y and 1 is subtracted, resulting in a reduced argument, A. A Taylor series evaluation of A is performed, resulting in an evaluated argument, B. B is multiplied by a post-processing factor for the final result.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi-1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: A new function for calculating the reciprocal residual of a floating-point number X is defined as recip_residual(X)=1?X*recip(X), where recip(X) represents the reciprocal of X. The function may be implemented using a fused multiply-add unit in a processor. The reciprocal value of X, recip(X), may be obtained from a lookup table. The recip_residual function may help reduce the latency of many multiplicative functions that are based on products of multiple numbers and can be expressed in simple terms of functions on each individual number (e.g., log(U*V)=log(U)+log(V)).

Abstract: Methods and apparatuses for constructing a multi-level solver, comprising decomposing a graph into a plurality of pieces, wherein each of the pieces has a plurality of edges and a plurality of interface nodes, and wherein the interface nodes in the graph are fewer in number than the edges in the graph; producing a local preconditioner for each of the pieces; and aggregating the local preconditioners to form a global preconditioner.

Abstract: In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.

Abstract: Approximations of reciprocal square roots are provided in IEEE floating point binary format by obtaining an index from an input value, accessing a pair of table values and performing a limited number of simple and rapidly performed manipulations. The maximum relative error in the approximation thus provided is less than 0.75/2(2k+1) as compared with a maximum relative error of 1/2k+2 of known methods, where 2k is the number of table entries.

Abstract: A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain.

Abstract: A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain.

Abstract: A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.

Abstract: In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi-1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi?1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a divide or a square-root operation to produce a result, which includes one or more additional bits of accuracy beyond a desired accuracy for the result. Next, the system rounds the result to the desired accuracy to produce a rounded result t. The system then analyzes the additional bits of accuracy to determine whether t is correct and whether t is exact.

Abstract: A data processing apparatus and method generate an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value.

Abstract: In a first aspect, a first method of reciprocal estimate computation using floating point pipeline logic is provided. The first method includes the steps of (1) receiving an input value having an exponent and a mantissa when represented as a floating point number on which a reciprocal estimate computation is to be performed; (2) determining whether the exponent is one of a plurality of predetermined numbers; and (3) if the exponent is one of the plurality of predetermined numbers, adjusting at least one of a plurality of modified mantissa bits (e.g., mantissa bits internal to leading zero anticipator (LZA) logic) and the exponent so as to prevent an underflow result of the reciprocal estimate computation. Numerous other aspects are provided.

Abstract: A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.

Abstract: A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.

Abstract: A new function for calculating the reciprocal residual of a floating-point number X is defined as recip_residual(X)=1?X*recip(X), where recip(X) represents the reciprocal of X. The function may be implemented using a fused multiply-add unit in a processor. The reciprocal value of X, recip(X), may be obtained from a lookup table. The recip_residual function may help reduce the latency of many multiplicative functions that are based on products of multiple numbers and can be expressed in simple terms of functions on each individual number (e.g., log(U*V)=log(U)+log(V)).

Abstract: Approximations of reciprocal square roots are provided in IEEE floating point binary format by obtaining an index from an input value, accessing a pair of table values and performing a limited number of simple and rapidly performed manipulations. The maximum relative error in the approximation thus provided is less than 0.75/2(2k+1) as compared with a maximum relative error of 1/2k+2 of known methods, where 2k is the number of table entries.

Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

Abstract: Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

Abstract: A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set of Taylor's series coefficients for each segment of the input value range. Other aspects of the invention are methods for determining preferred parameters for elements of such a circuit, a circuit designed in accordance with such a method, and a system (e.g., a pipelined graphics processor) for and method of pipelined graphics data processing using any embodiment of the circuit. The preferred parameters are determined by minimizing the circuit's size subject to constraints on input and output value format and output accuracy, assuming a specific function to be approximated and a specific degree for the approximation but allowing variation of parameters such as coefficient width and number of input value range segments.

Abstract: A method and apparatus allows the quick computation of an estimate of the reciprocal of a floating point number in IEEE format. A table with 2k entries allows the computation of an estimate with 2×k+3 good bits. x is a floating point number in IEEE format for which a reciprocal approximation is to be computed. {circumflex over (x)} be a floating point number in IEEE format derived from x by leaving the sign bit unchanged, complementing the exponent bits, leaving the first k fraction bits unchanged, and complementing the remaining fraction bits. t is another floating point number in IEEE format found by using the first k bits of the fraction of x as an index into a table with 2k entries. The product {circumflex over (x)}×t computed with IEEE floating point arithmetic is an estimate of the reciprocal of x with 2×k+3 good bits (i.e., relative error less than 2?2×k+3).

Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.

Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.

Abstract: Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Three iterations produce a result with accuracy sufficient for computer graphic applications. The initial estimate and input operand are scaled to minimize final adjustments to the result mantissa and final exponent adjustments required by the algorithm are performed concurrently with any adjustment required by rounding. A pipelined implementation of the algorithm produces a result with a latency of 24 and a repeat rate of 21 clock cycles.

Abstract: The present invention provides apparatus, methods, and computer program products for non-iterative division and non-iterative reciprocal generation. In one embodiment, the present invention uses a logic network that determines the bits of the quotient of a divisor and dividend by using a non-iterative, (i.e., non trial and error), method. Further, in another embodiment, the present invention may determine the reciprocal of a number M by separating the number M into at least two numbers X, Y . . . Z so that M=X+Y+ . . . +Z. The reciprocal of M is computed according to an equation 1/M=F(X,Y . . . Z) or an approximation 1/M?G(X,Y . . . Z), where the approximation gives the correct value of the inverse of M to a predetermined accuracy. In some embodiments, the apparatus uses an equation that exactly describes the reciprocal or instead, it may include one or more memories for storing look-up tables containing pre-calculated parts of the equation.

Abstract: A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The approximation circuit is configured to generate an approximation of a difference of the first result from the multiplier and a constant. The control circuit is configured to approximate a function specified by a floating point instruction provided to the floating point unit for execution using an approximation algorithm. The approximation algorithm comprises at least two iterations through the multiplier and optionally the approximation circuit. The control circuit is configured to correct the approximation from the approximation circuit from a first iteration of the approximation algorithm during a second iteration of the approximation algorithm by supplying a correction vector to the multiplier during the second iteration. The multiplier is configured to incorporate the correction vector into the first result during the second iteration.

Abstract: The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (Xi); (b) determining a first intermediate result (IR1) according to the equation: IR1=1?N*Xi; (c) multiplying IR1 by Xi to produce a second intermediate result (IR2); and (d) adding Xi to IR2 to produce an approximation of the reciprocal of N. Approximating the reciprocal square root includes: (a) estimating the reciprocal square root of N to produce Xi; (b) multiplying Xi by N to produce IR1; (c) determining IR2 according to the equation: IR2=(1?Xi*IR1)/2; (d) multiplying IR2 by Xi to produce a third intermediate result (IR3); and (e) adding IR3 to Xi to produce an approximation of the reciprocal square root of the number.

Abstract: A method and apparatus for the calculation of the reciprocal of a normalized mantissa M for a floating-point input number D. A formula for determining the minimum size for the look-up table in accordance with the required precision is provided, as well as formulas for calculating look-up table entries. The look-up table stores the initiation approximations and the correction coefficients, which are addressed by the corresponding number of the mantissa's most significant bits and used to obtain the initial approximation of the reciprocal by means of linear interpolation requiring one subtraction operation and one multiplication operation. The result of the linear interpolation may be fed to a Newton-Raphson iteration device requiring, for each iteration, two multiplication operations and one two's complement operation, thereby doubling the precision of the reciprocal.

Abstract: Generally, a method and apparatus are provided for computing a matrix inverse square root of a given positive-definite Hermitian matrix, K. The disclosed technique for computing an inverse square root of a matrix may be implemented, for example, by the noise whitener of a MIMO receiver. Conventional noise whitening algorithms whiten a non-white vector, X, by applying a matrix, Q, to X, such that the resulting vector, Y, equal to Q·X, is a white vector. Thus, the noise whitening algorithms attempt to identify a matrix, Q, that when multiplied by the non-white vector, will convert the vector to a white vector. The disclosed iterative algorithm determines the matrix, Q, given the covariance matrix, K. The disclosed matrix inverse square root determination process initially establishes an initial matrix, Q0, by multiplying an identity matrix by a scalar value and then continues to iterate and compute another value of the matrix, Qn+1, until a convergence threshold is satisfied.

Abstract: A method and apparatus allows the quick computation of an estimate of the reciprocal of a floating point number in IEEE format. A table with 2k entries allows the computation of an estimate with 2×k+3 good bits. x is a floating point number in IEEE format for which a reciprocal approximation is to be computed. {circumflex over (x)} be a floating point number in IEEE format derived from x by leaving the sign bit unchanged, complementing the exponent bits, leaving the first k fraction bits unchanged, and complementing the remaining fraction bits. t is another floating point number in IEEE format found by using the first k bits of the fraction of x as an index into a table with 2k entries. The product {circumflex over (x)}×t computed with IEEE floating point arithmetic is an estimate of the reciprocal of x with 2×k+3 good bits (i.e., relative error less than 2−2×k+3).

Abstract: Operations that involve denormalized numbers are handled by restructuring the input values for an operation as normalized numbers, and performing calculations on the normalized numbers. As a first step in the process of performing an operation, a determination is made whether input values for the operation contain one or more denormalized numbers. For certain types of operations, a determination is made whether the input values are such that the output value from the operation will be a denormalized number. For each operation in which either the input values or output values comprise a denormalized number, the input values are scaled to produce values that are not denormalized. Once the appropriate factoring has been carried out, the requested operation is performed, using normalized numbers, to produce an intermediate result which is then adjusted to account for the initial scaling.

Abstract: A polynomial inverse computing apparatus comprises first to sixth registers, a left shift unit, first and second exclusive-OR units, a doubling computing unit which executes doubling computation in an extension field with characteristic 2, a halving computing unit which executes halving computation in the extension field of characteristic 2, a determination unit which determines whether or not a content of each register is 0, a decrement unit which decrements the content of each register, an increment unit which increments the content of each register.

Abstract: A digital signal system (10, 100) for determining an approximate reciprocal of a value of x. The system includes an input (12) for receiving a signal, and circuitry (18) for measuring an attribute of the signal. The measured attribute relates at least in part to the value of x. The system further includes circuitry (104) for identifying a bounded region within which x falls. The bounded region is one of a plurality of bounded regions, and each bounded region has a corresponding slope value and first and second endpoints. The system further includes circuitry (106, 108, 110) for determining the approximate reciprocal by adjusting a reciprocal value at one of the first and second endpoints by a measure equal to a distance of the value of x from the one of the first and second endpoints times the slope value corresponding to the bounded region within which x is identified as falling.

Abstract: A floating point inverse square root circuit is disclosed. The circuit is configured to receive a floating point value comprised of a sign bit, an exponent field, and a mantissa field. The inverse square root circuit includes a lookup table configured to receive at least a portion of the floating point value and further configured to generate an initial approximation (x0) of the inverse square root of the floating point value from the received portion of the floating point value. The inverse square root circuit further includes a first estimation circuit that receives the initial approximation from the lookup table and at least a portion of a value L derived from the floating point value mantissa field (M) and further configured to produce a first approximation (x1) of the floating point value's inverse square root based upon L and x0 where x1 is a more accurate estimate of the inverse square root than x0.