Abstract: A system that efficiently performs a CMOD operation in solving a system of equations involving a sparse coefficient matrix by identifying supernodes in the sparse matrix. Each supernode comprises a set of contiguous columns having a substantially similar pattern of non-zero elements. The system performs a CMOD operation on each supernode, by determining a structure for the supernode, and computing a function of the structure. The system uses a one-dimensional trapezoidal representation for the supernode during the CMOD operation, if the result of the function is lower than a threshold value, and otherwise uses a two-dimensional rectangular representation for the supernode. The function of the structure of the supernode is a function of a number of computational operations involved in computing a lower-triangular sub-block portion of the supernode and a number of computational operations involved in computing a rectangular sub-block portion of the supernode.

Abstract: An approximation circuit approximates a function f(x) of an input value “x” by adding at least the first two terms in a Taylor series (i.e., f(a) and f′(a)(x−a)) where “a” is a number reasonably close to value “x”. The first term is generated by a first look-up table which receives the approximation value “a”. The first look-up table generates a function f(a) of the approximation value “a”. The second look-up table generates a first derivative f′(a) of the function f(a). A first multiplier then multiplies the first derivative f′(a) by a difference (x−a) between input value “x” and approximation value “a” to generate a product f′(a)(x−a). The approximation circuit can approximate the function f(x) by adding the third term of the Taylor series, (½)f″(a)(x−a)2.

Abstract: Method for the cryptography of data recorded on a medium usable by a computing unit in which the computing unit processes an input information x using a key for supplying an information F(x) encoded by a function F. The function uses a decorrelation module Mk such that F(x)=[F′(Mk)](x), in which K is a random key and F′ a cryptographic function. This Abstract is neither intended to define the invention disclosed in this specification nor intended to limit, in any manner, the scope of the invention.

Abstract: A method and apparatus for the calculation of the reciprocal of a normalized mantissa M for a floating-point input number D. A formula for determining the minimum size for the look-up table in accordance with the required precision is provided, as well as formulas for calculating look-up table entries. The look-up table stores the initiation approximations and the correction coefficients, which are addressed by the corresponding number of the mantissa's most significant bits and used to obtain the initial approximation of the reciprocal by means of linear interpolation requiring one subtraction operation and one multiplication operation. The result of the linear interpolation may be fed to a Newton-Raphson iteration device requiring, for each iteration, two multiplication operations and one two's complement operation, thereby doubling the precision of the reciprocal.

Abstract: A division circuit which can shorten a critical path for division and can perform the division at a high speed, provided with a 1's complement processor for outputting a complement of 1 of a divisor when the divisor is negative; an adder for adding “1” to the output from the complement processor and making the result of addition an absolute value; a priority encoder for calculating a logarithmic value comprised of an integer value of a logarithm of 2 of the value output from the 1's complement processor, a shift processor for shifting the absolute value in accordance with the logarithmic value, making the shift processing value a mantissa when the MSB of the shift processing value is “1”, and making the shift processing value with an MSB replaced by “1” the mantissa when the MSB of the shift processing value is “0”, and a subtractor for determining the shift amount in response to the MSB of the shift processing value of the shift processor.

Abstract: The invention provides a system and method for improving the accuracy of approximating the reciprocal of a number and the reciprocal square root of a number. A method according to the present invention for approximating the reciprocal square root of a number (N) includes the steps of: (a) estimating the reciprocal square root of the number to produce an estimate (Xi); (b) multiplying Xi by N to produce a first intermediate result (IR1); (c) determining a second intermediate result (IR2) according to the equation: IR2=(1−Xi,*IR1)/2; (d) multiplying IR2 by Xi to produce a third intermediate result (IR3); and (e) adding IR3 to Xi to produce an approximation of the reciprocal square root of the number. This method provides one advantage because of the order in which the multiplication is performed makes it likely that all results will be in normalized form. Specifically, the Newton-Raphson algorithm requires one to determine the product of: N*Xi*Xi.

Abstract: An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

Abstract: A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X)={overscore (A)}ix2+{overscore (B)}ix+{overscore (C)}i, in each interval i. The reciprocal square root computation uses the piece-wise quadratic approximation in the form: 1/squareroot(X)=Aix2+Bix+Ci, in each interval i. The coefficients {overscore (A)}i, {overscore (B)}i, and {overscore (C)}i, and Ai, Bi, and Ci are derived for the square root operation and for the reciprocal square root operation to reduce the least mean square error using a least squares approximation of a plurality of equally-spaced points within an interval. In one embodiment, 256 equally-spaced intervals are defined to represent the 23 bits of the mantissa.

Abstract: A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

Abstract: A reciprocal generator is useful for perspective correction for 3D graphics. The input range is divided into many sections. A lookup table contains reciprocal outputs for only two of the sections, the smallest-inputs section and the largest-inputs section. Entries in the table for the smallest section contain a base and a scale factor to indicate the reciprocal value. One entry is provided for each possible input value in the smallest section. This provides high precision where the outputs have the largest values, reducing visible distortions caused by relatively small changes in the large output values. Each section is divided into intervals, with one table entry for each interval. For the largest section, each table entry has an initial reciprocal and a slope of a line approximating the reciprocal curve in that interval. Reciprocals for inputs within the interval are calculated by multiplying an offset into the interval by the slope, and then adding to the initial reciprocal for that interval.

Abstract: A multi-function look-up table for determining output values for predetermined ranges of a first mathematical function and a second mathematical function. In one embodiment, the multi-function look-up table is a bipartite look-up table including a first plurality of storage locations and a second plurality of storage locations. The first plurality of storage locations store base values for the first and second mathematical functions. Each base value is an output value (for either the first or second function) corresponding to an input region which includes the look-up table input value. The second plurality of storage locations, on the other hand, store difference values for both the first and second mathematical functions. These difference values are used for linear interpolation in conjunction with a corresponding base value in order to generate a look-up table output value.

Abstract: A method for generating entries for a bipartite look-up table having base and difference table portions. In one embodiment, these entries are usable to form output values for a mathematical function, f(x), in response to receiving corresponding input values within a predetermined input range. The method first comprises partitioning the input range into I intervals, J subintervals/interval, and K sub-subintervals/subinterval. For a given interval M, the method includes generating K difference table entries and J base table entries. Each of the K difference table entries corresponds to a particular group of sub-subintervals within interval M, each of which has the same relative position within their respective subintervals. Each difference table entry is computed by averaging difference values for the sub-subintervals included in a corresponding group N.

Abstract: An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The translation logic decodes the square root macro instruction into a plurality of prescribed-precision machine instructions according to the square root calculation precision specified by the plurality of square root instructions. The execution logic, coupled to the translation logic, receives the plurality of prescribed-precision machine instructions and calculates the square root of the operand according to the specified square root calculation precision. At least one of the plurality of square root instructions specifies the square root calculation precision such that less significant bits are calculated in the square root than are provided in the operand.

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1.ltoreq.x<2, and one lookup table is used, having an interval size of 1/32. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table). In another implementation, the input value is normalized within the range 0.5.ltoreq.

Abstract: Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively parallel processing system. A flexible addressing scheme supports data organizations which can vary widely, depending on the processing task. Different data organizations in memory are supported by a PE internal address having certain bits designated as the target PE number and the remaining bits designating the offset within that PE's local memory. The PE and offset bits are distributed throughout the PE internal address to achieve various data distributions throughout memory. When a transfer occurs, the PE number bits and offset bits are separated via the centrifuge under control of a software-supplied mask.

Abstract: A system and method of using a computer processor (34) to generate a solution to a linear system of equations is provided. The computer processor (34) executes a Jacobi iterative technique to produce outputs representing the solution. Multiplication operations required by the iterative technique are performed using logarithmic arithmetic. With logarithmic arithmetic, a multiplication operation is accomplished using addition. For a given n.times.n matrix A, the computer processor (34) can compute an inverse matrix A.sup.-1 by repeatedly executing the iterative technique to solve n linear systems.

Abstract: A method of effecting a matrix transpose operation in a computer is described. The method uses a computer instruction which restructures a data string by retaining first and last sub-strings of the data string in unchanged positions and interchanges the position of at least two intermediate sub-strings. The data string is formed from sub-strings each representing one or more data value in a matrix.The computer instruction can be effected in a single register store having a predetermined bit capacity addressable by a single address, or in a pair of such register stores.The data restructuring instructions include "flip", "zip" and "unzip" instructions.