Abstract: Systems and methods are described to create radio daisy chains for convenient and aesthetically pleasing high-density radio deployments.

Abstract: Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum.

Abstract: Systems and methods for time division duplex (TDD) synchronizing in distributed communication systems (DCSs) synchronize remote units operating with 5G signals by initially connecting these remote units to a 4G TDD source, and once the remote units are synchronized, switching back to a 5G TDD source. By using the downlink synchronization process of 4G instead of the normal synchronization process of 5G, the synchronization of the remote units using 5G is expedited. Further, the 5G receiver is not compressed or otherwise negatively impacted.

Abstract: In a multiply accumulate (MAC) unit, an accumulator may be implemented in two or more stages. For example, a first accumulator may accumulate products from the multiplier of the MAC unit, and a second accumulator may periodically accumulate the running total of the first accumulator. Each time the first accumulator's running total is accumulated by the second accumulator, the first accumulator may be initialized to begin a new accumulation period. In one embodiment, the number of values accumulated by the first accumulator within an accumulation period may be a user-adjustable parameter. In one embodiment, the bit width of the input of the second accumulator may be greater than the bit width of the output of the first accumulator. In another embodiment, an adder may be shared between the first and second accumulators, and a multiplexor may switch the accumulation operations between the first and second accumulators.

Abstract: In the subject architecture flexible binary arithmetic coding system, coding circuitry of an electronic device may receive video data that is to be coded (e.g., to be encoded or decoded) by binary arithmetic coding. The coding circuitry may also compute at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation (e.g., without performing a table look-up operation). The coding circuitry may perform binary arithmetic coding on the video data using the at least one of the LPS range or the MPS range. The computation of the LPS range and/or the MPS range using the multiplication operation may have a lower computational cost than using a table look-up operation.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

Abstract: Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

Abstract: Systems and methods for transmitting data using various Modulation on Zeros schemes are described. In many embodiments, a communication system is utilized that includes a transmitter having a modulator that modulates a plurality of information bits to encode the bits in the zeros of the z-transform of a discrete-time baseband signal. In addition, the communication system includes a receiver having a decoder configured to decode a plurality of bits of information from the samples of a received signal by: determining a plurality of zeros of a z-transform of a received discrete-time baseband signal based upon samples from a received continuous-time signal, identifying zeros that encode the plurality of information bits, and outputting a plurality of decoded information bits based upon the identified zeros.

Abstract: Aspects of the disclosure are directed to receiving numerical product data indicative of a product, the numerical product data comprising numerical values indicative of at least one of chemical composition, radius, tensile strength, a diameter, position and yield strength, and storing the numerical product data in a non-volatile memory device. The numerical product data is processed in a processor to create a plurality of explanatory variables indicative of the numerical product data. Multivariate data analysis is performed on the explanatory variables indicative of the numerical product data, where the multivariate data analysis includes an iterative cluster based outlier detection procedure. A confidence indicator value indicative of the likelihood that the numerical product data includes at least one fabricated or false data entry is generated.

Abstract: A method is provided for preventing dark data in a data set. At a time t1, a first version of the data set is received. The first version is analyzed and its parameters are gathered in a first statistical profile. The first statistical profile is stored. At a time t2, a second version of the data set is received. The second version is analyzed and its parameters are gathered in a second statistical profile. The second statistical profile is stored. The first and second statistical profiles are compared and a similarity index is created. If the similarity index exceeds a pre-set threshold, dissimilarity is flagged and a responsive action is taken.

Abstract: A mobile device comprises: a mesh loader manages configured to download compressed mesh sequences from a remote server into a local storage buffer; a mesh decoder that is configured to decode compressed mesh sequences into frames of meshes in real-time; a mesh decoder manager that is configured to request compressed mesh sequences from the mesh loader and to request the mesh decoder to decode the compressed mesh sequences; a player manager that is configured to decode texture video and to request corresponding decoded mesh from the mesh decoder manager and to maintain synchronizations between requesting the corresponding decoded mesh and decoding the texture video; and a renderer that is configured to render, using a rendering engine, the decoded mesh on a canvas; and a camera controller that is configured to detect one or more user actions and control a hardware camera in accordance with the one or more user actions.

Abstract: Data objects are sampled from data sources and stored in a tree data structure that is employed to compute histogram information. Each node in the tree includes sufficient statistics and a particular value corresponding to one or more sampled data objects. The nodes of the tree can be two or more types, such as exponential nodes and regular nodes. Also, each histogram tree may be precalculated to start with an empty exponential node, and a defined number of regular nested nodes that correlate to a precision value for the histogram, i.e., a number of significant figures for sampled data values that can be stored in the tree.

Abstract: A method of determining a quantum phase of quantum device including performing a plurality of measurements for cosine and sine components of the quantum phase; counting a number of measurements in a vertical axis for the sine component and counting a number of measurements in a horizontal axis for the cosine component; and determining the quantum phase based on a majority of a number of 0 measurements and a number of 1 measurements of the sine component and the cosine component.

Abstract: Inventive aspects include a high-precision log 1p( ) compute logic section of a computing machine to approximate a function F(x)=log 1p(x)=ln(x+1), using an estimation function E(x), and to at least: (i) receive an input x, (ii) compute (x+1) using only native precision, (iii) compute an integer N such that: 4/32N?1?(x+1)? 4/32N, (iv) compute ƒN(x)=Sx+(S?1) where S=2?N, (v) compute E(ƒN(x)), and (vi) return a value v=E(ƒN(x))+N ln(2) as an approximation of F(x)=log 1p(x).

Abstract: Rockets, rocket motors, methods of controlling a rocket and methods of evaluating a rocket design are disclosed. In some embodiments, a method of controlling a rocket may include measuring a combustion chamber pressure, calculating a logarithm of the measured combustion chamber pressure, and computing the difference between the logarithm of the measured combustion chamber pressure and the logarithm of a reference combustion chamber pressure value to generate an error signal. The method may further include filtering the error signal to generate a compensated signal in the logarithm domain, and exponentiating of the compensated signal in the logarithm domain to provide a compensated signal in the physical domain.

Abstract: Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

Abstract: Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number are provided. A first subset of bytes is read, and an associated first remainder by division is calculated and stored in the memory location from which the subset was read. A second subset of bytes is read, and an associated second remainder by division is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third and fourth subset of bytes is read and associated remainders are calculated.

Abstract: An arithmetic device includes a database that stores a first indicator representing a base unit included in a unit system being assigned with a prime number other than a prime factor of a prefix, and a second indicator derived by combining the base units, in a form of a simple fraction; a conversion section that obtains a plurality of physical quantities each including a quantity, a prefix, and possibly a unit, to derive a third indicator by converting the unit into the first indicator and multiplying the converted first indicator by the prefix, or when the unit belongs to the derived unit, by converting the unit into the second indicator and multiplying the converted second indicator by the prefix; and an arithmetic section that performs calculation between the quantities of the plurality of physical quantities and between the third indicators.

Abstract: A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for loge and ex calculations. Apparatus specifying, simulating, and/or layouts of the computer (components) are disclosed. Apparatus the computer and/or its components are disclosed.

Abstract: A quantum phase estimator may include at least one phase gate, at least one controlled unitary gate, and at least one measurement device. The quantum phase estimator receives at least one ancillary qubit and a calculational state comprised of multiple qubits. The phase gate may apply random phases to the ancillary qubit, which is used as a control to the controlled unitary gate. The controlled unitary gate applies a second random phase to the calculational state. The measurement device may measure a state of the ancillary qubit from which a phase of the calculational state may be determined.

Abstract: A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.

Abstract: A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Abstract: A computerized system for a digital method for the detection of fraud and/or anomalous transactions is disclosed based on a novel statistical interpretation of Benford's Law and a unique set of computer implementations outlining the development of digital distributions from the low-value region on the left of a given data set to the high-value region on the right. A division into sub-intervals of the entire data set along adjacent integral powers of ten suggested in the method provides the unique manner of visualizing and computer output actualization of the gradual evolution of digital distribution from near digital equality on the left to severe inequality on the right. The method provides a venue for detecting fraud committed by the sophisticated cheater well-aware of Benford's Law but inventing data without regards to development. Experimental results consistently demonstrate the effectiveness of the techniques used in embodiments of the invention.

Abstract: Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

Abstract: An arithmetic device includes a database that stores a first indicator representing a base unit included in a unit system being assigned with a prime number other than a prime factor of a prefix, and a second indicator derived by combining the base units, in a form of a simple fraction; a conversion section that obtains a plurality of physical quantities each including a quantity, a prefix, and possibly a unit, to derive a third indicator by converting the unit into the first indicator and multiplying the converted first indicator by the prefix, or when the unit belongs to the derived unit, by converting the unit into the second indicator and multiplying the converted second indicator by the prefix; and an arithmetic section that performs calculation between the quantities of the plurality of physical quantities and between the third indicators.

Abstract: An automated method of performing exponentiation is disclosed. A plurality of tables holding factors for obtaining results of Exponentiations are provided. The plurality of tables are loaded into computer memory. Each factor is the result of a second exponentiation of a constant and an exponent. The exponent is related to a memory address corresponding to the factor. A plurality of memory addresses are identified for performing the first exponentiation by breaking up the first exponentiation into equations, the results of which are factors of the first Exponentiation. The exponents of the equations are related to the memory addresses corresponding to the factors held in the tables. A plurality of lookups into the computer memory are performed to retrieve the factors held in the tables corresponding to the respective memory addresses. The retrieved factors are multiplied together to obtain the result of the first exponentiation.

Abstract: A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for loge and ex calculations. Apparatus specifying, simulating, and/or layouts of the computer (components) are disclosed. Apparatus the computer and/or its components are disclosed.

Abstract: A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by adding a plurality of first values related to a plurality of information bits, a plurality of second values related to the information bits and a plurality of third values related to a plurality of parity bits. Step (B) may generate a plurality of permutated values by permutating the sum values based on a configuration signal. The configuration signal generally identifies a current one of the communications standards. Step (C) may generate a plurality of branch metrics values by adding pairs of the permutated values.

Abstract: A method for quantifying and analyzing intrinsic parallelism of an algorithm is adapted to be implemented by a computer, and includes the steps of: configuring the computer to represent the algorithm by means of a plurality of operation sets; configuring the computer to obtain a Laplacian matrix according to the operation sets; configuring the computer to compute eigenvalues and eigenvectors of the Laplacian matrix; and configuring the computer to obtain a set of information related to intrinsic parallelism of the algorithm according to the eigenvalues and the eigenvectors of the Laplacian matrix.

Abstract: Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.

Abstract: Implementations of the present disclosure provide for determining an encoding type of data. Implementations include receiving a data set from a computer-readable storage medium, decoding the data set using a first encoding type to provide a first plurality of numbers, generating a first distribution based on the first plurality of numbers, decoding the data set using a second encoding type to provide a second plurality of numbers, and generating a second distribution based on the second plurality of numbers. An actual encoding type of the data set is determined based on the first distribution, the second distribution and an expected distribution, and the data set is processed based on the actual encoding type.

Abstract: A numeric value display method uses a display processing section. When an operation to read out a numeric value from storage means and display it is executed, if the numeric value has a greater number of digits than the number of digits which can be displayed on a numeric value display device, the display processing section divides the numeric value into a predetermined number of digits and displays a part of the numeric value on the numeric value display device in such a manner that it is possible to know which part of the numeric value is displayed. Moreover, each time operation keys are pressed, the display processing section resets a display diction variable (P) required for controlling the display position for each of the divided parts of digits preset and switches the part of the numeric value to be output to the numeric value display device.

Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table.

Abstract: A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

Abstract: A method of calculating a transport block size in an HSPA receiver of a communication system is provided. After decomposing an exponential function Pk into a plurality of constant vectors, the invention needs only little memory space and executes few continued multiplication operations to obtain a correct transport block size, thereby increasing efficiency and reducing calculation complexity.

Abstract: A method and ALU for implementing logarithmic arithmetic in a multi-stage pipeline is described herein. According to one embodiment, a master function is decomposed into two or more sub-functions. Memory associated with the pipeline stores a look-up table for each stage of the pipeline, where each table represents function values generated based on the corresponding sub-function, and where the look-up table associated with one stage differs from the look-up table(s) associated with at least one other stage. Each stage computes a stage output based on the stage input and the corresponding look-up table. By combining the stage outputs, the multi-stage pipeline outputs the logarithmic arithmetic output.

Abstract: The present invention describes a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a logarithmic format. In one exemplary embodiment, an ALU implements logarithmic arithmetic on complex numbers represented in a logpolar format. According to this embodiment, memory in the ALU stores a look-up table used to determine logarithms of complex numbers, while a processor in the ALU generates an output logarithm based on complex input operands represented in logpolar format using the stored look-up table. In another exemplary embodiment, the ALU performs logarithmic arithmetic on real and complex numbers represented in logarithmic format.

Abstract: Technologies are described herein for using efficient log-linear transformations to reduce the complexity of numerical computations. Efficient transforms can convert between linear fixed point values and log space values in about ten processor cycles per sample. A fractional exponent and an integer exponent may be combined together into a log domain variable representation. Log domain arithmetic operations may be performed on the combined variable as a whole. A fractional exponent representation of log domain numerical values can support automatic bit carries from the fractional exponent into the integer exponent. If an intermediate result of a calculation in the log domain causes the fractional portion of the exponent to exceed one, a bit carry can occur over to the integer component of the exponent. This carry can occur automatically due to the conjoined placement of the integer and fractional components of the exponent in the log domain combined variable.

Abstract: A method and a calculating circuit for generating an output signal representing an actual amplitude of a received digitized signal having a magnitude of the actual amplitude equal or greater than a value of a saturation level of a dynamic range of a receiver. For the determination of the actual amplitude, firstly, a predetermined time interval is selected. Then, a total number of samples of the received digitized signal within the predetermined time interval is calculated. Further, a number of samples of the received digitized signal within the predetermined time interval with the amplitude equal to the saturation level is calculated. Thereafter, a ratio between the number of the samples with the amplitude value equal to the saturation level and the total number of the samples is calculated. For calculation of the magnitude of the actual amplitude a predetermined relationship between the magnitude of the amplitude and the ratio is applied and the output signal representing the actual amplitude is provided.

Abstract: A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.

Abstract: A method of analysis of incomplete data sets to detect fraudulent data is disclosed. The method comprises computing constant values for various leading digit sequence lengths, computing artificial Benford frequencies for the digit sequence lengths, computing a standard deviation for each of the sequence lengths, and flagging any digit sequences in the data set that deviate more than an upper bound number of standard deviations from the artificial Benford frequencies, the upper bound used to determine if the observed data deviates enough to be considered anomalous and potentially indicative of fraud or abuse.

Abstract: A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the format. The logarithm unit determines a magnitude of an unbiased exponent of the floating point operand as an intermediate result based on the at least one signal, wherein the unbiased exponent is represented by unbiased exponent bits. Still further, the logarithm unit determines an exponent field and a fraction field high part of the intermediate result.

Abstract: A logarithmic transformer capable of a reduction in circuit scale. A logarithmic transformation upper bit string generating unit detects a highest order bit of logic “1” out of the bits bn−1, . . . , b0 of input data B as an active bit. Binary data for indicating the bit position S of the active bit is generated as a logarithmic transformation upper bit string DUP (dm−1, . . . ,dm−p). Here, based on the number of bits n of the input data B, the number of bits p of the logarithmic transformation upper bit string DUP (dm−1, . . . , dm−p) is set for the relationship n=2p. A logarithmic transformation lower bit string generating unit determines a bit string of order lower than the bit position S, having a predetermined number q of bits, out of the bits bn−1, . . . , b0 of the input data B. The resultant bit string makes a logarithmic transformation lower bit string DLOW (dm−p−1, . . . , d0).

Abstract: The invention includes a method and apparatus for generating a wide instruction controlling at least one data processing resource, local to that data processing resource, by accessing a local wide instruction memory based upon a narrow instruction, to generate at least part of the wide instruction. The local wide instruction memory can be accessed on every instruction cycle to reconfigure the controlled data processing resource(s). The data processing resources preferably includes arithmetic resources acting on the logarithms of various data inputs to generate a spectrum of non-additive results.

Abstract: A computation unit employs a logarithmic number system that uses a logarithmic numerical representation that differs from an IEEE standard representation to improve the efficiency of computation, both by reducing the time expended in performing the computation and by reducing the size of the integrated circuit that performs the computation. The illustrative computation unit employs a numerical representation that is similar to the IEEE format except that the sign term is omitted. Thus only positive numbers are represented. The value of the mantissa is defined as a fractional number between zero and one. The logarithmic number system is a useful number system domain for multiplication, division, reciprocal, square root, and power computations using multiplication, division, and square root computation techniques described by following equations: A*B=Anti-log(log(A)+log(B)),  (3) A/B=Anti-log(log(A)−log(B)),  (4) B½=Anti-log(log(B)/2).

Abstract: A digital signal system (50) for determining an approximate antilog x from a value of ƒ(x), wherein x has a base b. The system comprises circuitry (52) for storing the value of ƒ(x) as a digital representation, wherein the value of ƒ(x) has an integer portion and a decimal portion (i.f). The system also comprises circuitry (53) for setting a most significant digit bit position MSD of the approximate antilog x in response to the integer portion of ƒ(x), wherein adjacent the most significant digit bit position MSD is located a set of bits in respective lesser significant bit locations. The system also comprises a table (36) for storing a set of predetermined logarithms having the base b, wherein each of the predetermined logarithms corresponds to a number in a set of numbers.

Abstract: A device (1) for generating a digital output signal YLOG(k)/K) as a mathematical function of a digital input signal (XLOG(k)) includes a level-changing device (6), which by amplifying or attenuating the input signal (XLOG(k)) generates a first intermediate signal (A) that falls within a compressed argument range of the mathematical function and a correction signal (shiftLOG) dependent on the amplification or attenuation of the input signal (XLOG(k)). Tabulated function values of the mathematical function are stored at or between indices in a storage device (11). The tabulated function values (B1) are read from the storage device (11) in dependence on the first intermediate signal (A), and a second intermediate signal (B) is generated in dependence on the read tabulated function values (B1). The correction signal (shiftLOG) is subtracted from the second intermediate signal (B) in a subtractor (12) to yield the digital output signal YLOG(k)/K).

Abstract: A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central processing unit having a converter unit and a set of conversion registers. The load/store instructions having data requiring conversion include an index field for identifying one of the conversion registers. Each one of the conversion registers includes information on the type of conversion required and any scaling factors to be applied. Upon receiving one of these instructions, the converter uses the identified conversion register to perform the conversion and stores the converted data into the corresponding register or memory location.

Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability logarithm function with a small lookup table plus simple logic.