Abstract: A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand, wherein the integer operand is an integer power of two. Once detected, a multiplication operation meeting these criteria may be executed by using an integer adder to sum the integer power and the floating point operand's exponent to from a product exponent. The bias of the integer operand's exponent may also be subtracted. A product mantissa is simply copied from the floating point operand's mantissa. The floating point operand's sign bit may be inverted to form the product's sign bit if the integer operand is negative. Advantageously, the product is generated using integer addition which is faster than floating point multiplication. The method may be implemented in hardware or software.

Abstract: A method and system for an IIR filter are provided. A sequence of input signals is converted to a first sequence of log signals, while a sequence of feedback signals is converted to a second sequence of log signals. IIR filtering coefficients are then added to each sequence of log signals to generate a plurality of term signals. The term signals are then converted to inverse-log signals which are summed to produce an output signal. The log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial.

Abstract: A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

Abstract: A system (400) alternatively performs real matrix operation in a first mode or performs complex matrix multiplication in a second mode. One input matrix (e.g., {B}) stays in a plurality of memory fields (430-k), while the other input matrix (e.g., {A}) is loaded into a plurality of registers (410-k). Parallel operating groups (405-k, 409-(k+1)) combine elements of {A} with elements of {B}. The groups (405-k, 409-(k+1)) comprise the memory fields (430-k), the registers (410-k) as well as computational units (440-k), switches (420-k) and adder units (460-k). The adder units (460-k) are configured by the switches (420-k) to operate as adders or to operate as accumulators, depending on the mode. Adders provide intermediate results and accumulators accumulate these intermediate results (e.g., Sum) to elements of the resulting matrix {C}. For complex multiplication, real (Re) and imaginary (Im) parts of matrix elements are in processed in adjacent groups.

Abstract: With reference to FIG. 1 signal processor (10) for performing transformations of sets of input data points comprises a memory for storing a first half input data points and a second half input data points, an adder unit for pairwise adding one real part of each one first half input data point and a second half input data point and providing adder output data, and a computing unit for performing transformations upon the adder output data. Addition for data reduction and data transformation are carried out simultaneously by different units.

Abstract: A multiply-multiply-accumulate (MMA) system (10) efficiently evaluates matrix products X=F*C. Matrix C is dissected into submatrices A and B taking advantage of symmetry in C. LOG unit (14) converts B, A, and F to LOG values B', A' and F'. These are summed in K parallel calculating units CU's (18) and converted back to Normal domain as P=F*B*A in ALOG units (22) and sent to accumulators ACU's (24). The ACU's (24) accumulate the results. An output buffer (26) combines the results. The B', A' values (32,34) are held in a cache memory (20) and the LOG sums are performed in two steps with intermediate storage.

Abstract: An apparatus that includes a logarithm based processor (216) having at least one digital logarithm converter (202) and a power amplifier (208) responsive to the logarithm based processor (216).

Abstract: A method and system for a convolution operation in a digital signal processor (DSP) are provided. The convolution operation is performed in a logarithmic number system (LNS) domain. The DSP includes a plurality of processing elements that executes the convolution in a highly parallel fashion. The method can be implemented as a software program that directs a LNS based DSP to execute the convolution operation.

Abstract: A parallel processor (110) operates in the LOG domain. A LOG converter (114) receives input data in the NORMAL and converts it to the LOG domain for processing in the parallel processing units PPU-k. Scaling of the input data, is performed in the LOG converter (114) without need for additional multipliers. A constant factor is added to the LOG input data during the LOG conversion process using existing LOG adders already present to perform the LOG conversion. Thus, less total circuitry is needed and the processor can be made more compact, more efficient and less costly.

Abstract: An apparatus that includes a logarithm based processor (216) having at least one digital logarithm converter (202) and an audio amplifier (208) responsive to the logarithm based processor (216).

Abstract: The sum of a plurality of logarithmic numbers is determined by expressing the logarithmic numbers as one of a predetermined values. For example, the numbers may be analog values which may be sampled by an 8-bit AtoD converter to be expressed as one of a possible 256 values. The number of occurrences for each of the values is accumulated in bins (counters) and the sum is determined by a summation of the logarithmic numbers based on processing of the counts rather than the logarithmic numbers themselves. Bin counts are reduced iteratively by replacing counts greater than 1 by incrementing the count of a proportionately higher value bin until only counts of 1 or zero remain. These counts are then combined to provide only a single counter with a non-zero count value which indicates the accumulated signal strength of the signal strength measurements. The invention may further be provided using single bit memory elements and byte processing with look-up tables.