Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

Abstract: A system and method improve the performance of non-volatile memory storage by offloading parity computations to facilitate high speed data transfers, including direct memory access (DMA) transfers, between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., SSD). In conjunction with writing to non-volatile memory storage, a stripe map is used to target a selected data storage device for parity generation. All data of a stripe is transmitted to the selected data storage device to generate the parity and the generated parity is propagated from the selected data storage device to other data storage devices in the stripe. The data for the stripe may also be propagated from the selected data storage device to the other data storage devices in the stripe.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages includes shifted parities generated, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed by selecting one of the shifted parities for the first protection and the second protection.

Abstract: Disclosed are a fault-localization and error-correction method for a self-checking binary signed-digit adder and a digital logic circuit for performing the method. More specifically, a fault-localization and error-correction method for a self-checking binary signed-digit adder in which a stuck-at fault of the self-checking binary signed-digit adder may be detected at low cost and with low complexity and in which an error may be autonomously corrected using the self-dual concept, and a digital logic circuit for performing the method are disclosed.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: A method for calculating an error signal that enables a diagnosis of the correctness of a product, determined by a first multiplier unit, of a first factor and a second factor, the error signal being determined by a difference formation unit as the difference of a sum logarithm and a product logarithm.

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract: Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

Abstract: f(x(sk?1, sk))=A(sk?1)+B(sk) is calculated for nm2 pairs of consecutive state variables {sk?1, sk} using A(sk)=minsk?1,x{A(sk?1)+?(xk=x)} and B(sk)=minsk+1,x{B(sk+1)+?(xk+1=x, sk+1)}, where ?(xk=x) is a metric associated with a branch xk=x connecting consecutive state variables sk?1 and sk. The nm lowest values are selected from the nm2 calculated values of f(x(sk?1, sk))=A(sk?1)+B(sk) and log likelihood ratios (LLRs) are set to those lowest f(x(sk?1, sk)) values. The nm values of x that correspond to the nm lowest values are determined.

Abstract: A method includes receiving packed data corresponding to pixel components to be processed at a graphics pipeline. The method includes unpacking the packed data to generate floating point numbers that correspond to the pixel components. The method also includes routing each of the floating point numbers to a separate lane of the graphics pipeline. Each of the floating point numbers are to be processed by multiplier units of the graphics pipeline.

Abstract: A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value.

Abstract: In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

Abstract: An apparatus and method for searching for erroneous data is provided. The method of searching for erroneous data includes checking received data using an error-checking field included in the received data, and compensating for erroneous data of the checked data.

Abstract: An FFT processor for an OFDM receiver includes multiple interrelated operational blocks. The FFT processor is configured to perform data demodulation, channel estimation, and fine timing acquisition on received OFDM symbols. The FFT processor incorporates a pipelined FFT engine using a memory architecture shared with channel estimation and demodulation blocks. The combination of the shared memory structure and the pipelined FFT operation enable the channel estimation and demodulation processing to be completed during the time used to capture the next received symbol.

Abstract: A semiconductor device transmitting a plurality of data using a multilevel signal includes a parity bit control unit generating a parity bit that varies with a number of data in which a most significant bit (MSB) and least significant bit (LSB) are different. A data conversion unit either inversely outputs the MSB or the LSB, or outputs the data without a change in response to the parity bit. Transmission units transmit data provided by the data conversion unit using the multilevel signal.

Abstract: A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) data on the array, the file system determines which disks contain free blocks in a next allocated stripe of the array. There may be multiple blocks within the stripe that do not contain file system data (i.e., unallocated data blocks) and that could potentially store parity. One or more of those unallocated data blocks can be assigned to store parity, arbitrarily. According to the dynamic parity distribution technique, the file system determines which blocks hold parity each time there is a write request to the stripe. The technique alternately allows the RAID system to assign a block to contain parity when each stripe is written.

Abstract: A reconfigurable device having a plurality of component elements each configured in accordance with configuration information, the device being adapted to determine whether an error in configuration information for the component elements affects an output of the reconfigurable device.

Abstract: A new rate compatible coding approach is disclosed herein which takes advantage of the structure of irregular repeat accumulate (IRA) type codes, a special class of low density parity check codes.

Abstract: A method of constructing a puncture sequence includes providing a seed puncture sequence including a plurality of elements. The elements of the seed puncture sequence are based upon non-zero elements of a plurality of columns of a parity-check matrix having a column dimension and a row dimension. In this regard, the parity-check matrix defines an error correction code, and has been constructed based upon a seed parity-check matrix derived from an edge ensemble. After providing the seed puncture sequence, a variable node-puncture sequence can be constructed based thereupon. The variable node-puncture sequence, then, corresponds to a puncture sequence configured for processing an error correction code.

Abstract: Decoding by passing messages back and forth between a set of variable nodes and a set of check nodes, where at least one of the nodes broadcasts the same message to each of its associated nodes, is provided. For example, the variable nodes can broadcast and the check nodes can provide individual messages. Alternatively, the check nodes can broadcast and the variable nodes can provide individual messages. As another alternative, the variable nodes and the check nodes can both broadcast to their associated nodes. Broadcasting reduces the number of interconnections required between variable nodes and check nodes. Broadcasting is enabled by providing local storage within the nodes and/or by providing extra processing steps within the nodes.

Abstract: A decoder for decoding low-density parity-check codes includes a first calculator that calculates ??rRml, for each parity check equation, at iteration i?1. A second calculator calculates ??rQ?m, for each parity check equation, at iteration i. ??rQ?m represents information from bit node I to equation node m, one for each connection. ??rRml represents information from equation node m to bit node I, one for each connection. The first calculator is responsive to the second calculator.

Abstract: A computer system including: at least one host computer, a storage system for storing data used in the host computer, and a managing computer for managing storing the data in the storage system which are connected to each other with a network. The managing computer monitors the journal volume which is a storing destinations of the journal, in a case that the journal is stored in the journal volume in parallel, when it is detected that the storing destination of the journal changes from one of the groups into which the journal is just stored to another group, transmits an instruction to the storage system to change the storing destination of the journal to another group.

Abstract: A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.

Abstract: A method and apparatus for enhancing performance of parity check in computer readable media is provided. For example, in a RAID (N+1) configuration, a virtual data strip is added for a calculation of parity. Data of the virtual data strip is set so that a predetermined portion of a data area in the virtual data strip has a predetermined value. Consequently, performance of parity check performed in a data processing system having a RAID configuration can be enhanced.

Abstract: A fault-tolerant system for storage arrays has constraints on the number of data from which each redundancy value is computed. The fault-tolerant system has embodiments that are supported on small array sizes to arbitrarily large array sizes, and can tolerate a large number T of failures. Certain embodiments can tolerate many instances of more than T failures. The fault-tolerant system has efficient XOR-based encoding, recovery, and updating algorithms and has simple redundancy formulas. The fault-tolerant system has improved IO seek costs for certain multiple-element sequential host updates.

Abstract: A decoder for decoding low-density parity-check codes comprises a first calculator to calculate LLrRml, for each parity check equation, at iteration i?1. A detector detects LLrRml, at iteration i, in response to the first calculator. A second calculator calculates LLrQLm, for each parity check equation, at iteration i in response to the detector. LLrQLm represents information from bit node l to equation node m, one for each connection. LLrRml represents information from equation node m to bit node l, one for each connection. The first calculator is responsive to the second calculator.

Abstract: A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circuit. In succeeding iterations, the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block decoder from an immediately preceding iteration. The storage system includes a threshold check circuit to select (i) an output of the soft linear block code decoder if the number of parity-check violations has a first relationship with respect to a threshold, or (ii) an output of the channel decoder if the number of violations has a second relationship with respect to the threshold. The storage system includes a decoder to decode an output of the threshold check circuit.

Abstract: A system, method, and apparatus are disclosed for storing segmented data and corresponding parity data with modules configured to functionally execute the necessary steps of storing segmented data and corresponding parity data. These modules, in the described embodiments, include a designation module that designates a first set of data, from parity data and a plurality of segmented data, as surplus data and designates the remaining data as primary data. A storage module stores the primary data in main electronic storage devices in a distributed manner and stores a first copy of the surplus data on a first main electronic storage device and a second copy of the surplus data on a second main electronic storage device. An optional auxiliary storage module selectively activates an auxiliary electronic storage device and stores the surplus data on the auxiliary storage device. Beneficially, selective activation of the auxiliary electronic storage conserves power.

Abstract: Disclosed is a parity checking scheme for data forwarding of results from a first function unit to a second function unit. In one embodiment, the results of the first function unit are forwarded along a result forwarding bus to a destination parity generator at the second function unit. The destination parity generator generates destination parity bits for the forwarded results and sends the destination parity bits to a parity checking circuit at the second function unit. In addition, the results of the first function unit are sent to a source parity generator at the first function unit. The source parity generator generates source parity bits for the forwarded results and sends the source parity bits to the parity checking circuit at the second function unit via a parity forwarding bus. The parity checking circuit compares the source parity bits and the destination parity bits, and generates a parity error signal indicating whether result forwarding is with any error.

Abstract: The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.

Abstract: A method and apparatus for characterizing frequency response of a device under test (DUT) is disclosed. A repeated base bit pattern is received, the base bit pattern including a first transition from a 0-bit to a 1-bit. Then, using bit error rate distribution, multivalue voltage along the first transition is determined. Finally, the multivalued voltages are converted into frequency domain using fast Fourier transform. The apparatus includes a processor and storage with instructions for the processor to perform these operations. Using the present inventive technique, the frequency response of the DUT can be determined using an error performance analyzer such as a BERT.

Abstract: The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.

Abstract: A method and apparatus for generating a flag simultaneously with production of an operation result by an operational unit. The flag is generated based on data input to the operational unit, and the flag indicates the presence or absence of a condition in the operation result produced by the operational unit.