Error Detection Or Correction Patents (Class 708/530)
  • Patent number: 11468797
    Abstract: Disclosed herein is an apparatus for calculating a cryptographic component R2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises an arithmetic logic unit configured to iteratively perform Montgomery multiplication of a first operand with a second operand to produce an intermediate result, wherein the first operand and the second operand are set to the intermediate result after each iteration, responsive to a termination condition being met, determine an adjustment parameter indicative of a difference between the intermediate result and the cryptographic component, and perform Montgomery multiplication of the intermediate result with the adjustment parameter, to calculate the cryptographic component for the cryptographic function.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: October 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ishai Ilani, Noam Weber
  • Patent number: 11463112
    Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: October 4, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
  • Patent number: 10650151
    Abstract: In this method, a securing hardware module of a microprocessor: 1) verifies (176) the integrity and the authenticity of a cryptogram contained in a code line loaded with the aid of a message authentication code contained in this same line and triggers (172) the signalling of an execution fault if the integrity or the authenticity of the cryptogram is not confirmed, and then 2) decrypts (178) the cryptogram to obtain a decrypted instruction or a decrypted datum if the integrity and the authenticity of the cryptogram are confirmed, and then: in the case of a decrypted instruction, the decrypted instruction is recorded (180) in a queue of instructions to be executed successively one after another by an arithmetic and logic unit of the microprocessor, and in the case of a decrypted datum, the decrypted datum is recorded in an internal register of the microprocessor while waiting to be processed by the arithmetic and logic unit.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: May 12, 2020
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Olivier Savry
  • Patent number: 10469270
    Abstract: A data processing device includes a Physical Unclonable Function value source which is set up to provide a reference Physical Unclonable Function value and a plurality of subsequent Physical Unclonable Function values, the reference Physical Unclonable Function value and each subsequent Physical Unclonable Function value having a multiplicity of binary components, a determination device which is set up to determine a set of components, the value of which is identical in the plurality of subsequent Physical Unclonable Function values, and a Physical Unclonable Function reconstruction device which is set up to reconstruct the reference Physical Unclonable Function value from the subsequent Physical Unclonable Function values assuming that the values of the determined components in the subsequent Physical Unclonable Function value match the values of the determined components in the reference Physical Unclonable Function value.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies AG
    Inventor: Rainer Goettfert
  • Patent number: 10366042
    Abstract: A mobile computing device is provided. The device includes a first port having a pinout configuration that is configured to support at least one data format, a data source configured to provide data of a second data format that is different from the at least one data format, and a first multiplexer configured to selectively direct data from the data source towards the first port. The pinout configuration is modified to enable the first port to support the second data format.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: July 30, 2019
    Assignee: The Boeing Company
    Inventor: Bradley Shawn Wynn
  • Patent number: 10216942
    Abstract: When data is stored for a significant amount of time or is transmitted through a noisy environment, it is not uncommon for pieces of that data to be lost or degraded. The disclosed method provides users with a new way of generating and then storing data to provide for easy recovery of said data when pieces of data are lost during storage or during transmission. Unlike the present art, which requires users to store or transmit redundant data, this method does not require redundancy. By removing that redundancy, space-costs of storing data can be reduced.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 26, 2019
    Assignee: University of Louisiana at Lafayette
    Inventor: Louis M. Houston
  • Patent number: 9842086
    Abstract: A first calculation unit is capable of calculating f(x)bx1 and sets a calculation result of f(x)bx1 to u, and a second calculation unit is capable of calculating f(x)ax2, and sets a calculation result of f(x)ax2 to v. A final calculation unit outputs (ub?va?)1/d for d=a?a+b?b when the calculation result u and the calculation result v satisfy ua=vb. Here, G and H are groups, f is a function for mapping an element x of the group H to the group G, X1 and X2 are random variables values of which are in the group G, a realization of the random variable X1 is x1, a realization of the random variable X2 is x2, and a, b, a?, and b? are integers.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 12, 2017
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Tetsutaro Kobayashi, Go Yamamoto
  • Patent number: 9813061
    Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: November 7, 2017
    Assignee: Altera Corporation
    Inventors: Herman Henry Schmit, David Lewis
  • Patent number: 9698825
    Abstract: A device includes a processor and a checksum module, wherein the checksum module calculates, for first data, an updated checksum that complies with Internet Engineering Task Force Request For Comments Number 1624 using twos-complement arithmetic. The processor replaces the original checksum with the updated checksum to update a data packet.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: July 4, 2017
    Assignee: QUEST SOFTWARE INC.
    Inventor: George Weigt
  • Patent number: 9678924
    Abstract: A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 13, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Rainer Goettfert, Berndt Gammel, Thomas Kuenemund
  • Patent number: 9678751
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Moustapha Hagog, Robert Valentine, Amit Gradstein, Simon Rubanovich, Zeev Sperber, Boris Ginzburg, Ziv Aviv
  • Patent number: 9665376
    Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
  • Patent number: 9619167
    Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Knut S. Grimsrud, Richard L. Coulson
  • Patent number: 9507602
    Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
  • Patent number: 9424139
    Abstract: A method, article of manufacture, and apparatus for recovering data. In some embodiments, this includes creating a version of the data set, determining a metadata window based on the created version, storing metadata based on the determined metadata window in a first storage device, and storing the version in a second storage device. In some embodiments, a metadata tag may be associated with the metadata, and in some embodiments, a version tag may be associated with the version.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 23, 2016
    Assignee: EMC Corporation
    Inventors: Michael John Dutch, Christopher Hercules Claudatos, Mandavilli Navneeth Rao
  • Patent number: 8977668
    Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventor: Wieland Fischer
  • Patent number: 8963579
    Abstract: Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, George I. Bourianoff, Tahir Ghani
  • Patent number: 8907973
    Abstract: An image processor includes generates a content adaptive kernel from an image block with noise of a luminance component signal with a low resolution. The content adaptive kernel is convolved with the luminance component signal. A noise signal and an extracted texture which excludes noise are generated. The luminance component signal is filtered as function of the noise signal to generate an enhanced luminance component signal. Horizontal and vertical scaling is performed on the enhanced luminance component signal, the extracted texture, and the luminance component signal, with the luminance component signal adaptively scaled as a function of the extracted texture. The horizontally and vertically scaled enhanced luminance component signal, extracted texture and luminance component signal are then combined to generate an output luminance component signal with a high resolution.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Chandranath Manchi
  • Patent number: 8706377
    Abstract: A controller system in which a plurality different main functions are integrated includes a plurality of microcontrollers. Each of the microcontrollers is associated with one of the main functions. At least one monitoring unit is implemented for the plurality of the main functions, for example a brake monitor and a comfort monitor. When the at least one monitoring unit detects a defect of a main function in the controller, only the defective main function is deactivated.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: April 22, 2014
    Assignee: Autoliv Development AB
    Inventors: Lothar Weichenberger, Franz Obesser
  • Publication number: 20140059105
    Abstract: A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: The Regents of the University of California
    Inventors: Andrew B. Kahng, Seokhyeong Kang
  • Patent number: 8626816
    Abstract: A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Weinberg, Martin S. Schmookler
  • Patent number: 8612508
    Abstract: A device may include a compressor. The compressor may receive a first number of inputs, each of the inputs having a predetermined width. The compressor may also compute a one's complement sum of the first number of inputs to generate carry bits having the predetermined width and sum bits having the predetermined width, modify the carry bits by moving a most significant bit of the carry bits to a least significant bit position, and output the modified carry bits and the sum bits.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 17, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Anurag Agrawal, Philip A. Thomas
  • Patent number: 8489664
    Abstract: A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: July 16, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Wei Fu, Arash Farhoodfar
  • Patent number: 8452492
    Abstract: A driver assistance device for a vehicle having a plurality of safety functions, such as in particular an LDW function and an LKS function, in which system-related boundary values are provided for the safety functions such that when they are undershot the safety function is activated and when they are exceeded the safety function is deactivated. The boundary values are developed to be variable.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: May 28, 2013
    Assignee: Obert Bosch GmbH
    Inventors: Lutz Buerkle, Tobias Rentschler, Thomas App
  • Patent number: 8412762
    Abstract: An error-correcting method used in decoding data transmission is disclosed. The error-correcting method is used for analyzing an error receiving data received from a receiving terminal and comprises: providing a first calculating formula for manipulation of the receiving data to generate the first sum; providing a second calculating formula for manipulation of the receiving data to generate the second sum; identifying the error position of the receiving data according to the result of dividing the second sum by the first sum.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: April 2, 2013
    Assignee: Princeton Technology Corporation
    Inventor: Chiung-Ying Peng
  • Patent number: 8352530
    Abstract: A residue generator for calculation and correction of a residue value. The residue generator includes a residue-generation tree connected with an operand register at an input of the residue generator including a plurality of register-bits receiving and carrying bits of numerical data.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Juergen G. Haess, Michael Klein, Michael K. Kroener
  • Patent number: 8335808
    Abstract: The invention is a method of calculating a key equation polynomial. The key equation comprises an errata locator polynomial and an errata evaluator polynomial. The errata locator polynomial decomposes to a plurality of coefficients. Some or all of the plurality of coefficients are formed by adding up decomposed data. The method comprises a coefficient calculation procedure for the errata locator polynomial of updating at least two coefficients, or two decomposed data of the coefficient calculation procedure, or a combination of the above in a single clock cycle simultaneously to get the errata locator polynomial.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: December 18, 2012
    Assignee: Mediatek Inc.
    Inventor: Jia-Horng Shieh
  • Patent number: 8312361
    Abstract: In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: November 13, 2012
    Assignee: Fujitsu Limited
    Inventor: Shiro Kamoshida
  • Publication number: 20120278374
    Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F. Cowlishaw, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh
  • Patent number: 8301180
    Abstract: A portable electronic device is provided. The portable device comprises a wireless transceiver to receive and transmit messages and a messaging client. The messaging client receives a first message from the wireless transceiver, wherein the first message is from a first peer messaging client, parses the first message to read a first message sequence count, compares the first message sequence count to a first expected message sequence count, and based on a miscompare of the first message sequence count with the first expected message sequence count transmits a corrective message to the wireless transceiver for transmitting to the first peer messaging client.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 30, 2012
    Assignee: Sprint Communications Company L.P.
    Inventors: Michael A. Gailloux, Kenneth W. Samson
  • Publication number: 20120239720
    Abstract: For efficient computation of results for mathematical functions, a method receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function of the function call varies with respect to the values for the arguments. The method determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The method further aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results.
    Type: Application
    Filed: May 23, 2012
    Publication date: September 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John Robert Ehrman
  • Patent number: 8260091
    Abstract: An apparatus and method for searching for erroneous data is provided. The method of searching for erroneous data includes checking received data using an error-checking field included in the received data, and compensating for erroneous data of the checked data.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-yeul Kwon, Seong-soo Kim
  • Publication number: 20120197956
    Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.
    Type: Application
    Filed: April 10, 2012
    Publication date: August 2, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Wieland FISCHER
  • Patent number: 8229014
    Abstract: An FFT processor for an OFDM receiver includes multiple interrelated operational blocks. The FFT processor is configured to perform data demodulation, channel estimation, and fine timing acquisition on received OFDM symbols. The FFT processor incorporates a pipelined FFT engine using a memory architecture shared with channel estimation and demodulation blocks. The combination of the shared memory structure and the pipelined FFT operation enable the channel estimation and demodulation processing to be completed during the time used to capture the next received symbol.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: July 24, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Kevin Stuart Cousineau
  • Patent number: 8219605
    Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael F. Cowlishaw, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh
  • Patent number: 8205097
    Abstract: A Microprocessor (1) in a security-sensitive computing system for processing an operand according to an instruction is for improving its security provided with a modulo-based check hardware (2) to perform operations in parallel to the microprocessor (1) and for comparing both results regarding congruence.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: June 19, 2012
    Assignee: NXP B.V.
    Inventors: Ralf Malzahn, Li Tao
  • Publication number: 20120150932
    Abstract: A divider circuit includes: a register which is configured of an even number of bits and in which a dividend data is stored. A shift operation section is configured to acquire a data stored in an upper bit portion of the register when the even number of bits of the register is equally divided to the upper bit portion and a lower bit portion, as a quotient data when the dividend data is divided by a maximum of a divisor data which can be expressed by a half of the even number of bits of the register.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 14, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Mihoko Tanaka
  • Patent number: 8185570
    Abstract: The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Fukumura, Patrick Hamilton, Masaya Nakahata, Takashi Oomori
  • Patent number: 8185572
    Abstract: A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data word bid and an adjacent data word bit to provide a first output bit and a second logic circuit connected to receive the first output bit and a different adjacent bit of the data word to provide a second output bit representing a corrected value of the unique bit.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventor: Deepak K. Singh
  • Patent number: 8144812
    Abstract: A communications node can receive a plurality of communication signals, each including a block of data estimates with respective quality metrics. Each block of data estimates can be derived from an original block of data sent over different wireless paths, or from a derived block of data estimates sent over a different wireless path. A data combining circuit can be used to combines the blocks of data estimates as a function of the respective quality metrics to produce an output set of data estimates with a derived quality metric.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: March 27, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Dilip Krishnaswamy
  • Patent number: 8140606
    Abstract: A base station transmitter for maintaining data rate transmission between a set of Fourier Transform matrices, having a digital Fourier Transform Matrix (FTM), and analog FTM, and a plurality of transmit paths therebetween. During the occurrence of a power amplifier failure, the method includes detecting the failure of a power amplifier (PA); and reconfiguring the digital FTM and analog FTM to a pass-thru mode.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: March 20, 2012
    Assignee: Motorola Mobility, Inc.
    Inventors: Ronald L. Porco, Leroy A. Plymale, Jr.
  • Patent number: 8037533
    Abstract: A detecting method for network intrusion includes: selecting a plurality of features contained within plural statistical data by a data-transforming module; normalizing a plurality of feature values of the selected features into the same scale to obtain a plurality of normalized feature data; creating at least one feature model by a data clustering technique incorporated with density-based and grid-based algorithms through a model-creating module; evaluating the at least one feature model through a model-identifying module to select a detecting model; and detecting whether a new packet datum belongs to an intrusion instance or not by a detecting module.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: October 11, 2011
    Assignee: National Pingtung University of Science and Technology
    Inventors: Cheng-Fa Tsai, Chia-Chen Yen
  • Patent number: 7978972
    Abstract: The optical line terminal has a PON transceiver including an error correction code decoder. The error correction decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table. Also the optical network terminal has a PON transceiver including an error correction code decoder. The error code decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: July 12, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masaki Ohira, Taro Tonoduka
  • Patent number: 7941473
    Abstract: In a graphing calculator, a decimal calculation unit obtains a calculation result of an arithmetic expression input by an input device to an n-th digit and an (n+m)-th digit. When the values from the most significant digit to an (n+1)-th digit in the (n+m)-digit calculation result are zero, with respect to an addition or subtraction, the CPU corrects an n-digit calculation result of the addition or subtraction to zero.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 10, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hisashi Ito
  • Publication number: 20110010408
    Abstract: Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.
    Type: Application
    Filed: March 5, 2009
    Publication date: January 13, 2011
    Inventor: Katsutoshi Seki
  • Patent number: 7865793
    Abstract: A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the test case by determining missing input operands and storing these input operands in both the temporary register file and the initial register file, and calculating missing results and storing all results in the temporary register file.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Stefan Letz, Juergen Vielfort, Kai Weber
  • Patent number: 7859547
    Abstract: A method and an apparatus for adjusting a display parameter are provided. The method includes the steps of: (a) calculating a scene change value between a current frame and a previous frame; (b) setting a first weight according to the scene change value; (c) calculating an original parameter of the current frame; (d) providing a display parameter of the previous frame; (e) calculating a display parameter of the current frame according to the first weight, the original parameter, and the display parameter of the previous frame.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: December 28, 2010
    Assignee: Himax Technologies Limited
    Inventors: Shing-Chia Chen, Ling-Hsiu Huang
  • Patent number: 7769795
    Abstract: An end-to-end residue-based protection scheme protects multiple units/blocks of a floating point execution pipeline without the complexity and cost of having multiple protection schemes for the execution pipeline. Protecting an execution pipeline that supports floating point operations includes factoring in component operations, such as normalization and rounding, into a residue generated for a result. In addition, residues of operands are distilled to extract their corresponding mantissa residues, thus allowing the floating point operations (e.g., multiplication, addition, etc.) to be applied to the mantissa residues.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: August 3, 2010
    Assignee: Oracle America, Inc.
    Inventor: Sorin Iacobovici
  • Patent number: 7751505
    Abstract: A decoder for decoding low-density parity-check codes includes a first calculator that calculates ??rRml, for each parity check equation, at iteration i?1. A second calculator calculates ??rQ?m, for each parity check equation, at iteration i. ??rQ?m represents information from bit node I to equation node m, one for each connection. ??rRml represents information from equation node m to bit node I, one for each connection. The first calculator is responsive to the second calculator.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: July 6, 2010
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Gregory Burd
  • Patent number: 7730356
    Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, John Vranich, Pierre Laurent, Daniel Cutter, Wajdi K. Feghali, Andrew Milne, Erdinc Ozturk