Abstract: Checking correctness of computations. An arithmetic logic unit circuit provides a computation result as a first number. The computation result is increased by a constant as a second number by the arithmetic logic unit circuit. A sum of the first number and the constant is compared to the second number, and an error is reported, if the comparing operation does not indicate an equal result.

Abstract: A field device includes a first program area storing a first program, a second program area storing a second program designed such that if a program execution portion executes each of the first and second programs using the same data, a result of a calculation performed according to the second program is the same as a result of a calculation performed according to the first program, a first calculation result storage buffer storing a result of the calculation performed by the program execution portion according to the first program, and a second calculation result storage buffer storing a result of the calculation performed by the program execution portion according to the second program, and a calculation result comparator comparing the calculation result stored in the first calculation result storage buffer with the calculation result stored in the second calculation result storage buffer.

Abstract: A portable electronic device is provided. The portable device comprises a wireless transceiver to receive and transmit messages and a messaging client. The messaging client receives a first message from the wireless transceiver, wherein the first message is from a first peer messaging client, parses the first message to read a first message sequence count, compares the first message sequence count to a first expected message sequence count, and based on a miscompare of the first message sequence count with the first expected message sequence count transmits a corrective message to the wireless transceiver for transmitting to the first peer messaging client.

Abstract: A method and device may be useful for dynamically verifying a processor architecture at runtime. The checker may more efficiently and cheaply verify at least some of the functionality provided by the execution unit of the processor architecture. The checker may verify operations such as addition, subtraction, multiplication, and division.

Abstract: Methods and apparatus, including computer program products, for modelling a non-linear transfer function with a power law function. A transfer function is received. Iteratively, until a termination flag is set, a first power law function is received, an auxiliary function is generated from the transfer function and local differences between the transfer function and the first power law function, a second power law function is fitted to the auxiliary function, a modelling error is calculated from the second power law function and the transfer function, and the termination flag is set when the modelling error is less than a predetermined value.

Abstract: Disclosed is a diagnostic method for a logic used in a vehicle in which a sequence of a plurality of logic operations is predetermined, the method comprising the steps of assigning an ID to each logic operation; comparing an ID of a logic operation that should be performed (“correct logic operation”) with an ID of a logic operation to be performed (“present logic operation”) before the present logic operation is performed; and determining that an error has not occurred in the case where the correct logic operation corresponds to the present logic operation, and determining that an error has occurred in the case where the correct logic operation does not coincide with the present logic operation.