Abstract: A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements. The method comprises: a) executing (in 48) n arithmetic or logical operations of a first iteration of the first tree in parallel using the n processing elements, then b) executing (in 66) m arithmetic or logical operations in parallel between the results of the first iteration, using m processing elements chosen from the n processing element used for the computation of the first iteration, the other n?m processing element being unused for the computation of the second iteration. In parallel with the computation of the second iteration of the first tree, the method comprises executing (in 66) k arithmetic or logical operations of the second tree in parallel using k processing elements chosen from the n?m processing elements unused for the computation of the second iteration of the first tree.

Abstract: Methods, apparatus, and computer program products are disclosed for executing a gather operation on a parallel computer according to embodiments of the present invention. Embodiments include configuring, by the logical root, a result buffer or the logical root, the result buffer having positions, each position corresponding to a ranked node in the operational group and for storing contribution data gathered from that ranked node.

Abstract: The optical line terminal has a PON transceiver including an error correction code decoder. The error correction decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table. Also the optical network terminal has a PON transceiver including an error correction code decoder. The error code decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table.

Abstract: To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.

Abstract: A reconfigurable device having a plurality of component elements each configured in accordance with configuration information, the device being adapted to determine whether an error in configuration information for the component elements affects an output of the reconfigurable device.

Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.

Abstract: Methods and systems for performing arithmetic functions. In accordance with a first aspect of the invention, methods and apparatus are provided, working in conjunction of software algorithms and hardware implementation of class network routing, to achieve a very significant reduction in the time required for global arithmetic operation on the torus. Therefore, it leads to greater scalability of applications running on large parallel machines. The invention involves three steps in improving the efficiency and accuracy of global operations: (1) Ensuring, when necessary, that all the nodes do the global operation on the data in the same order and so obtain a unique answer, independent of roundoff error; (2) Using the topology of the torus to minimize the number of hops and the bidirectional capabilities of the network to reduce the number of time steps in the data transfer operation to an absolute minimum; and (3) Using class function routing to reduce latency in the data transfer.

Abstract: The present invention relates to a method of utilizing information made available in a bit error check of data words belonging to instructions read into a processor having a first (11) and a second (11′) calculating unit which operate in parallel with one another, a so-called double processor mode. The processor structure also comprises a third and a fourth calculating unit (13, 13′) intended for continuously checking for possible bit errors in read-in data words, a comparator (14) for comparing output data from parallel operating units (11, 11′), a diagnostic unit (15) adapted to determine which of the calculating units delivered correct output data when detecting a difference in output data in the comparator (14), and a control unit (16) adapted to control that the output data from the processor structure (1) originates from a calculating unit that has delivered correct output data.

Abstract: The present invention is a method and apparatus for reporting exception in a single instruction multiple data (SIMD) processor in computing an arithmetic function for a plurality of argument data. The SIMD processor is configured for processing N elements simultaneously. A sequence of instructions is re-arranged to allocate the plurality of argument data in the N elements. The N elements are processed simultaneously. The exceptions for N elements are detected simultaneously. The detected exceptions are then combined to generate a global exception.