Overflow Or Underflow Patents (Class 708/552)

Patent number: 11409537Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floatingpoint operation, including a multidimensional floatingpoint operation, and the second instruction to cause the GPU to perform an integer operation; and a generalpurpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the generalpurpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.Type: GrantFiled: November 21, 2017Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Elmoustapha OuldAhmedVall, Barath Lakshmanan, Tatiana Shpeisman, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Anbang Yao, Ben J. Ashbaugh, Linda L. Hurd, Liwei Ma

Patent number: 11301214Abstract: A circuit for performing multiply/accumulate operations evaluates a type of each value of a pair of input values. Signed values are split into sign and magnitude. One or more pairs of arguments are input to a multiplier such that the arguments have fewer bits than the magnitude of signed values or unsigned values. This may include splitting input values into multiple arguments and inputting multiple pairs of arguments to the multiplier for a single pair of input values.Type: GrantFiled: June 9, 2020Date of Patent: April 12, 2022Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Mankit Lo, Meng Yue, Jin Zhang

Patent number: 11262981Abstract: An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.Type: GrantFiled: November 5, 2018Date of Patent: March 1, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hajime Kimura, Takahiro Fukutome

Patent number: 9781682Abstract: The disclosure discloses a method for poweron control of a mobile terminal and a mobile terminal. The method includes: when a poweron detection flag bit in a mobile terminal is at a high level, judging whether there is an external power supply access event; if it is judged that there is an external power supply access event, and it is detected that the mobile terminal is in a poweroff status currently, then triggering an external power supply poweron event, and setting the poweron detection flag bit to a high level; if it is judged that there is no external power supply access event, then judging whether there is a keypressing event; and if it is judged that there is a keypressing event, and it is determined that the keypressing event is used for controlling to turn on the mobile terminal, then triggering a keypressing poweron event, and setting the poweron detection flag bit to a high level.Type: GrantFiled: November 11, 2011Date of Patent: October 3, 2017Assignee: XI'AN ZTE NEW SOFTWARE COMPANY LIMITEDInventors: Jiajun Liu, Jihong Wang

Patent number: 9524143Abstract: A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, poweroftwo detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2N, where N is a positive integer, and bypass circuitry configured, in response to signalling of the bypass condition, to cause the division circuitry to be bypassed and to cause the result value to be generated as the input numerator shifted by N bits.Type: GrantFiled: June 26, 2014Date of Patent: December 20, 2016Assignee: ARM LimitedInventors: Neil Burgess, David Raymond Lutz

Patent number: 8805914Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimize underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixedpoint units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.Type: GrantFiled: June 2, 2010Date of Patent: August 12, 2014Assignee: Maxeler Technologies Ltd.Inventors: Oliver Pell, James Huggett

Patent number: 8495117Abstract: A system and method for parallelization of saturated accumulation is provided. In the method, an input sequence is divided into a plurality of subsequences. For each subsequence, three parallel saturating additions are performed. The local saturation minimum is the saturating addition of the global saturation minimum and the values of the subsequence. The local midpoint is the saturating addition of the values of the subsequence and the local saturation maximum is the saturating addition of the global saturation maximum and the values of the subsequence. In embodiments, the accumulation total for a subsequence is calculated as the saturating addition of the accumulation total for prior subsequences and the local midpoint of the current subsequence, wherein the accumulation total of the last subsequence is the result of the saturated accumulation for the sequence. In another embodiment, the saturated addition of subsequence results are further parallelized before the final result is reached.Type: GrantFiled: March 17, 2009Date of Patent: July 23, 2013Assignee: Broadcom CorporationInventors: Alexander J. Burr, Timothy M. Dobson

Patent number: 8316067Abstract: A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a calculationinstruction memory section which stores the calculation instruction having the number of calculation digits and a type of calculation set therein, and a decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in the plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in the calculation instruction stored in calculationinstruction memory section, in decimal calculation according to type of calculation set in the calculation instruction stored in calculationinstruction memory section, and sequentially wrType: GrantFiled: April 22, 2009Date of Patent: November 20, 2012Assignee: Casio Computer Co., Ltd.Inventors: Hisashi Ito, Tetsuichi Nakae

Patent number: 8266198Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform roundtonearest and roundtonearesteven operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a lookahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.Type: GrantFiled: June 5, 2006Date of Patent: September 11, 2012Assignee: Altera CorporationInventors: Kwan Yee Martin Lee, Martin Langhammer, YiWen Lin, Triet M. Nguyen

Patent number: 8209366Abstract: A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit is combined with an arithmetic shifter and a final decision multiplexor. The final decision multiplexor receives the output from the arithmetic shifter and the saturated value from the saturation circuit. When saturation is detected by the saturation detection circuit, the final decision multiplexor selects the saturate minimum or the saturate maximum depending on whether the MSB of the data in equals one or zero, respectively.Type: GrantFiled: February 28, 2005Date of Patent: June 26, 2012Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Jeffrey J. Dobbek, Kirk Hwang

Patent number: 8094768Abstract: The present invention discloses a novel multichannel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardwarebased linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardwarebased secondorder timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop.Type: GrantFiled: December 21, 2006Date of Patent: January 10, 2012Assignee: Triductor Technology (Suzhou) Inc.Inventor: Yaolong Tan

Patent number: 7962729Abstract: Software defects (e.g., array access out of bounds, stack overflow, infinite loops, and data corruption) occur due to integer values falling outside their expected range. Because programming languages do not include rangechecking instructions as part of their language, to detect software defects and ensure that the code runs smoothly, programmers generally use 1) runtime assertions and/or 2) subrange data types. However, these techniques cause additional conditional branches, incur additional overhead, and decrease processor performance. Processors comprising a range checking hardware feature supported by machine instructions for runtime integer range checking can eliminate the conditional branches generated during runtime integer range checks. Programming language extensions for the range checking hardware can allow dynamic range bounds to be defined during runtime without decreasing the processor's performance. This can allow for easier programming and code that is easier to maintain.Type: GrantFiled: January 5, 2009Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventor: Jose G. Rivera

Patent number: 7958177Abstract: The present invention is to provide a parallel filtering method, which is implemented to an interpolation filter and comprises the steps of separating coefficients of the interpolation filter into two sets comprising the positive and negative coefficients respectively for parallelly filtering a plurality of input data pixels packed into data words inputted to the interpolation filter concurrently to obtain a first result data word, and clipping and shifting the first result data word to obtain a final output data word containing packed halfpel pixels for parallelly and efficiently filtering data stream of video without increasing the complexity, cost, size and power consumption of circuitry of an electronic video apparatus.Type: GrantFiled: November 29, 2006Date of Patent: June 7, 2011Assignee: Arcsoft, Inc.Inventor: HongBo Zhu

Patent number: 7925687Abstract: A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is nonzero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.Type: GrantFiled: May 15, 2006Date of Patent: April 12, 2011Assignee: Texas Instruments IncorporatedInventors: Manisha Agarwala, John M. Johnsen, Lewis Nardini

Patent number: 7917566Abstract: A plurality of generalpurpose registers each has a first bit width. A computing unit has a first and a second input end, at least the first input end having a second bit width wider than the first bit width, and performs an arithmetical operation on data supplied from the generalpurpose registers to the first and second input ends. An overflow register having a bit width narrower than the first bit width holds data on figures overflowed as a result of calculation by the computing unit as overflow data and supplies the held overflow data as higherorder bits to at least one input end of the computing unit.Type: GrantFiled: October 10, 2007Date of Patent: March 29, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Jun Tanabe

Patent number: 7860915Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.Type: GrantFiled: May 12, 2006Date of Patent: December 28, 2010Assignee: Xilinx, Inc.Inventors: Vasisht Mantra Vadi, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins

Patent number: 7689640Abstract: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.Type: GrantFiled: June 6, 2005Date of Patent: March 30, 2010Assignee: Atmel CorporationInventors: Erik K. Renno, Ronny Pedersen, Oyvind Strom

Patent number: 7680874Abstract: An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generated on the basis of bit signals (a0a15, b0b15) for the portion from the 1st digit to the 15th digit of the input data, and of carry signal CIN input to the 1st digit, and it is output from CLA 204. Then, carry signal c15 from the 16th digit to the 17th digit is generated based on said generated carry signal c14 and bit signals (a15, b15) of the 16th digit of the input data, and this is output from CIA 205. ExclusiveNOR circuit 206 then operates on said carry signals c14 and c15, and overflow detection signal OVF16 is generated.Type: GrantFiled: January 18, 2005Date of Patent: March 16, 2010Assignee: Texas Instruments IncorporatedInventors: Akihiro Takegama, Tsuyoshi Tanaka, Masahiro Fusumada

Patent number: 7580967Abstract: A method of operating a processor in a variable bitlength environment by performing a maximum limit function and minimum limit function. The method comprises accessing a most significant portion of a first number in a first register, wherein the most significant portion of the first number includes a first value. The method also includes accessing a most significant portion of a second number that includes a maximum/minimum limit, wherein the most significant portion of the second number includes a second value. The method includes changing the most significant portion of the first number to match the most significant portion of the second number if the first value is greater/less than the second value and storing the most significant portion of the first number in the first register.Type: GrantFiled: January 22, 2003Date of Patent: August 25, 2009Assignee: Texas Instruments IncorporatedInventors: Alexander Tessarolo, Karthikeyan Rajan Madathil, G. Subash Chandar

Patent number: 7543014Abstract: In some embodiments a system comprises an overflow control bit, a programmable saturation control bit, a processing unit, and a saturation unit coupled to the processing unit. A selection unit may select the output of the processing unit or the output of the saturation unit based on the state of the saturation control bit. Further, the saturation control unit may output a saturated or unsaturated value based on the overflow control bit.Type: GrantFiled: July 31, 2003Date of Patent: June 2, 2009Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Dominique D'Inverno

Patent number: 7467178Abstract: A system and method for overflow and saturation processing during accumulator operations that reduces the error in a saturation operation. Upon overflow, additional guard bits used in conjunction with an accumulator allow a user to continue processing without any error in the values used in computations following the overflow. A saturation condition can be detected following the overflow the appropriate maximum value stored in the accumulator upon detecting saturation.Type: GrantFiled: June 1, 2001Date of Patent: December 16, 2008Assignee: Microchip Technology IncorporatedInventor: Michael I. Catherwood

Patent number: 7461118Abstract: A saturationcapable arithmetic logic unit (ALU) includes a generalpurpose comparator coupled to receive a data value and a saturation threshold value during a saturation operation. Using the generalpurpose comparator of the ALU for saturation minimizes circuit area without adversely affecting microprocessor performance. In an unsigned saturation operation, the data value is replaced with the threshold value when the data value is greater than the threshold value. In a signed saturation operation, positive data values are compared with an upper threshold value and negative data values are compared with a lower threshold value. In this manner, the data value need only be compared to either the upper or lower threshold value, rather than both. If the data value falls outside the bounds set by the upper and lower threshold values, the data value is replaced with the nearest threshold value.Type: GrantFiled: April 9, 2003Date of Patent: December 2, 2008Assignee: Infineon Technologies AGInventor: Alexander M. Griessing

Patent number: 7428567Abstract: An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carrypropagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry.Type: GrantFiled: July 16, 2004Date of Patent: September 23, 2008Assignee: Sandbridge Technologies, Inc.Inventors: Michael J. Schulte, Erdem Hokenek, Pablo I. Balzola, C. John Glossner

Patent number: 7177893Abstract: A method for determining, by means of a circuit, a result sk+2 of an operation of the type s k + 2 = ( s k ? + • ? a k ) ? + • ? a k + 1 where sk, ak, and ak+1 are fractional signed operands and symbol + • represents a saturating addition operation, comprising: a step of calculation of three sums representative of a possible value of the result, and a step of selection of one of said three sums according to overflows having occurred in the sum calculation. At least one step of the method uses the positive part and the negative part of at least one of the operands.Type: GrantFiled: February 7, 2003Date of Patent: February 13, 2007Assignee: STMicroelectronics S.A.Inventor: Benoît Dupont de Dinechin

Patent number: 7171438Abstract: A method of formulating and solving equations that facilitate recognition of full word saturating addition and subtraction The method includes formulating, for each basis addition statement z=x+y or subtraction statement z=x?y, data flow equations that describe properties of the program statements being analyzed; and solving the data flow equations. The properties may include: (a) the values BITS of program variables as Boolean functions of the sign bits of x, y and z; (b) the condition COND under which program statements are executed as Boolean functions of the sign bits of x, y and z; and (c) the condition REACH of which values of variables reach any given use of z when overflow/underflow/neither occurs.Type: GrantFiled: March 7, 2003Date of Patent: January 30, 2007Assignee: Sandbridge Technologies, Inc.Inventors: Mayan Moudgill, Vladimir Kotlyar

Patent number: 7149766Abstract: Methods of detecting overflow and/or underflow events are provided. The methods are preferably incorporated into a highlevel programming language, but this is not necessary. In one embodiment, an increasing function that may cause overflow for a data element having a value is performed on a surrogate variable having the same value as the data element. The variable is then compared to the value to determine whether the variable, after the function is performed, is greater than the value. If the value is greater than or in some cases equal to the variable, an overflow has occurred. If the value is less than the variable, no overflow has occurred. Additional embodiments determine whether an underflow occurs with a decreasing function in similar fashion, and the function may be performed on either the variable or the value.Type: GrantFiled: November 12, 2002Date of Patent: December 12, 2006Assignee: Unisys CorporationInventors: Kelsey L. Bruso, James M. Plasek, Rachel M. Noack

Patent number: 7089277Abstract: A computation circuit which can obtain n+mdigit accumulation results by using an ndigit computation unit. This computation circuit comprises a computation unit which performs additions of ndigit data; an mdigit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carryover occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n?1?1.Type: GrantFiled: February 19, 2003Date of Patent: August 8, 2006Assignee: Oki Electric Industry Co., Ltd.Inventors: Teruaki Uehara, Keitaro Ishida

Patent number: 7051062Abstract: Apparatus for determining a value, a sign and an overflow status of an addition of at least three nbit data inputs. The apparatus comprising: a first adder, for adding the at least three nbit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of mbit addends, m being smaller than or equal to n. The apparatus further comprising at least two electroniccircuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electroniccircuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.Type: GrantFiled: September 10, 2002Date of Patent: May 23, 2006Assignee: Analog Devices, Inc.Inventor: Michel Jalfon

Patent number: 7047270Abstract: A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is nonzero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.Type: GrantFiled: November 22, 2002Date of Patent: May 16, 2006Assignee: Texas Instruments IncorporatedInventors: Manisha Agarwala, John M. Johnsen, Lewis Nardini

Patent number: 7013321Abstract: According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. The first, second and third input operand registers respectively include a number of first input operands, a number of second input operands and a number of third input operands. Each of the number of functional blocks performs a multiply accumulate operation. The output operand register includes a number of output operands. Each of the number of output operands is related to one of the number of first input operands, one of the number of second input operands and one of the number of third input operands.Type: GrantFiled: November 21, 2001Date of Patent: March 14, 2006Assignee: Sun Microsystems, Inc.Inventor: Ashley Saulsbury

Patent number: 6993545Abstract: A digital filter having the capability to completely prevent the digital filter from generating the overflow oscillation by detecting positive and negative overflow propagating one or a plurality of bits by means of an overflow detecting circuit. When overflow is detected, a clipping circuit serves to fix the output signal to a positive maximum value or a negative maximum value.Type: GrantFiled: September 25, 2001Date of Patent: January 31, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Mikio Shiraishi

Patent number: 6983300Abstract: An arithmetic unit for adding a plurality of values to define a result, the arithmetic unit including circuitry for receiving the plurality of values; circuitry for adding the plurality of values to define a result, the result being within a first range; circuitry for determining if the result falls within a second range, the second range being smaller than the first range, the circuitry arranged to consider only some of the bits of the result; and circuitry for modifying the result in so that the result output by said arithmetic unit falls within the second range.Type: GrantFiled: July 30, 2001Date of Patent: January 3, 2006Assignee: STMicroelectronics S.A.Inventor: Sebastien Ferroussat

Patent number: 6947962Abstract: An algorithm and implementation is described of overflow prediction for addition without the use of an expensive addition operation. This overflow prediction is particularly applicable to the implementation of addition operation using the carrysave format in high speed arithmetic units.Type: GrantFiled: January 24, 2002Date of Patent: September 20, 2005Assignee: Intel CorporationInventor: Yatin Hoskote

Patent number: 6941329Abstract: In a digital electronic method for increasing the calculation accuracy in nonlinear functions and a system for performing the method, wherein an input format has a strictly defined word but the fixed point may be at different locations, the values are so processed that the accuracy of the calculations and also the calculation speed are substantially increased.Type: GrantFiled: July 12, 2001Date of Patent: September 6, 2005Assignee: Forschungszentrum Karlsruhe GmbHInventors: Wolfgang Eppier, Thomas Fischer

Publication number: 20040167954Abstract: A math device has a multiplier and an overflow detector. The multiplier multiplies an nbit input with an mbit input and produces a reduced width output without producing an intervening data file having a width greater than or equal to n+m. The overflow detector determines if the reduced width output eliminates nonredundant bits. According to a second aspect, the overflow detector determines when the product of the mbit input and the nbit input would exceed obits, where o<(m+n), the overflow detector having a first overflow unit provided in parallel to the multiplier, and a second overflow unit provided in series with the multiplier. According to a third aspect, the overflow detector has a comparator provided on a critical timing path, and the comparator requires only a review of 4 bits.Type: ApplicationFiled: February 21, 2003Publication date: August 26, 2004Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventor: Alexander Griessing

Publication number: 20040098439Abstract: An apparatus and method provide for performing either an overflow or underflow comparison while minimizing overflow/underflow comparison circuitry. In particular, the apparatus and are implemented with overflow/underflow possible check circuitry that determines if a mathematical operation between a first exponent signal and a second exponent signal creates a potential overflow condition. The overflow/underflow possible check circuitry generates a signal indicating whether an overflow or underflow condition is a possibility. Exponent compare circuitry computes an actual overflow or underflow condition. The exponent compare circuitry computes an actual overflow condition if the signal, from the overflow/underflow possible check circuitry, indicates that overflow is possible, and computes an actual underflow condition if the signal, from the overflow/underflow possible check circuitry, does not indicate overflow is possible.Type: ApplicationFiled: July 3, 2003Publication date: May 20, 2004Inventors: Stephen L. Bass, Ravi G. Koshy

Patent number: 6718357Abstract: A microcomputer is provided with an upper clip circuit for comparing digital values output from an analogtodigital (AD) converting circuit 1 with a high level reference value A, and replacing a digital value larger than the reference value A with the reference value A; and a lower clip circuit for comparing digital values output from the upper clip circuit with a reference value B, and replacing a digital value smaller than the reference value B with the reference value B. Irregular signal waveforms can be removed by replacing the reference values A, B, thereby enhancing the reliability of operation results.Type: GrantFiled: January 8, 2001Date of Patent: April 6, 2004Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design CorporationInventor: Sanghoon Ha

Publication number: 20040049528Abstract: Apparatus for determining a value, a sign and an overflow status of an addition of at least three nbit data inputs. The apparatus comprising: a first adder, for adding the at least three nbit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of mbit addends, m being smaller than or equal to n. The apparatus further comprising at least two electroniccircuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electroniccircuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.Type: ApplicationFiled: September 10, 2002Publication date: March 11, 2004Inventor: Michel Jalfon

Publication number: 20030182341Abstract: Systems and methods are provided for diffusing clipping error in a computing system. When a data set contains values which are to be restricted to a range, and the data set includes one or more values which are beyond the range, the invention provides methodology that is an improvement over clipping extraneous values to the range or squeezing the values to the range. Advantageously, systems and methods are provided for distributing or diffusing error to neighboring samples of the data set, thereby spreading localized error, and minimizing the effects associated with remapping the data set to the restrictive range.Type: ApplicationFiled: March 20, 2002Publication date: September 25, 2003Applicant: Microsoft Corporation.Inventor: John Michael Snyder

Publication number: 20030163501Abstract: Method and apparatus for reducing the occurrence of overflow in an IIR filter. The feedback state of a filter is stored with double precision and scaleddown to increase range.Type: ApplicationFiled: May 30, 2001Publication date: August 28, 2003Applicant: Sony Corporation and Sony Electronics Inc.Inventors: Chinping Q. Yang, Robert Weixiu Du

Patent number: 6535900Abstract: A processor made up of a computation unit, an accumulator unit, a saturation determination unit and a saturation unit. The computation unit operates on one or more operands of W bits. The accumulator unit stores the output of the computation unit, in W bits. The saturation determination unit detects overflow in parallel with latching of the output of the computation unit. Overflow occurs when the operand latched by the accumulator represents a number having more than A significant bits, where A is less than W. The saturation unit provides saturation operands to the computation unit when the operand latched in the accumulator unit represents a number having more than A significant bits. Furthermore, the processor has saturation operands of either (+2A−1−1) or −2A−1. A method for using the processor is also disclosed.Type: GrantFiled: September 8, 1999Date of Patent: March 18, 2003Assignee: DSP Group Ltd.Inventors: Ronen Perets, Yael Gross, Moshe Sheier

Patent number: 6532486Abstract: A method for saturating data in a register (100) is disclosed. The method comprises shifting data contents in the register (100) by a saturation value and setting at least one bit equal to a sign bit (110) on the register (100). The method further comprises storing the shifted contents in a temporary register (160), which (160) has compare bits (180). The method further comprises setting high bits (150) and low bits (140) to a positive value when the compare bits (180) are not equal to the sign bit (110) and the sign bit indicates a positive data word in the register (100). The method further comprises setting the high bits (150) and low bits (140) to a negative value when the compare bits (180) are not equal to the sign bit (110), and the sign bit (110) indicates a negative data word in the register (100). The method further comprises shifting the set data contents in the register (100) by the saturation value and setting at least one bit equal to a least significant bit (102) on the register (100).Type: GrantFiled: December 15, 1999Date of Patent: March 11, 2003Assignee: Texas Instruments IncorporatedInventor: Alexander Tessarolo

Patent number: 6529930Abstract: Methods and apparatus for performing signed saturation of binary numbers to arbitrary powers of two are described. Given an nbit signed binary word, the methods and apparatus of the present invention perform a signed saturation to kbits where the value of k can vary such that 1<k<n. Through the use of hardware circuits of the present invention the signed saturation operation is implemented in a more efficient manner than software implementations which utilize multiple compare operations. The signed saturation circuits of the present invention can be incorporated into processors, e.g., CPUs, to provide a hardware implementation within a CPU for a signed saturation processor instruction, e.g., either a SISD OR SIMD saturation command or instruction. The signed saturation circuits can accept the data value upon which the operation is to be performed, and, optionally, a value k indicating the number of bits to which individual data value are to be saturated.Type: GrantFiled: September 9, 1999Date of Patent: March 4, 2003Assignee: Hitachi America, Ltd.Inventors: Sharif Mohammad Sazzad, Michael A. Plotnick

Patent number: 6519620Abstract: A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.Type: GrantFiled: April 22, 1999Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Huy Van Nguyen, Michael Putrino, Charles Philip Roth

Patent number: 6499046Abstract: An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input operands, and a plurality of saturation value signals. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carryout signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carryout signals from carry lookahead logic receiving the subvector operands as input.Type: GrantFiled: May 20, 1999Date of Patent: December 24, 2002Assignee: International Business Machines CorporationInventors: Huy Van Nguyen, Charles Philip Roth

Publication number: 20020188640Abstract: A system and method for overflow and saturation processing during accumulator operations that reduces the error in a saturation operation. Upon overflow, additional guard bits used in conjunction with an accumulator allow a user to continue processing without any error in the values used in computations following the overflow. A saturation condition can be detected following the overflow the appropriate maximum value stored in the accumulator upon detecting saturation.Type: ApplicationFiled: June 1, 2001Publication date: December 12, 2002Inventor: Michael I. Catherwood

Publication number: 20020103842Abstract: An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carryoutput signal of the adder. A flag generation circuit is coupled to at least one of the stages and is operative to generate an overflow flag for the adder substantially in parallel with the generation of the sum output signal and the primary carryoutput signal of the adder. Advantageously, the invention substantially reduces the computational delay associated with generation of the overflow flag, relative to that of conventional adders, without requiring an increase in transistor count or circuit area.Type: ApplicationFiled: December 8, 2000Publication date: August 1, 2002Inventor: Alexander Goldovsky

Patent number: RE39121Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sumproduct result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sumproduct result register 6 with the coded 32bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sumproduct result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sumproduct result register 6 to the data bus 18.Type: GrantFiled: February 13, 2003Date of Patent: June 6, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toru Morikawa, Nobuo Higaki, Akira Miyoshi, Keizo Sumida

Patent number: RE43145Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sumproduct result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sumproduct result register 6 with the coded 32bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sumproduct result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sumproduct result register 6 to the data bus 18.Type: GrantFiled: December 21, 2004Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Toru Morikawa, Nobuo Higaki, Akira Miyoshi, Keizo Sumida

Patent number: RE43729Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sumproduct result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sumproduct result register 6 with the coded 32bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sumproduct result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sumproduct result register 6 to the data bus 18.Type: GrantFiled: April 22, 2011Date of Patent: October 9, 2012Assignee: Panasonic CorporationInventors: Toru Morikawa, Nobuo Higaki, Akira Miyoshi, Keizo Sumida