Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A method and system for the use of prediction data in monitoring actual production targets is described herein. In one embodiment, a process is provided to receive data from a plurality of source systems in a manufacturing facility and generate a prediction pertaining to a future state of the manufacturing facility based on the data received from the plurality of source systems. A recent state of the manufacturing facility is determined based on the data received from the plurality of source systems and a comparison between the recent state and the prediction is facilitated.

Abstract: For efficient computation of results for mathematical functions, a method receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function of the function call varies with respect to the values for the arguments. The method determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The method further aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results.

Abstract: Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. An example apparatus obtains a first operand value and a second operand value. The example apparatus then determines if the second operand value subtracted from the first operand value is greater than a minimum value and determines if the first operand value is greater than a sum value associated with a minimum operand value. The example apparatus then asserts an output signal indicative of an absence of an underflow condition associated with a floating-point value based on conditions associated with determining whether the second operand value subtracted from the first operand value is greater than the minimum value and determining if the first operand value is greater than the sum value.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit is combined with an arithmetic shifter and a final decision multiplexor. The final decision multiplexor receives the output from the arithmetic shifter and the saturated value from the saturation circuit. When saturation is detected by the saturation detection circuit, the final decision multiplexor selects the saturate minimum or the saturate maximum depending on whether the MSB of the data in equals one or zero, respectively.

Abstract: Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic devices coupled to the plurality of comparator circuits are operated to determine whether performing a floating-point operation using a floating-point hardware unit will generate an underflow condition. The operating of the plurality of comparator circuits and the logic devices involves inputting a multiply-add operation result value to at least some of the plurality of comparator circuits. In addition, a plurality of logic outputs are outputted via the plurality of logic devices. The plurality of logic outputs are indicative of comparison operations performed by at least some of the comparator circuits based on the multiply-add operation result value. An underflow indicator is outputted based on the plurality of logic outputs.

Abstract: A system and method for unbiased rounding away from, or toward, zero comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M?N bit number, and apparatus for adding the equivalent value of ‘½’ to the M?N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½.

Abstract: A method and system for determining whether a result d of a floating-point operation on operands a, b, c is tiny (may underflow) is disclosed. In one embodiment, a prediction whether d is tiny is made in hardware, but this prediction may include false results. Operands a, b, c are scaled to a?, b?, c? and then result d? from the floating-point operation on operands a?, b?, c? is calculated. A determination whether d will actually be tiny can be determined from the value of d?. A decision may then be made to proceed with either software or hardware calculations of d.

Abstract: A method is provided for efficient computation of reliable results for mathematical functions. The method may include an interface, a control module, and an error module. The interface receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function varies with respect to the values for the arguments. The control module determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The error module aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results.

Abstract: An apparatus and system are provided for efficient computation of reliable results for mathematical functions. The apparatus may include an interface, a control module, and an error module. The interface receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function varies with respect to the values for the arguments. The control module determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The error module aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage; scales the butterfly outputs of this stage from a predicted normalization scale factor to obtain the maximum butterfly output without overflow from this stage; determines from the butterfly outputs of this stage the minimum normalizing exponent for the butterfly outputs of this stage and predicts a normalization scale factor of the next stage from the minimum normalizing exponent of this stage and a stage guard scale value to obtain the maximum butterfly output without overflow from that next stage.

Abstract: An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection. This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.

Abstract: An arithmetic unit for adding a plurality of values to define a result, the arithmetic unit including circuitry for receiving the plurality of values; circuitry for adding the plurality of values to define a result, the result being within a first range; circuitry for determining if the result falls within a second range, the second range being smaller than the first range, the circuitry arranged to consider only some of the bits of the result; and circuitry for modifying the result in so that the result output by said arithmetic unit falls within the second range.

Abstract: A method for arithmetic expression optimization includes receiving a first instruction defined for a first processor having a first base, the first instruction including an operator and at least one operand, converting the first instruction to a second instruction optimized for a second processor having a second base when all operands do not carry potential overflow or when the operator is insensitive to overflow, the second base being smaller than the first base, and converting to a wider base a third instruction that is the source of the overflow when the at least one operand the potential for overflow and when the operator is sensitive to overflow.

Abstract: A system for accurately and efficiently determining the result of an integer multiple-divide operation having the form of (A*B)/C is disclosed. If the values of A, B, and C provide for an easy solution (e.g., A, B, or C are zero, A equals C or B equals C, or A or B equals one), the result is directly computed. Otherwise, if the product of A and B would produce an overflow condition, A and/or B are scaled by a tracked number of bits so that the product of scaled A and B would fit in an integer variable of the current computing system. Then, the product of scaled or unscaled A and B is computed. If C is large compared to the calculated product of A*B, C is scaled to minimize the likelihood of a false zero as a result. Then, the result is scaled if required. Thus, the result of an integer multiple-divide operation having the form of (A*B)/C is efficiently determined according to the system for accurately and efficiently performing an integer multiply-divide operation.

Abstract: An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at least one of the stages and is operative to generate an overflow flag for the adder substantially in parallel with the generation of the sum output signal and the primary carry-output signal of the adder. Advantageously, the invention substantially reduces the computational delay associated with generation of the overflow flag, relative to that of conventional adders, without requiring an increase in transistor count or circuit area.

Abstract: Within a content addressable memory, the latency in a memory access is reduced by combining the steps of effective address generation addition and searching within the content-addressable memory. Two inputs to the content-addressable memory are conditioned and then supplied to matching cells, which determine which address stored in the content-addressable memory will be output. This is accomplished without a full adder being implemented to add the two input operands before being supplied to the content-addressable memory.

Abstract: A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of the floating point adder. The leading zero anticipator outputs a control signal to a shifter to shift the sum of the significand adder to eliminate the leading zeros. The number of leading zeros is also provided to an exponent circuit that reduces the magnitude of the exponent to reflect the shifted significand. The leading zero anticipator includes a pattern generator that outputs an intermediate pattern with a number of leading zeros approximately equal to the number of leading zeros in the sum. A counter circuit counts the number of leading zeros and provides one or more one-hot control signals to the shifter. In one embodiment, the significand shifter implements two stages of one-hot multiplexers to provide the desired shift.