Abstract: A method for calculating a square root B having N bits of a number X having 2N bits includes iterating on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteration, the method includes locating a 1 at the squared location of bit bi in a CHECK variable, determining the value of bit bi from the result of a comparison of number X with a function of all previously found bits and a previous comparison outcome, shifting all previously found bits right 1 location in a CHECK variable, and adding the determined value of bit bi into its squared location in the CHECK variable.

Abstract: Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.

Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 ? / ? d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Abstract: A method, system and computer program product for disambiguating meaning of terms. A natural language processing system obtains a first corpora of words used in a first sense and a second corpora of the same words that are used in a second sense. Each of these corpora of words may be associated with different linguistic domains. The natural language processing system generates a first and a second set of patterns using both the first and second corpora of words, respectively. A question passage is then received by the natural language processing system. The natural language processing system examines a word of interest in the question passage. The user is then notified that the word of interest is being used in the first sense or the second sense in response to identifying the word of interest in only the first set of patterns or the second set of patterns, respectively.

Abstract: Apparatuses and methods of manufacturing same, systems, and methods for generating a starting estimate for radix-16 square root iterative calculation using hardware, including a radix-4 partial remainder-divisor (PD) table, which is used for both division and square root operations, are described. In one aspect, a part of a radicand for a radix-16 square root iterative operation is used to determine column/root and row/partial radicand values, which are then used to determine a starting estimate from a radix-4 PD table for the radix-16 square root iterative operation.

Abstract: Embodiments of the inventive concept include a shared hardware integer/floating point divider and square root logic unit, which combines floating point division, floating point square root operations, and/or integer division into one shared hardware design. The shared hardware logic unit can share, for example, a sparse random access memory (sparse RAM) in place of a full partial remainder divisor (PD) table, one or more on-the-fly (OTF) state machines, and/or a data path for integer division, floating point division, and square root operations. The normalization of subnormal numbers and the normalization of signed and unsigned integers can be handled with shared hardware. The division operations and the square root operations can be of the same radix. Early out exceptions and special cases can be automatically handled. Both improved latency and less die area can be achieved in accordance with embodiments of the inventive concept.

Abstract: Signal processing may include determining a first component common to a first input signal and a second input signal and extracting the first component from at least one of the first input signal or the second input signal, a second component from the first input signal, and a second component from the second input signal. The second component of the first input signal may be different from the second component of the second input signal. An operation may be performed using the extracted, second components. The first component may be combined with a result of the operation.

Abstract: A residue-based error checking mechanism is provided for checking for error in a shift operation of a shifter. The checking includes: partitioning an input vector into the shifter into one or more bit groups of bit width W; generating a predicted residue on the input vector being shifted, the generating including masking out any bit group of bit width W fully shifted out by the shift operation from contributing to the predicted residue, and the generating accounting for any bits of a bit group of the input vector partially shifted out by the shift operation; generating a result residue on a result vector of the shift operation; and comparing the result residue with the predicted residue to check for an error in the result vector of the shift operation.

Abstract: A data processing apparatus has a processing circuitry for performing a floating-point square root operation on a radicand value R to generate a result value. The processing circuitry has first square root processing circuitry for processing radicand values R which are not an exact power of two and second square root processing circuitry for processing radicand values which are an exact power of 2. Power-of-two detection circuitry detects whether the radicand value is an exact power of two and selects the output of the first or second square root processing circuitry as appropriate. This allows the result to be generated in fewer processing cycles when the radicand is a power of 2.

Abstract: A method and computer system are provided for implementing a square root operation using an iterative converging approximation technique. The method includes fewer computations than conventional methods, and only includes computations which are simple to implement in hardware on a computer system, such as multiplication, addition, subtraction and shifting. Therefore, the methods described herein are adapted specifically for being performed on a computer system, e.g. in hardware, and allow the computer system to perform a square root operation with low latency and with low power consumption.

Abstract: Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port.

Abstract: Methods and circuitry for evaluating reciprocal, square root, inverse square root, logarithm, and exponential functions of an input value, Y. In one embodiment, an approximate value, RA, of the reciprocal of Y is generated. One Newton-Raphson iteration is performed as a function of RA and Y, resulting in a truncated approximate value, R. R is multiplied by Y and 1 is subtracted, resulting in a reduced argument, A. A Taylor series evaluation of A is performed, resulting in an evaluated argument, B. B is multiplied by a post-processing factor for the final result.

Abstract: Presently a direct analytical method, vide the Babylonian method developed in 1800 B.C., is available for the digit-by-digit extraction of the square root of a given positive real number. To calculate the nth root of a given positive real number one may use trial and error method, iterative method, etc. When one desires to determine the nth root, it is found that such methods are inherent with certain weaknesses like the requirement of an initial guess, a large number of arithmetic operations and several iterative steps for convergence, etc. There has been no direct method for the determination of the nth root of a given positive real number. This paper focuses attention on developing a numerical algorithm to determine the digit-by-digit extraction of the nth root of a given positive real number up to any desired accuracy. The analytic method contained in this paper would enable one to carry out digit-by-digit extraction of the nth root of a given positive real number which can be directly implemented.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi-1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

Abstract: A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

Abstract: An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m?1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.

Abstract: An amplitude calculation apparatus or an amplitude calculation program of an output signal of an encoder dividing a resurge waveform into a predetermined number of angle areas, presetting and storing coefficient ? of the A-phase and the coefficient ? of the B-phase corresponding to the divided angle areas, the coefficients being set so that ?A+?B approximates the radius of the theoretical resurge waveform, calculating the radius of the resurge waveform as ?A+?B, and making the calculated radius the amplitude of the output signal of the encoder or converting a phase angle ? of a quadrant n to a phase angle ?? of the quadrant 1, and calculating the radius of the resurge waveform as ?|A|+?|B|, whereby the circuit size of the apparatus for calculating the resurge radius from the output of the encoder is reduced and the processing time by software for calculating the resurge radius is shortened.

Abstract: A system and method are provided for use in an electronic device configured to process data to perform a method of generating a fixed point approximation of a number x by first locating the most significant bit of a given number, then retrieving predetermined values from electronic data storage, where the first value is based on a first index value generated from the most significant bit and contains fixed-point representation located in a table in storage. Then, output values are generated from look-up tables that correspond to index values generated from a number of bits that immediately following the most significant bit. Finally, the final mathematic result is computed using fixed-point arithmetic logic to generate a fixed point approximation.

Abstract: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.

Abstract: In one aspect, there is provided a digital logic circuit that comprises circuitry for generating a new iteration xn+1 of the reciprocal square root of A from the previous iteration xn by (i) multiplying the previous iteration xn by the number A; (ii) multiplying the result of (i) by the previous iteration xn; (iii) subtracting the result of (ii) from 3; and (iv) multiplying the result of (iii) by half of the previous iteration xn. According to another aspect there is provided a calculator unit for determining an initial value for use in a iterative process for calculating an estimate of the reciprocal square root of a number A, the calculator unit comprising circuitry for (a) rounding the number A to the nearest number of the form 2J, where J is an integer; (b) if J is odd, rounding J up to the nearest even number to give J?; (c) if J is even, setting J to J?; and (d) calculating 2?(J?/2) to determine the initial value for the reciprocal square root of A.

Abstract: A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible.

Abstract: Disclosed is a method for factoring integers by squaring computation time. The present invention uses binary numbers to process invert function of multiplication as factorization. Inverse method of integer factorization uses a diamond expansion form to arrange the digit positions of 1-numbers and 0-numbers subtracted from the product number P and its complement number No. The complement number N0 is the difference between the product number P and the square of the whole-1-number 1n2. The square of the whole-1-number 1n2 equals to the number of that first n-1 digits are 1s, followed by n 0s, and ended by 1.

Abstract: A method, apparatus and system to ensure the security in the information exchange and to provide list matching with higher efficiency and practicality. In a particular embodiment, each of lists to be subject to list matching is represented as a polynomial having roots equivalent to the items of the list. Then, polynomials generated for the lists to be subject to list matching are added according to a distributed secret computation. A list containing an item equivalent to a root of a polynomial resulting from the addition is created and output as the list of a common item.

Abstract: Circuitry for solving linear matrix equations involving a resultant matrix, an unknown matrix and a product matrix that is a product of the resultant matrix and the unknown matrix includes matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below the resultant matrix elements on the diagonal. The matrix decomposition circuitry includes an inverse square root multiplication path that computes diagonal elements of the resultant matrix having an inverse square root module, and the said inverse square root module computes inverses of the diagonal elements to be used in multiplication in place of division by a diagonal element. Latency is hidden by operating on each nth row of a plurality of matrices prior to any (n+1)th row.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi?1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: A method, apparatus and system to ensure the security in the information exchange and to provide list matching with higher efficiency and practicality. In a particular embodiment, each of lists to be subject to list matching is represented as a polynomial having roots equivalent to the items of the list. Then, polynomials generated for the lists to be subject to list matching are added according to a distributed secret computation. A list containing an item equivalent to a root of a polynomial resulting from the addition is created and output as the list of a common item.

Abstract: An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions and also combining input terms to reduce the total number of terms that remain to be processed. By progressively combining the active terms into a smaller number of terms for subsequent processing, the time needed to process a result can be significantly reduced.

Abstract: A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of a carry save adder and the output of the adder are input to convert the data into twos complement representation data, and the twos complement representation data is shifted a certain bit number (determined on the basis of the radix of the operation) to use the shifted data for a partial remainder of the next digit. Hence, a large number of parts such as registers of a divisor and a partially extracted square root can be commonly used in a divider and a square root extractor to realize an effective and high performance arithmetic unit.

Abstract: One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a divide or a square-root operation to produce a result, which includes one or more additional bits of accuracy beyond a desired accuracy for the result. Next, the system rounds the result to the desired accuracy to produce a rounded result t. The system then analyzes the additional bits of accuracy to determine whether t is correct and whether t is exact.

Abstract: Sensor data is received from one or more sensors. The sensor data is organized within a hierarchy. The sensor data is organized within a hierarchy that is non-dyadic. A processor of a computing device generates a discrete wavelet transform, based on the sensor data and based on the hierarchy of the sensor data, to compress the sensor data. The sensor data, as has been compressed via generation of the discrete wavelet transform, is processed.

Abstract: A phase calculation apparatus using a binary search is provided. The phase calculation apparatus includes a quarter surface preprocessor determining the bigger one between an absolute value of I component data and an absolute value of Q component data as horizontal component data and the smaller one as perpendicular component data, and detecting information on a phase region indicating an mth (m=1 to 8) phase region (the mth phase region is between (m?1) ?/4 and m ?/4 in which the I/Q component data are located; a phase representative value detector detecting phase representative values x corresponding to the horizontal component data and the perpendicular component data; and a quarter surface postprocessor calculating phase values of the I/Q component data based on the detected information about the phase region and the detected phase representative values x. The phase can be calculated using a limited memory, low complexity of calculation and regardless of the number of bits of I/Q component data.

Abstract: In general, techniques are described that provide for 4×4 transforms for media coding. A number of different 4×4 transforms are described that adhere to these techniques. As one example, an apparatus includes a 4×4 discrete cosine transform (DCT) hardware unit. The DCT hardware unit implements an orthogonal 4×4 DCT having an odd portion that applies first and second internal factors (C, S) that are related to a scaled factor (?) such that the scaled factor equals a square root of a sum of a square of the first internal factor (C) plus a square of the second internal factor (S). The 4×4 DCT hardware unit applies the 4×4 DCT implementation to media data to transform the media data from a spatial domain to a frequency domain. As another example, an apparatus implements a non-orthogonal 4×4 DCT to improve coding gain.

Abstract: Described is a technology, such as implemented in a computational software program, by which a minimal polynomial is efficiently determined for a radical expression over the ring Z of integer numbers or the ring Q of rational numbers. The levels of the radical are grouped into a level permutation group that is used to find a level permutation set. An annihilation polynomial is found based upon the level permutation set. The annihilation polynomial is factored, and a selection mechanism selects the minimal polynomial based upon the annihilation polynomial's factors.

Abstract: A method for selecting a set of parameters from a parameter space of a contemplated implementation of a pipelined processor for configuring the processor to generate an output word in response to each of a set of input words. The method includes determining a mapping between each set of parameters in the parameter space and the area of an integrated circuit implementation of the processor, and searching the parameter space to select a preferred set of the parameters that minimizes the area of the integrated circuit implementation subject to the constraints that each of the input word and the output word has specified format and that the preferred set of the parameters results in no more than a specified maximum error between the function of each of the input values and the approximation of the function of said each of the input values.

Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m-1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.

Abstract: A function that represents data points is derived by creating a matrix (e.g., a Hankel matrix) of an initial rank, where the matrix contains the data points. Singular values are derived based on the matrix, and it is determined whether a particular one of the singular values satisfies an error criterion. In response to determining that the particular singular value does not satisfy the error criterion, the rank of the matrix is increased and the deriving and determining tasks are repeated. In response to determining that the particular singular value satisfies the error criterion, values of parameters that approximate the function are computed.

Abstract: Described is a technology, such as implemented in a computational software program, by which a minimal polynomial is efficiently determined for a radical expression based upon its structure of the radical expression. An annihilation polynomial is found based upon levels of the radical to obtain roots of the radical. A numerical method performs a zero test or multiple zero tests to find the minimal polynomial. In one implementation, the set of roots corresponding to a radical expression is found. The annihilation polynomial is computed by grouping roots of the set according to their conjugation relationship and multiplying factor polynomials level by level. A selection mechanism selects the minimal polynomial based upon the annihilation polynomial's factors.

Abstract: Certain embodiments described herein are directed to chromatography systems that include a microfluidic device. The microfluidic device can be fluidically coupled to a switching valve to provide for selective control of fluid flow in the chromatography system. In some examples, the microfluidic device may include a charging chamber, a bypass restrictor or other features that can provide for added control of the fluid flow in the system. Methods of using the devices and methods of calculating lengths and diameters to provide a desired flow rate are also described.

Abstract: One embodiment of the present invention provides a system that efficiently performs an accuracy-check computation for Newton-Raphson divide and square-root operations. During operation, the system performs Newton-Raphson iterations followed by a multiply for the divide or square-root operation. This result is then rounded to produce a proposed result. Next, the system performs an accuracy-check computation to determine whether rounding the result to a desired precision produces the correct result. This accuracy-check computation involves performing a single pass through a multiply-add pipeline to perform a multiply-add operation. During this single pass, a Booth encoding of an operand in a multiply portion of the multiply-add pipeline is modified, if necessary, to cause an additional term for the accuracy-check computation to be added to the result of the multiply-add operation.

Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.

Abstract: A system and method are provided for use in an electronic device configured to process data to perform a method of generating a fixed point approximation of a number x by first locating the most significant bit of a given number, then retrieving predetermined values from electronic data storage, where the first value is based on a first index value generated from the most significant bit and contains fixed-point representation located in a table in storage. Then, output values are generated from look-up tables that correspond to index values generated from a number of bits that immediately following the most significant bit. Finally, the final mathematic result is computed using fixed-point arithmetic logic to generate a fixed point approximation.

Abstract: A method and apparatus receiving number and using instruction to create resulting number approximating one of square root, reciprocal, or reciprocal square root of number. The resulting number as a product of that process. Using resulting number in a graphics accelerator. Apparatus preferably includes log-calculator, log-arithmetic-unit, and exponential-calculator. At least one of log-calculator and exponential-calculator include implementation non-linear calculator. The non-linear calculators may use at least one of mid-band-filter, outlier-removal-circuit. The invention includes making arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator. The arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator as products of manufacture. The arithmetic circuit may further include at least one of a floating-point-to-log-converter and/or a second of log-calculators.

Abstract: A nonlinear conversion system using precision mapping and the method thereof are described. The system includes a source value converter, a mapping table unit, a recovering parameter computing unit, and an output computing unit. The method includes the steps of: receiving an input value; converting the input value into a source value; mapping the source value to a destination value in a limited domain for restricting the calculation within a destination domain; establishing a mapping table by directly selecting a precision according to the destination domain and inverse-mapping back to a source domain; and outputting the destination value according to the mapping table, combining the destination value with a recovering parameter for recovering an output value produced by the nonlinear conversion of the input value.

Abstract: One embodiment of the present invention provides a system that uses the Newton-Raphson technique to compute a square-root. During operation, the system receives a radicand b. Next, the system calculates the square root of b, ?{square root over (b)}, by first using the Newton-Raphson technique to find 1/?{square root over (b)}, and then multiplying 1/?{square root over (b)} by b to produce ?{square root over (b)}. While using the Newton-Raphson technique to find 1/?{square root over (b)}, the system first obtains an initial estimate x0 for 1/?{square root over (b)} and then iteratively solves the equation x i + 1 = x i ? ? ( 3 - bx i 2 2 ) .