Abstract: An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The translation logic decodes the square root macro instruction into a plurality of prescribed-precision machine instructions according to the square root calculation precision specified by the plurality of square root instructions. The execution logic, coupled to the translation logic, receives the plurality of prescribed-precision machine instructions and calculates the square root of the operand according to the specified square root calculation precision. At least one of the plurality of square root instructions specifies the square root calculation precision such that less significant bits are calculated in the square root than are provided in the operand.

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1.ltoreq.x<2, and one lookup table is used, having an interval size of 1/32. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table). In another implementation, the input value is normalized within the range 0.5.ltoreq.

Abstract: A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

Abstract: A processor capable of efficiently evaluating constant powers of an operand such as the reciprocal and reciprocal square root is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to evaluate constant powers of an operand such as the reciprocal and reciprocal square root. Intermediate products that are formed may be rounded and normalized in two paths, one assuming an overflow will occur, and then compressed and stored for use in the next iteration. The processor comprises a multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier may performing rounded by adding a rounding constant.

Abstract: An iterative division and/or iterative square root circuit 20 uses quotient digits q.sub.j+1 within the calculation that are dependent upon the input divisor D or radicand A and current partial remainder or partial radicand P.sub.j for the cycle reached. As the input divisor D or radicand A is fixed throughout the calculation, the critical path through the iterative circuit may be speeded up by preselecting and storing a subset QC of quotient digit values using a primary quotient digit selecting circuit 18, 22 operating in dependence upon the divisor D or radicand A and independently of the partial remainder or partial radicand P.sub.j. Within the iterative circuit 20, the quotient digits q.sub.j+1 to be used for each cycle can then be selected from this subset QC by a secondary quotient digit selecting circuit 24 in dependence upon the partial remainder or partial radicand P.sub.j and independent of the divisor D or radicand A.

Abstract: A data processing apparatus (200) which improves the accuracy of resultant data. The data processing apparatus includes an input (220, 222) configured to receive input data. The input data includes data corresponding to an input coefficient to be multiplied by the square root of two (.sqroot.2) and input addend. The data processing apparatus further includes a first memory (202) for storing a coefficient of the square root of two, a second memory (204) for storing an addend, a summer (206, 208) which independently sums the input coefficient and the coefficient to produce a combined coefficient and sums the input addend and the addend to produce an addend sum, a multiplier (210) which multiplies the combined coefficient and an approximation of the square root of two to produce an intermediate result, and a summer (214) which sums the intermediate result and the addend sum to produce the resultant data.

Abstract: An envelope detection method by using a peel cone approximation concept and an envelope detection circuit which implements the envelope detection method are disclosed. The envelope detection circuit includes an absolute value-determining circuit, a maximum/minimum value-determining circuit, a plurality sets of comparison circuits, an address encoder, a read only memory (ROM), and a multiplier/adder. A delaying circuit for synchronization is further included in the envelope detection circuit. With the method and the circuit for an envelope detection by using a peel cone approximation, advantages of a compact circuit structure, less operation latency, a low approximation error and a low cost are all achieved.

Abstract: A processor system apparatus and method for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system.