Abstract: A resampling method based on window function for flexible sampling rate conversion in broadband frequency measurement devices is described. The resampling algorithm can satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are analyzed, and the design criterion of the filter in resampling model is considered. A fractional delay filter design model based on window function method is described. A fractional delay filter matrix, which is expressed by polynomial form, is constructed. Then the expression related to subfilter coefficients is obtained and subfilter coefficients are solved for by the least square method.

Abstract: Embodiments of systems, apparatuses, and methods for dual complex number multiplication and addition in a processor are described. For example, execution circuitry executes a decoded instruction to multiplex data values from positions in source operands to a multiplier, the source operands including pairs complex numbers, calculate a real part of a product of each pair of complex numbers, add the real part of the product of a first pair of complex numbers to the real part of the product of a second pair of complex numbers to calculate a first real result, and add the real part of the product of a third pair of complex numbers to the real part of the product of a fourth pair of complex numbers to calculate a second real result, and store the results to corresponding positions in the destination operand.

Abstract: This application relates to the communications field, and discloses a signal transmitting method and apparatus, a transmitter, and a signal transmission system. An example method includes: generating a real-number-type signal; performing phase rotation processing on the real-number-type signal to obtain a complex-number-type signal, where a value of a real part signal of the complex-number-type signal is equal to a value of an imaginary part signal of the complex-number-type signal; and transmitting the complex-number-type signal to a receiver.

Abstract: Computational apparatus includes a systolic array of processing elements. In each of a sequence of processing cycles, the processing elements in a first row of the array each receive a respective first plurality of first operands, while the processing elements in a first column of the array each receive a respective second plurality of second operands. Each processing element, except in the first row and first column, receives the respective first and second pluralities of the operands from adjacent processing elements in a preceding row and column of the array. Each processing element multiplies pairs of the first and second operands together to generate multiple respective products, and accumulates the products in accumulators. Synchronization logic loads a succession of first and second vectors of the operands into the array, and upon completion of processing triggers the processing elements to transfer respective data values from the accumulators out of the array.

Abstract: Embodiments of systems, apparatuses, and methods for dual complex number by complex conjugate multiplication in a processor are described. For example, execution circuitry executes a decoded instruction to multiplex data values from a plurality of packed data element positions in the first and second packed data source operands to at least one multiplier circuit, the first and second packed data source operands including a plurality of pairs complex numbers, each pair of complex numbers including data values at shared packed data element positions in the first and second packed data source operands; calculate a real part and an imaginary part of a product of a first complex number and a complex conjugate of a second complex number; and store the real result to a first packed data element position in the destination operand and store the imaginary result to a second packed data element position in the destination operand.

Abstract: According to an aspect, a digital signal processor obtains a program instruction, selects a first real valued input or a second real valued input as a given real valued input (the first and second real valued inputs organized as adjacent elements of a first input vector), depending on an instruction type. The processor performs an arithmetic operation on the selected real valued input to provide a real valued result, and provides a first real valued output and a second real valued output during a first operation cycle (organized as adjacent elements of a second output vector). The real valued result is provided as the first real valued output and as the second real valued output, depending on the instruction type, and the second output vector is a real valued second output vector for real-complex multiplication with a complex valued third vector.

Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: An information processing apparatus includes a memory; and a processor. The processor is configured to execute partitioning a predetermined matrix whose values of elements are to be generated by a matrix operation, into a predetermined number of first submatrices whose dimension in at least one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers used for the matrix operation, and into the predetermined number of second submatrices that are different from the predetermined number of the first submatrices; and assigning a matrix operation to generate values of elements of each of the predetermined number of the first submatrices, and a matrix operation to generate values of elements of each of the predetermined number of the second submatrices, to each of the predetermined number of threads.

Abstract: Disclosed embodiments relate to efficient complex vector multiplication. In one example, an apparatus includes execution circuitry, responsive to an instruction having fields to specify multiplier, multiplicand, and summand complex vectors, to perform two operations: first, to generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and to generate a temporary vector using a fused multiply-add (FMA) circuit having A, B, and C inputs set to the specified multiplier, the double-even multiplicand, and the specified summand, respectively, and second, to generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, to generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and to generate a result using a second FMA circuit having its even product negated, and having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively.

Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

Abstract: Provided are a method and apparatus for modulating data including a controller. The controller is configured to determine sizes of a first complex-number component and a second complex-number component of input data, and determine a cell to assign a sine wave to the input data, based on a difference between the sizes of the first complex-number component and the second complex-number component.

Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.

Abstract: A method of transmitting information between a plurality of radioelectric stations and an associated transmission network are disclosed. In one aspect, the method transmits information between radioelectric stations, each station including a transmitter and a receiver, the information including NbMot words of data, NbMot being an integer >1.

Abstract: The system has first, second, third, and fourth subsystems. Each subsystem has first and second multipliers coupled, respectively, to first and second adders. Each multiplier has two inputs. The first adder is coupled to a first output, a first accumulator, and a bit shifter. The bit shifter is coupled to a third adder. The third adder is coupled to a multiplexer. The multiplexer is coupled to a second output and a second accumulator. The second adder is coupled to the third adder and the multiplexer. The first outputs of the first and second subsystems are coupled directly to a fourth adder, the second outputs of the first and second subsystems are coupled directly to a fifth adder, the first outputs of the third and fourth subsystems are coupled directly to a sixth adder, and the second outputs of the third and fourth subsystems are coupled directly to a seventh adder.

Abstract: An embodiment includes a method for computing operations, such as modular exponentiation, using a mix of vector and scalar instructions to accelerate various applications such as encryption protocols that rely heavily on large number arithmetic operations. The embodiment requires far fewer instructions to execute the operations than more conventional practices. Other embodiments are described herein.

Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

Abstract: A specialized processing block is configurable as one ternary linear decomposition or two binary linear decompositions to perform large multiplications using smaller multipliers, and includes a first number of multiplier circuits of a first size, a second number of pre-adders, and a third number of block inputs. The block inputs are connected to a first subset of the multiplier circuits, and to the pre-adders which are connected to a second subset of the multiplier circuits. There is also a fourth number of additional inputs. A plurality of shifters shift partial product outputs of each of the multipliers by various shift amounts. A joint adder structure combines the shifted partial products. Controllable elements controllably select between different configurations of inputs to the multipliers and pre-adders, controllably connect and disconnect certain ones of the shifted partial products, and selectively split the joint adder structure into two smaller adder structures.

Abstract: A method for processing a digital signal, comprising the following steps: receiving a complex-valued input data array with a processor; converting the complex-valued input data array into a quantized polar domain by approximating magnitude and quantizing the phase data of the input data array with the processor; storing the approximated magnitude in a phase-column indexed matrix in a memory store that is operatively coupled to the processor; processing the input data array with the processor such that all multiplications and summations that would occur during signal processing of the input data array in the Cartesian domain are substituted with circular row shifts and additions of phase-column indexed values in the quantized polar domain; and converting the processed input data array back into the Cartesian domain.

Abstract: Provided two CORDIC processors, each including: two input ports representing real and imaginary input ports; and two output ports representing real and imaginary output ports; wherein real and imaginary parts of a first input signal are applied to the imaginary input ports of the first and second CORDIC processors; real and imaginary parts of a second input signal are applied to the real input ports of the first and second CORDIC processors; the first and second CORDIC processors rotate the respective input signals applied thereto by 45 degrees in the clockwise direction; respective data from the real output ports of said first and second CORDIC processors constitute real and imaginary parts of a first output signal; and respective data from the imaginary output ports of said first and second CORDIC processors constitute real part and imaginary part of a second output signal.

Abstract: A multiply-accumulate unit (MAU) configurable to perform both real and complex multiplication operations, a method of performing a mac operation and a processing unit incorporating the MAU or the method. In one embodiment, the MAU includes: (1) a first multiplier having a first vector input and a first scalar input and configured to multiply a first vector by a first scalar to yield a first product, (2) a second multiplier having a second vector input and a second scalar input and configured to multiply a second vector by a second scalar to yield a second product and (3) an accumulator coupled to the first multiplier and the second multiplier and configured to receive the first and second products.

Abstract: A configurable multiplier circuit for multiplying both real and complex numbers is included in a PLD. In one embodiment, the circuit includes two adder trees. Multiplexers are used such that a conventional multiplier component is not required. The circuit is programmable to operate in one of two modes. In a first mode, the circuit multiplies the four parts of two complex numbers and outputs two values, the real portion of the product and the imaginary portion of the product. In a second mode, each of two portions of the circuit multiplies two pairs of real numbers and outputs the products.

Abstract: Methods and apparatus for testing software with real-time source data from a projectile according to various aspects of the present invention operate in conjunction with a real-time data source, a signal processor, a recordable medium, and a testing platform. The signal processor receives real-time data from a real-time data source during a test and saves it to a storage medium before providing the real-time data to the testing platform for permanent storage. During a subsequent test, the testing platform may upload the saved real-time data to the signal processor foregoing the need to generate new real-time data from the real-time data source.

Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.

Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Abstract: Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit length) from a first register having a register length of at least 2m+1 bits, and also receives third and fourth complex data (each having 2m-bit length) from a second register having a register length of at least 2m+1 bits, to calculate a sum of real parts or imaginary parts of a complex product of the first and third complex data and a complex product of the second and fourth complex data. The complex-MAC unit adds the obtained sum of the real parts or imaginary parts to a stored value of the third register, and overwrites the third register with the cumulative total value. The third register has a register length of at least 2m+2 bits.

Abstract: A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Abstract: Provided are an apparatus and method for performing a complex number operation using a Single Instruction Multiple Data (SIMD) architecture. A SIMD operation apparatus may perform, in parallel, a real part operation and an imaginary part operation of a plurality of complex numbers. The real part operation and the imaginary part operation may be performed sequentially, or in parallel.

Abstract: Embodiments of systems, apparatuses, and methods for performing a complex multiplication instruction in a computer processor are described. In some embodiments, the execution of such instruction causes a real and an imaginary component resulting from the multiplication of data of first and second complex data source operands to be generated and stored.

Abstract: The present invention relates to a complex multiplier and a twiddle factor generator.

Abstract: The quality of signals during SDMA is raised. In an uplink, a signal processing unit receives signals respectively from a plurality of terminal apparatuses which have been multiple-accessed by division of time. It derives receiving channel characteristics corresponding to the plurality of terminal apparatuses, respectively, for each time slot. In a downlink, the signal processing unit derives transmitting channel characteristics from the receiving channel characteristics derived and, based on the transmitting channel characteristics derived, it transmits signals respectively to the plurality of terminal apparatuses to which SDMA has been performed.

Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.

Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which a real part and an imaginary part of a product of the multiplying can be stored in a same register of the processor. First data is conveyed along at least a first interconnect of the processor. The first data has a first operand. The first operand represents a first complex number. Second data is conveyed along at least a second interconnect of the processor. The second data has a second operand. The second operand represents a second complex number. The first operand is multiplied at the execution unit by the second operand to produce a first result. The first result represents a third complex number. Third data is stored at a first register of the processor. The third data has the first result. The first result has at least the product of the multiplying.

Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which all four scalar multiplications, concomitant to multiplying two complex numbers, can be performed in parallel. A real part of a first complex number is multiplied at the execution unit by a real part of a second complex number to produce a first part of a real part of a third complex number. An imaginary part of the first complex number is multiplied at the execution unit by an imaginary part of the second complex number to produce a second part of the real part of the third complex number. A first arithmetic function is performed at the execution unit between the first part of the real part of the third complex number and the second part of the real part of the third complex number. The imaginary part of the first complex number is multiplied at the execution unit by the real part of the second complex number to produce a first part of an imaginary part of the third complex number.

Abstract: Methods and apparatus for an encryption processor for performing accelerated computations to establish secure network sessions. The encryption processor includes an execution unit and a decode unit. The execution unit is configured to execute Montgomery operations and including at least one adder and at least two multipliers. The decode unit is configured to determine if a square operation or a product operation needs to be performed and to issue the appropriate instructions so that certain multiply and/or addition operations are performed in parallel in the execution unit while performing either the Montgomery square or Montgomery product operation.

Abstract: A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a?b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and ?1 and 2) the difference (a?b) multiplied by one of +1 and ?1.

Abstract: A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.

Abstract: A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports multiple-execution instructions that allow a single instruction to perform multiple moves into accumulators for efficient data movement inside MFE.

Abstract: A frequency translator uses a CORDIC phase rotator coupled to a phase accumulator to translate an input signal in frequency. The CORDIC phase rotator performs required phase angle rotations of input vectors using only shift and add operations. Thus, the frequency translator can be readily implemented in hardware. Higher precision arithmetic is used in the CORDIC phase rotator operations than the input vectors contain. To avoid truncation error at the output of the CORDIC phase rotator, stochastic rounding is employed. A dither signal is added to avoid errors due to nonlinear operation of D/A converters, where D/A conversion of the frequency translated signal is required.

Abstract: The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention includes a family of core cells built from instances of these calculators providing an upward, functionally compatible, extension to a family of Application Specific Integrated Circuit (ASIC) core cells. All of these core cells consistently provide the ability to perform high speed DSP tasks including Fast Fourier Transforms (FFTs), Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The core cells built from the calculators can concurrently perform many non-linear function calculations. The core cells can switch between tasks every clock cycle.

Abstract: An angle rotator uses a coarse stage rotation and a fine stage rotation to rotate an input complex signal in the complex plane according to an angle ?. The coarse stage rotation includes a memory device storing pre-computed cosine ?M and sine ?M values for fast retrieval, where ?M is a radian angle that corresponds to a most significant word (MSW) of the input angle ?. The fine stage rotation uses one or more error values that compensate for approximations and quantization errors associated with the coarse stage rotation. The rotator consolidates operations into a small number of reduced-size multipliers, enabling efficient multiplier implementations such as Booth encoding, yielding a smaller and faster overall circuit.

Abstract: A method and apparatus for complex multiplication includes steps of: (a) receiving a complex multiplicand having a real value and an imaginary value (704); (b) generating a negation of the real value of the complex multiplicand (706); (c) generating a negation of the imaginary value of the complex multiplicand (708); (d) receiving a complex multiplier (710); and (e) selecting a phasor constant having a value wherein a complex product of the complex multiplicand times the complex multiplier times the phasor constant has a real value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand (712).

Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.

Abstract: The multi-mode Multiplier-And-Accumulator of the present invention is used with the double-precision Complex-Valued Multiplier-And Accumulator as a main configuration, and the different precisions and digital modes make it more flexible, compared to the traditional real number Multiplier-And-Accumulator. In addition, it does not have a data alignment problem which occurs in the traditional application of different precision Subword Parallel processors. This kind of Multiplier-And-Accumulator takes a double-precision Complex-Valued Multiplier-And- Accumulator as the main configuration, with four double-precision real-valued multipliers and several groups of accumulators to assist in different modes ofoperation. Each double-precision real- valued multiplier can be segmented into four single-precision multipliers, and then double-precision multiplier products are obtained by means of displacement addition.

Abstract: A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication.

Abstract: A frequency translator uses a CORDIC phase rotator coupled to a phase accumulator to translate an input signal in frequency. The CORDIC phase rotator performs required phase angle rotations of input vectors using only shift and add operations. Thus, the frequency translator can be readily implemented in hardware. Higher precision arithmetic is used in the CORDIC phase rotator operations than the input vectors contain. To avoid truncation error at the output of the CORDIC phase rotator, stochastic rounding is employed. A dither signal is added to avoid errors due to nonlinear operation of D/A converters, where D/A conversion of the frequency translated signal is required.

Abstract: A method and apparatus for complex multiplication includes steps of: (a) receiving a complex multiplicand having a real value and an imaginary value (704); (b) generating a negation of the real value of the complex multiplicand (706); (c) generating a negation of the imaginary value of the complex multiplicand (708); (d) receiving a complex multiplier (710); and (e) selecting a phasor constant having a value wherein a complex product of the complex multiplicand times the complex multiplier times the phasor constant has a real value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand (712).

Abstract: The invention concerns a complex number multiplier receiving the binary number A, B, C and D complimentarily coded in pairs so as to perform the complex multiplication (A+jB)*(C+jD). A first processing stage enables to perform the operations A?B, C?D, and A+B whereof the results are binary numbers in base two with a redundant binary format, and a borrow-save coding for subtractions and carry-save coding for addition. A second processing stage converts said results into coded binary numbers in base four. A third processing stage enables to perform multiplication (A?B)C, (C?D)B and (A+B)D with a redundant binary format and a borrow-save coding. A last stage comprises two adders for working out the real part (A?B)C+(C?D)B and the imaginary part (A+B)D+(C?D)B in a redundant binary format and a borrow-save coding.