Abstract: The invention concerns a complex number multiplier receiving the binary number A, B, C and D complementarily coded in pairs so as to perform the complex multiplication (A+jB)*(C+jD). A first processing stage enables to perform the operations A−B, C−D, and A+B whereof the results are binary numbers in base two with a redundant binary format, and a borrow-save coding for subtractions and carry-save coding for addition. A second processing stage converts said results into coded binary numbers in base four. A third processing stage enables to perform multiplication (A−B)C, (C−D)B and (A+B)D with a redundant binary format and a borrow-save coding. A last stage comprises two adders for working out the real part (A−B)C+(C−D)B and the imaginary part (A+B)D+(C−D)B in a redundant binary format and a borrow-save coding.

Abstract: The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop).

Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register, at least one selectively controlled memory, and a plurality of processing elements. The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

Abstract: A cryptography process utilizes the product of two numbers to generate a key. At least one of the numbers is the result of concatenating a first constant whose bits are all equal to one, and a first variable of u bits. The other number has a length of s bits. The product of the two numbers is obtained from a series of operations, in which the most complex operation involves a multiplication of u bits by s bits.

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Abstract: A pipelined linear array of processor elements (PEs) for performing matrix computations in an efficient manner. The linear array generally includes a head PE and a set of regular PEs, the head PE being a functional superset of the regular PE, with interconnections between nearest neighbor PEs in the array and a feedback path from a non-neighbor regular PE back to the head PE. Each PE includes arithmetic circuitry for performing multiply, combine and accumulate operations, and a register file for storing inputs and outputs of the arithmetic circuitry. The head PE further includes a non-linear function generator. Each PE is pipelined such that the latency for an arithmetic operation to complete is a multiple of the period with which new operations can be initiated. A Very Large Instruction Word (VLIW) program or other type of program may be used to control the array. The array is particularly efficient at performing complex matrix operations, such as, e.g.

Abstract: Multiplication of complex numbers is performed utilizing a single adder. A “mult_i” instruction includes a first subinstruction to perform a multiplication by +i to perform a first portion of a complex multiplication. Next, a second subinstruction calls a multiplication by −i, and the same adder is used to write results to an output register. The output register contains the results of the complex multiplication.

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Abstract: In a method and apparatus for multiplying a complex number in the form of (a+ib), (±1 ±i) the multiplication result is resolved into addition operations providing the real number component of the multiplication result and the coefficient of i in the multiplication result. The addition operations are formed in a plurality of steps, and the terms a and b are combined in each of a pair of arithmetic units in a plurality of steps to provide the real number component and the complex number coefficient. In the preferred form, the multiplication is performed in four pairs of addition, and an operation code determines the signs of each term in each arithmetic unit in each operation.

Abstract: A complex multiplier is described for filtering a signal in the frequency domain. In one embodiment, additional, independent frequency coefficients are supplied by the complex multiplier so that gain and/or phase of the signal may be independently modified (i.e., gain may be modified without affecting phase and vice-versa).

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The simultaneous detection of multiple frequencies allows the receiver to search the frequency range of the transmitted signal in larger increments of frequency, thereby increasing the speed of acquisition. One receiver does not use coherent integration before computation of the transform and advantageously maintains a flat frequency response. The flat frequency response of the DFT circuit enables searching of multiple frequency offsets without CPU intensive processing to compensate for frequency response variations. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory.

Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The simultaneous detection of multiple frequencies allows the receiver to search the frequency range of the transmitted signal in larger increments of frequency, thereby increasing the speed of acquisition. One receiver does not use coherent integration before computation of the transform and advantageously maintains a flat frequency response. The flat frequency response of the DFT circuit enables searching of multiple frequency offsets without CPU intensive processing to compensate for frequency response variations. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory.

Abstract: The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention includes a family of core cells built from instances of these calculators providing an upward, functionally compatible, extension to a family of Application Specific Integrated Circuit (ASIC) core cells. All of these core cells consistently provide the ability to perform high speed DSP tasks including Fast Fourier Transforms (FFTs), Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The core cells built from the calculators can concurrently perform many non-linear function calculations. The core cells can switch between tasks every clock cycle.

Abstract: The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop).

Abstract: A complex vector operation processor for carrying out a complex vector operation includes first and second multiplier sections, first to third adder sections, and a data output section. The first and second multiplier sections are provided in parallel. The first adder section is operatively connected with outputs of the first and second multiplier sections. The second and third adder sections are operatively connected with output of the first adder section and arranged in parallel. The data output section is operatively connected with the second and third adder sections to produce complex operation resultant data.

Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Abstract: A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.

Abstract: When we use multi-mode Multiplier-And-Accumulator with the double-precision Complex-Valued Multiplier-And-Accumulator as our main configuration, the different precisions and digital modes make it more flexible, compared to the traditional real number Multiplier-And-Accumulator. In addition, it does not have the data alignment problem that happen in the traditional application of different precision Subword Parallel processors. This kind of Multiplier-And-Accumulator takes a double-precision Complex-Valued Multiplier-And-Accumulator as the main configuration, with four double-precision real-valued multipliers and several groups of accumulators to assist in different modes of operation. Each double-precision real-valued multiplier can be segmented into four single-precision multipliers, and then we get double-precision multiplier products by means of displacement addition.

Abstract: The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop).

Abstract: An apparatus for processing digital signals includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first register is connected to receive and store the sum and to provide a second input to the adder in response to a clock signal. A second register is connected to receive and store the output of the first register in response to an inverse of the clock signal to enable the addition of two products in a single clock cycle.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: A apparatus for providing a Fast Fourier Transform (FFT) and an inverse FFT is provided. The apparatus comprises a radix-N core. The radix-N core includes at least N multipliers. The radix-N core also includes a twiddle-factor lookup table that stores complex twiddle-factors. The twiddle-factor lookup table is coupled to one input of each of the multipliers. The radix-N core also includes a conversion random access memory (RAM) that stores transform points. The conversion RAM is coupled to another input of each of the multipliers. The radix-N core also includes an array of at least N-times-N adder-subtracter-accumulators.

Abstract: A digital circuit for computing a function consisting of sums and differences of the products of a first vector of N multipliers and a second vector of M multiplicands, where at least one of N and M is greater than one include N multibit recoding circuits and M multiples generator circuits. Each recoding circuit receives a respective multiplier as input and produces a radix-2k signed digit representation of the multiplier as output. Each multiples generator receives a respective multiplicand as input and producing multiples of the multiplicand between one and 2k−1 as output. The output of N recoding circuits and M multiples generator circuits are fed to an N×M array of partial product summers. Each partial product summer produces a respective product output, the set of outputs of the partial product summers comprising the product of each of the multipliers with each of the multiplicands.

Abstract: An improved radix-4 CORDIC rotator iteration stage, using answer digits {−3, −1, 1, 3} instead of the conventional choices of {−3, −2, −1, 0,1, 2, 3} or {−2, −1, 0, 1, 2}, thereby achieving constant magnitude amplification. The invention includes an answer digit decision module, which normally examines only a few digits of the remainder angle &thgr;i−1, thereby saving time when compared to full-length comparison. Very rarely does the answer digit decision process involves examining close to all the digits of the remainder angle. When examining only a few digits of the remainder angle, the circuit takes only approximately 20% longer than a radix-2 CORDIC stage. The invented rotator stage is usable either as a pipeline stage or as a single-stage iterative circuit. For use in a pipeline, the invented stage is to be used only when only a few remainder angle bits need to be examined.

Abstract: A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits of a result, moving a second operand occupying higher order bits of a second storage area to lower order bits of the result, and negating one of the first and second operands of the result.

Abstract: Complex multiplication is performed using a multiplier by generating time division signals with a first clock and a second clock having a speed twice as fast as the first clock and operating the multiplier in a time division mode by the time division signals. Using a first clock and a second clock, the time division signals delayed by one-forth cycle are generated during one cycle of the first clock. Real element and imaginary element of two complex numbers are stored in D flip flops. A multiplexer driven by the time division signals selects each element of the complex numbers. A multiplier multiplies the selected elements in the selected time order. The multiplication results are latched in a plurality of D flip flops according to the time division signals. The latched multiplication results are added or subtracted with adder and subtracter. The outputs of the adder and subtracter are stored in D flip flops and output from the D flip flops, thereby obtaining the multiplication of two complex numbers.

Abstract: The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop).

Abstract: A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits of a result, moving a second operand occupying higher order bits of a second storage area to lower order bits of the result, and negating one of the first and second operands of the result.

Abstract: A method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop). Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number.

Abstract: A complex multiplication circuit of a calculation formula equivalent but different from the usual formula.The calculation formula is as follows:Pr={x(a+b)-b(x+y)} equivalent to (ax-by)Pi={y(a-b)+b(x+y)} equivalent to (ay+bx)Here,Input signal: x+jyMultiplier:a+jbMultiplication result:Pr+jPi.

Abstract: A system (400) alternatively performs real matrix operation in a first mode or performs complex matrix multiplication in a second mode. One input matrix (e.g., {B}) stays in a plurality of memory fields (430-k), while the other input matrix (e.g., {A}) is loaded into a plurality of registers (410-k). Parallel operating groups (405-k, 409-(k+1)) combine elements of {A} with elements of {B}. The groups (405-k, 409-(k+1)) comprise the memory fields (430-k), the registers (410-k) as well as computational units (440-k), switches (420-k) and adder units (460-k). The adder units (460-k) are configured by the switches (420-k) to operate as adders or to operate as accumulators, depending on the mode. Adders provide intermediate results and accumulators accumulate these intermediate results (e.g., Sum) to elements of the resulting matrix {C}. For complex multiplication, real (Re) and imaginary (Im) parts of matrix elements are in processed in adjacent groups.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables permits the computation of vector rotation and large FFTs in an efficient-parallel fashion within a unitary field programmable gate array chip, without off-chip memory for storing constants.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A method and apparatus for performing complex digital filters. According to one aspect of the invention, a computer system generally having a transmitting unit, a processor, and a storage device is described. The storage device is coupled to the processor and has stored therein a routine. When executed by the processor, the routine causes the processor to perform a digital filter on unfiltered data items using complex coefficients to generate an output data stream. Execution of the routine causes the processor to perform outer and inner loops. The outer loop steps through corresponding relationships between the complex coefficients and the unfiltered data items. Each of these corresponding relationships is used by the digital filter to generate the output data stream. The inner loop steps the complex coefficients. Within the inner loop, the unfiltered data item corresponding to the current complex coefficient is determined according to the current corresponding relationship.