Sum Of Cross Products Patents (Class 708/626)

Patent number: 11669302Abstract: An inmemory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratchpad including two consecutive bits for each bit of each number being added, two consecutive bits for carryin (Cin), and two consecutive bits for carryoutbar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.Type: GrantFiled: October 15, 2020Date of Patent: June 6, 2023Assignee: Purdue Research FoundationInventors: Mustafa Ali, Akhilesh Jaiswal, Kaushik Roy

Patent number: 11611345Abstract: A low power sequential circuit (e.g., latch) uses a nonlinear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes passgates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.Type: GrantFiled: August 20, 2021Date of Patent: March 21, 2023Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni

Patent number: 11474785Abstract: A memory device is provided. The memory device includes: a cell region including a first metal pad, a memory cell in the cell region configured to store weight data, a peripheral region including a second metal pad and vertically connected to the memory cell by the first metal pad and the second metal pad, a buffer memory in the peripheral region configured to read the weight data from the memory cell, an input/output pad in the peripheral region configured to receive input data; and a multiplyaccumulate (MAC) operator in the peripheral region configured to receive the weight data from the buffer memory and receive the input data from the input/output pad to perform a convolution operation of the weight data and the input data, wherein the input data is provided to the MAC operator during a first period, and wherein the MAC operator performs the convolution operation of the weight data and the input data during a second period overlapping with the first period.Type: GrantFiled: July 30, 2020Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ga Ram Kim

Patent number: 11294632Abstract: A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N?1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N?1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.Type: GrantFiled: April 29, 2020Date of Patent: April 5, 2022Assignee: Chung Yuan Christian UniversityInventors: ShihHsu Huang, CheWei Tung

Patent number: 11263291Abstract: The present disclosure relates to an apparatus that includes decoding circuitry that decodes a single instruction. The single instruction includes an identifier of a first source operand, an identifier of a second source operand, an identifier of a destination, and an opcode indicative of execution circuitry is to multiply from the identified first source operand and the identified second source operand and store a result in the identified destination. Additionally, the apparatus includes execution circuitry to execute the single decoded instruction to calculate a dot product by calculating a plurality of products using data elements of the identified first and second operands using values less precise than the identified first and second source operands, summing the calculated products, and storing the summed products in the destination.Type: GrantFiled: June 26, 2020Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Gregory Henry, Alexander Heinecke

Patent number: 11113231Abstract: In a processing in memory (PIM) method using a memory device, m*n multiplicand arrangement bits are stored in m*n memory cells by copying and arranging m multiplicand bits of a multiplicand value and m*n multiplier arrangement bits are stored in m*n readwrite unit circuits corresponding to the m*n memory cells by copying and arranging n multiplier bits of a multiplier value. The m*n multiplicand arrangement bits stored in the m*n memory cells are selectively read based on the m*n multiplier arrangement bits stored in the m*n readwrite unit circuits, and m*n multiplication bits are stored in the m*n readwrite unit circuits based on the selectively read m*n multiplicand arrangement bits. A multiplication value of the multiplicand value and the multiplier value is determined based on the m*n multiplication bits stored in the m*n readwrite unit circuits.Type: GrantFiled: August 23, 2019Date of Patent: September 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Youngsun Song

Patent number: 10921122Abstract: A sensor includes an accelerometer, which, in operation, generates accelerometer data, and digital signal processing circuitry. The digital signal processing circuitry, in operation, generates, based on the generated accelerometer data, a value indicative of a cosine of an angle between an acceleration vector associated with current accelerometer data and a reference acceleration vector, compares the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with one or more thresholds and generates a tilt signal based on the comparison of the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with the one or more thresholds. The tilt signal may be used as an interrupt signal to an application processor.Type: GrantFiled: February 6, 2018Date of Patent: February 16, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Leo, Paolo Rosingana, Marco Castellano

Patent number: 10831445Abstract: Embodiments of the present disclosure pertain to multimodal digital multiplier circuits and methods. In one embodiment, partial product outputs of digital multiplication circuits are selectively inverted based on a mode control signal. The mode control signal may be set based on a format of the operands input to the multiplier. Example embodiments of the disclosure may multiply combinations of signed and unsigned input operands using different modes.Type: GrantFiled: September 20, 2018Date of Patent: November 10, 2020Assignee: Groq, Inc.Inventor: Christopher Aaron Clark

Patent number: 10416964Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multistage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of stepbystep accumulation based on a control signal of the first control unit; a second adder module comprising a twoinput addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.Type: GrantFiled: June 17, 2016Date of Patent: September 17, 2019Assignee: Institute of Computing Technology, Chinese Academy of SciencesInventors: Zhen Li, Shaoli Liu, Shijin Zhang, Tao Luo, Cheng Qian, Yunji Chen, Tianshi Chen

Patent number: 9787290Abstract: Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.Type: GrantFiled: May 20, 2015Date of Patent: October 10, 2017Assignee: Altera CorporationInventors: Martin Langhammer, Simon Peter Finn

Patent number: 9490815Abstract: A field programmable thresholdlogic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.Type: GrantFiled: July 8, 2014Date of Patent: November 8, 2016Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Sarma Vrudhula, Niranjan Kulkarni

Patent number: 9098426Abstract: A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.Type: GrantFiled: March 20, 2013Date of Patent: August 4, 2015Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventor: Herve LeGall

Patent number: 8667043Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na1 multiplied with the second operand bits 0 to nb2, selectively inverting the single bit products of the signed second operand bits 0 to na2 multiplied with the signed second operand bit nb1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb1, na1 and na+nb1 for receiving a final product.Type: GrantFiled: November 6, 2008Date of Patent: March 4, 2014Assignee: Texas Instruments IncorporatedInventor: Christian Wiencke

Patent number: 8667046Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multioperand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).Type: GrantFiled: February 20, 2009Date of Patent: March 4, 2014Assignee: Ecole Polytechnique Federale de Lausanne/Service des Relations IndustriellesInventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi ParandehAfshar

Patent number: 8364741Abstract: A multiplier includes an operation unit that adds or subtracts a first group selected from a current input data, and a second group selected from a next input data corresponding to the first group to generate an operation result, a Booth's encoder that encodes the operation result according to Booth's algorithm, and generates code data, a partial product generation unit that calculates a partial product from the code data as a first partial product, and calculates, in a case where the first group and the second group are specific combination, a second partial product, and an adder that cumulatively adds an output from the partial product generation unit. The specific combination is a combination in which the highestorder bit of each of the first group and the second group is the same value, and the third least significant bit obtained after the subtraction operation is 1.Type: GrantFiled: February 25, 2009Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventor: Yoichi Katayama

Patent number: 8028015Abstract: Methods, apparatus and systems for large number multiplication. A multiplication circuit is provided to compute the product of two operands (A and B), at least one of which is wider than a width associated with the multiplication circuit. Each of the operands includes contiguous ordered wordwide operand segments (Aj and Bi) characterized by specific weights j (integer from 0 to k) and i (integer from 0 to m). The multiplication circuit executes a matrix of wordwide operand segment pair multiplication operations. Multiplication operations are performed on a pair of rows at one time. For each pair of rows, a pair of corresponding Bi wordwide operand segments are read from a memory and wordwide operand segment pair multiplication operations (Aj*Bi) are iteratively performed for each of k+2 columns. For each column a maximum of two additional memory read operations and one memory write operation is required.Type: GrantFiled: August 10, 2007Date of Patent: September 27, 2011Assignee: Inside Contactless S.A.Inventors: Vincent Dupaquis, Russell Hobson

Publication number: 20090198758Abstract: A method for implementing sign extension within a multiprecision multiplier is described. The method includes receiving a first input within a multiplier core of the multiplier, receiving a second input within the multiplier core, and creating partial products in the multiplier core using the first and second inputs. The method also includes summing up the partial products in a partial product reduction tree in the multiplier core. The method also includes performing sign extension within the partial product reduction tree of the multiplier core by adding a value to a partial product of the partial product reduction tree. The method further includes computing an output from the partial product reduction tree, the output including a final product of the first and second inputs signed extended to a desired width.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry S. Barowski, Jeffrey Adam Butts, Silvia M. Mueller, Tim Niggemeier, Jochen Preiss

Publication number: 20080071851Abstract: Method, apparatus, and program means for performing a dotproduct operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dotproduct of at least two operands.Type: ApplicationFiled: September 20, 2006Publication date: March 20, 2008Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva

Patent number: 7139788Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.Type: GrantFiled: July 3, 2001Date of Patent: November 21, 2006Assignee: Arithmatica LimitedInventors: Sunil Talwar, Dmitriy Rumynin

Patent number: 6938061Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.Type: GrantFiled: August 11, 2000Date of Patent: August 30, 2005Assignee: Arithmatica LimitedInventors: Dmitriy Rumynin, Sunil Talwar, Peter Meulemans

Patent number: 6883011Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.Type: GrantFiled: January 25, 2001Date of Patent: April 19, 2005Assignee: Arithmatica LimitedInventors: Dmitriy Rumynin, Sunil Talwar, Peter Meulemans

Patent number: 6567834Abstract: Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby.Type: GrantFiled: June 1, 2000Date of Patent: May 20, 2003Assignee: Elixent LimitedInventors: Alan David Marshall, Anthony Stansfield, Jean Vuillemin

Patent number: 6535646Abstract: A linear transform apparatus for implementing a linear transform on input data values to produce linear transformed output data, the apparatus comprising: input means for inputting input data values one after another to each of a series of multiplication means; a series of multiplication means interconnected with the input means for multiplying a current input data value by a constant to produce a current multiplier output; an interconnection network interconnecting the series of multiplication means to predetermined ones of a series of signed accumulator means; a series of signed accumulator means each interconnected to the interconnection network, each of the signed accumulator means producing an intermediate accumulator output by accumulating a corresponding one of the current multiplier outputs with a corresponding previous intermediate accumulator output, each of the signed accumulator means outputting the intermediate accumulator output as a corresponding linear transformed output data value.Type: GrantFiled: March 2, 1999Date of Patent: March 18, 2003Inventor: Vincenzo Arturo Luca Liguori

Patent number: 6530011Abstract: A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar register and a second data in a vector register. Upon fetching the first data as a first operand and the second data as a second operand, the processing unit performs an operation between the first and second operands in response to an operator. After operations, the result is subsequently stored in a second scalar register.Type: GrantFiled: October 20, 1999Date of Patent: March 4, 2003Assignee: SandCraft, Inc.Inventor: Jack H. Choquette

Patent number: 6490608Abstract: Parallel multipliers and techniques for reducing Wallacetrees in parallel multipliers to achieve fewer reduction stages. The parallel multipliers of the present invention, in one embodiment, require one fewer stage of reduction than conventional multipliers proposed by Wallace and Dadda. Accordingly, fewer adder components are required. The speed of the parallel multipliers of the present invention is also improved due to the fewer number of reduction stages. In another embodiment, the method of the present invention is applicable to signed multiplication and includes a step of performing trial reduction on an input matrix that has a maximum number of nodes per column K. The trial reduction step is performed with a reduction target of &dgr;L2 nodes where &dgr;L1<K≦&dgr;L. If maximum number of nodes per column in the resulting matrix does not exceed &dgr;L2, then reduction steps are performed to generate a reduction tree having L1 reduction stages.Type: GrantFiled: December 9, 1999Date of Patent: December 3, 2002Assignee: Synopsys, Inc.Inventor: Jay Zhu

Patent number: 6470371Abstract: An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time thereof, which includes NXM ANDgates each for ANDing each multiplier bit ranging from a least significant bit to a most significant bit with each multiplicand bit in case of multiplying “N” multiplicand bits and “M” multiplier bits and for performing a partial multiplication and for outputting a least significant bit as a result of the multiplication; and a plurality of inputbits dividers, having 2, 3, and 4inputbits dividers, for receiving an output bit of a corresponding location among a rearranged output bit and a quotient bit outputted from a proceeding input bit in case that the output bits of the ANDgates is shifted to the left by a bit in accordance with a conventional binary multiplication method and for outputting a quotient bit and a remaining bit corresponding to each bit of a multType: GrantFiled: November 24, 1997Date of Patent: October 22, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Soung Hwi Park

Patent number: 6385634Abstract: A method and apparatus for including in a processor instructions for performing multiplyadd operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiplyadd operations on data elements in the first and second packed data.Type: GrantFiled: August 31, 1995Date of Patent: May 7, 2002Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt

Patent number: 6202078Abstract: A booth decoder decodes A or −A according to a booth algorithm, depending upon whether A×B or −A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products of A×B or −A×B following to a result of the decoding, and sequentially adds these partial products. Data C, or data made by inverting bits of C, is input to the partial multiplier/partial adder circuit 30, depending upon whether C should be added or −C should be added to the result of multiplication. Also the data C or data made by inverting bits of C are sequentially added by the partial multiplier/partial adder circuit 30. A final adder circuit 50 executes final addition of these partial products, and adds 1 when −C should be added. Thus, Z=±(A×B)±C (the order of signs being variable) can be calculated.Type: GrantFiled: October 23, 1998Date of Patent: March 13, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Haruhide Kikuchi, Masayuki Koizumi

Patent number: 6167421Abstract: Bitserial processors quickly multiply multiplebit operands using significantly fewer clock cycles as compared to conventional bitserial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bitserial applications, and the embodiments thus provide fast multiplebit multiplications while at the same time providing all of the advantages typically associated with conventional bitserial processors.Type: GrantFiled: April 9, 1998Date of Patent: December 26, 2000Assignee: TeraNex, Inc.Inventors: Woodrow Meeker, Andrew P. Abercrombie, Michele D. Van DykeLewis

Patent number: 6151617Abstract: A multiplier circuit multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary factors, and a combinatorial network provides the final sum of the partial products. The partial multiplications that include at least one of the more significant bits of the operands are performed by logic gating circuits which can be enabled to also carry out a two's complement partial multiplication. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values unrelated to the factors.Type: GrantFiled: June 16, 1999Date of Patent: November 21, 2000Assignee: STMicroelectronics S.r.l.Inventors: Raffaele Costa, Anna Faldarini, Laura Formenti

Patent number: 6122655Abstract: A multiplier generates an array of partial products. The partial products are reduced in a converter having cells defining rows and columns. Cells adjacent to adders alternate between a cell that provides noninverted outputs and a cell that provides inverted outputs, such that alternate rows of cells operate on noninverted data and the intervening rows of cells operate on inverted data. A multiplexer for receiving the outputs from a row of cells may be an inverting multiplexer or a noninverting multiplexer depending on the cell arrangement.Type: GrantFiled: May 15, 1998Date of Patent: September 19, 2000Assignee: Lucent Technologies Inc.Inventors: Alexander Goldovsky, Ravi Kumar Kolagotla

Patent number: 6066178Abstract: A computerbased method and system is disclosed that automates the design and layout of digital multiplier circuits. The preferred method utilizes an automatic design generator having a user interface which receives design requirements for a digital multiplier circuit design. A digital multiplier design generator receives the design requirements for the digital multiplier and retrieves relevant component implementations from a component library. Stored digital multiplier benchmarks are then retrieved from a benchmark memory and applied to corresponding digital multipliers to determine which of the various implementations optimally satisfies the user design requirements. Once the optimal digital multiplier implementation is selected, the digital multiplier design generator produces a logic design including a netlist and a physical design including design directives which are then used to place and route the digital multiplier as a finished layout.Type: GrantFiled: April 10, 1996Date of Patent: May 23, 2000Assignee: LSI Logic CorporationInventors: Owen S. Bair, FangHsing Chen

Patent number: 6035316Abstract: A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiplyadd circuit is coupled to the first and second storage areas. The multiplyadd circuit includes a first, second, third, and fourth multiplier, wherein each of the multipliers receives a corresponding set of said data elements. The multiplyadd circuit further includes a first adder coupled to the first and second multipliers, and second adder coupled to the third and fourth multipliers. A third storage area is coupled to the adders. The third storage area includes a first and second field for saving output of the first and second adders, respectively, as first and second data elements of a third packed data.Type: GrantFiled: February 23, 1996Date of Patent: March 7, 2000Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt, Derrick Chu Lin, Ahmet Bindal

Patent number: 6026483Abstract: A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm.Type: GrantFiled: January 28, 1998Date of Patent: February 15, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Stuart F. Oberman, Ravikrishna Cherukuri, Ming Siu

Patent number: 5983256Abstract: A method and apparatus for including in a processor instructions for performing multiplyadd operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiplyadd operations on data elements in the first and second packed data.Type: GrantFiled: October 29, 1997Date of Patent: November 9, 1999Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt

Patent number: 5978827Abstract: In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high signals in the input values is output in the binary notation, and outputs from a plurality of NDs are added by full adders to execute a high speed operation without carries. In addition, values with no common places are integrated into single data before being added.Type: GrantFiled: April 10, 1996Date of Patent: November 2, 1999Assignee: Canon Kabushiki KaishaInventor: Takeshi Ichikawa

Patent number: 5944775Abstract: A sumofproducts arithmetic unit includes a coefficient register, a data register, a multiplier, an adder, and a data bus used for the transfer of data to and from an external unit. Provision is made to allow addresses in the data register in which sumofproducts arithmetic data is to be stored to be specified without externally specifying an individual address in the data register for each piece of arithmetic data. This provision comprises an automatic data batch storage section, automatic address setting section, or address setting section.Type: GrantFiled: July 31, 1997Date of Patent: August 31, 1999Assignee: Fujitsu LimitedInventor: Matsui Satoshi

Patent number: 5935201Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.Type: GrantFiled: December 22, 1995Date of Patent: August 10, 1999Assignee: STMicroelectronics, S.r.l.Inventors: Raffaele Costa, Anna Faldarini, Laura Formenti

Patent number: 5928317Abstract: A multiplier generates an array of partial products. The partial products are reduced in the more significant side of the array assuming a carryout from the less significant side of the array as taking on a first state to produce a first set of reduced products. The partial products are also reduced in the more significant side of the array assuming a carryout from the less significant side of the array as taking on a second state to produce a second set of reduced products. Both sets of reduced partial products are generated in parallel with the carryout from the least significant side. The first set of reduced products are selected as the reduced products of the more significant side of the array when the carryout from the less significant side of the array takes on the first state. The second set of reduced products are selected as the reduced products of the more significant side of the array when the carryout from the less significant side of the array takes on the second state.Type: GrantFiled: May 5, 1997Date of Patent: July 27, 1999Assignee: Lucent Technologies Inc.Inventors: Jalil FadaviArdekani, Ravi Kumar Kolagotla, Hosahalli R. Srinivas

Patent number: RE38387Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.Type: GrantFiled: August 17, 2001Date of Patent: January 13, 2004Assignee: STMicroelectronics S.r.l.Inventors: Raffaele Costa, Anna Faldarini, Laura Formenti