Binary Patents (Class 708/625)
  • Patent number: 10826679
    Abstract: A digital encrypting and decrypting unit (PMEU) that operates according to a Rivest-Shamir-Adleman (RSA) cryptosystem based on Residue Numeral System (RNS) and Chinese Reminder Theorem (CRT). The unit includes two modular exponentiation calculating units (MES-1, MES-2) to process a two residual signals (X mod p; X mod q) to calculate a result of a modular exponentiation by a binary method. The calculating units have inputs (I-k[i], I-SM, I-MM) and outputs (O-k[i], O-SM, O-MM) for signals representing partial results of the modular exponentiation. A modular exponentiation controlling unit (MECU) is connected to the inputs and outputs of the calculating units to control flow of the signals representing the partial results of the modular exponentiation.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 3, 2020
    Assignee: ADIPS SPOLKA Z OGRANICZONA ODPOWIEDZIALNOSCIA
    Inventors: Janusz Jablonski, Witold Wendrowski
  • Patent number: 10802799
    Abstract: According to an embodiment, there is provided a semiconductor device including a plurality of operation circuits each including a multiplier including a first input terminal and a second input terminal and configured to calculate a product of a value input via the first input terminal and a value input via the second input terminal, and an accumulator configured to integrate an output of the multiplier and output an integrated value that is obtained by integrating output values of the multiplier. The plurality of operation circuits are divided into groups by two manners, where by the first manner multiple operation circuits are configured to receive a common first value via the respective first input terminals, and by the second manner multiple operation circuits are configured to receive a common second value via the respective second input terminals.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Daisuke Miyashita
  • Patent number: 10732932
    Abstract: Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit such as an 18×18 multiplier circuit may be used to support two or more smaller multiplication operations such as two 8×8 integer multiplications or two 9×9 integer multiplications. To implement the two 8×8 or 9×9 unsigned/signed multiplications, the 18×18 multiplier may be configured to support two 8×8 multiplications with one shared operand, two 6×6 multiplications without any shared operand, or two 7×7 multiplications without any shared operand. Any potential overlap of partial product terms may be subtracted out using correction logic. The multiplication of the remaining most significant bits can be computed using associated multiplier extension logic and appended to the other least significant bits using merging logic.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Bogdan Pasca, Martin Langhammer, Sergey Gribok, Gregg William Baeckler
  • Patent number: 10691701
    Abstract: An apparatus comprises: selection circuitry to select the two most preferred items from a set of items having ranking information indicative of an order of preference for the set of items. The selection circuitry comprises at least one selection node circuit, each selection node circuit to receive as inputs an indication of a first pair of items and a second pair of items among the set of items, and comprises first selection circuitry and second selection circuitry. The first selection circuitry to first selection circuitry to select as a first selected item a most preferred one of: a most preferred ranked item of the first pair, and a least preferred item of the second pair. The second selection circuitry to select as a second selected item a most preferred one of: a least preferred item of the first pair, and a most preferred item of the second pair.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 23, 2020
    Assignee: ARM Limited
    Inventor: Simon John Craske
  • Patent number: 10671348
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10528642
    Abstract: A computer-implemented method, computer program product, and apparatus are provided. The method includes substituting N×N first integer elements, among a plurality of first integer elements obtained by dividing first integer data expressing a first integer in a first digit direction, into a first matrix having N rows and N columns. The method further includes substituting each of one or more second integer elements, among a plurality of second integer elements obtained by dividing second integer data expressing a second integer in a second digit direction, into at least one matrix element of a second matrix having N rows and N columns. The method also includes calculating a third matrix that is a product of the first matrix and the second matrix. The method includes outputting each matrix element of the third matrix as a partial product in a calculation of a product of the first integer and the second integer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jun Doi
  • Patent number: 10402167
    Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h?1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 3, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Tim Lee
  • Patent number: 10402168
    Abstract: A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: William C. Hasenplaugh, Kermin E. Fleming, Jr., Tryggve Fossum, Simon C. Steely, Jr.
  • Patent number: 10404277
    Abstract: Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 3, 2019
    Assignee: iDensify LLC
    Inventors: Dan E. Tamir, Dan Bruck
  • Patent number: 10353850
    Abstract: A circuit device includes a detection circuit adapted to output first through n-th detection data, and a serial interface adapted to output the first through n-th detection data as serial data. In the case in which i-th detection data (1?i?n) out of the first through n-th detection data is M bits, and j-th detection data (1?j?n, j?i) is N bits (N<M), the serial interface outputs the serial data added with (M?N) complementary bits on an MSB side of the j-th detection data.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: July 16, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Seiji Eguchi
  • Patent number: 10289259
    Abstract: Defining a presentation format targetable to a demographic by distributing a questionnaire to a terminal connected to a distributed computer network for interactive presentation to a representative in order to elicit selections from the representative, obtaining selections in response to any such interaction, determining preferences based on the selections using code executing in a processor, including positive preferences concerning affirmative selections in response to the interaction with the questionnaire, negative preferences from un-preferred selections in response to the interaction with the questionnaire, or both. The determined preferences are transformed into an integrated passcode using the processor so as to be representative of the selections, the passcode being a representation of the determined preferences for use in defining the presentation format and is used to establish presentation parameters in a message that is delivered over the network to the demographic.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 14, 2019
    Assignee: Visual Targeting Corporation
    Inventor: Steven Kronick
  • Patent number: 10268450
    Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h-1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Tim Lee
  • Patent number: 10255041
    Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64-bit multiplication when Newton-Raphson, divide and square root operations are performed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Leonard Rarick
  • Patent number: 9841945
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: December 12, 2017
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Sunil Kumar Sharma, Mohana Tandyala
  • Patent number: 9836218
    Abstract: The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 5, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 9734126
    Abstract: A system and method for controlling post-silicon configurable instruction behavior are provided. For example, the method includes receiving data related to a compute circuit. The method also includes detecting a data pattern in the data. The method further includes determining that the data pattern is a special case that the compute circuit may handle improperly. The method also includes selecting a value from a post-silicon configurable data set based on the detected data. Further, the method includes changing a behavior of the compute circuit to produce a different output result based on the value selected from the post-silicon configurable data set.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Cuffney, Nicol Hofmann, Michael Klein, Petra Leber, Cédric Lichtenau, Silvia M. Mueller, Timothy J. Slegel
  • Patent number: 9703557
    Abstract: A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.
    Type: Grant
    Filed: November 16, 2014
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jonathan D. Bradbury
  • Patent number: 9684489
    Abstract: Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fixed-point value equal to the substring size.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 20, 2017
    Assignee: Southern Methodist University
    Inventors: Mitchell A. Thornton, Saurabh Gupta
  • Patent number: 9380151
    Abstract: A communication device, including a receiver specification section which specifies a receiving communication device; a control section which transmits, to the receiving communication device specified by the receiver specification section, call request information used for outputting a call request notification and deleting the call request notification after a predetermined time period; a time period setting section which sets a time period during when the call request notification is output by the receiving communication device; a message setting section which sets a call request message; and a cancel instruction section which inputs a cancel instruction of the call request notification.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: June 28, 2016
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Takaaki Yui
  • Patent number: 9372665
    Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na?1 multiplied with the second operand bits 0 to nb?2, selectively inverting the single bit products of the signed second operand bits 0 to na?2 multiplied with the signed second operand bit nb?1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb?1, na?1 and na+nb?1 for receiving a final product.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christian Wiencke
  • Patent number: 9369132
    Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 14, 2016
    Assignee: The Board of Regents of The University of Texas System
    Inventors: Earl E. Swartzlander, Jr., Inwook Kong
  • Patent number: 9329862
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventor: William W. Macy
  • Patent number: 9292283
    Abstract: Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Erdinc Ozturk, Vinodh Gopal, James Guilford
  • Patent number: 9235414
    Abstract: A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Gilbert M. Wolrich, Erdinc Ozturk, James D. Guilford, Kirk S. Yap, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Patent number: 9218319
    Abstract: One embodiment of the present invention is a method for increasing the speed of a computer in identifying occurrences of strings in a character stream that match a string pattern involving repetitions of characters of a particular character class. The method uses a parallel bit stream processing module of the computer, which processing module includes a processor equipped with parallel processing instructions, to form a plurality of parallel property bit streams Pj.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: December 22, 2015
    Assignee: International Characters, Inc.
    Inventor: Robert D. Cameron
  • Patent number: 9176709
    Abstract: A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 3, 2015
    Assignee: Apple Inc.
    Inventor: Junji Sugisawa
  • Patent number: 9158539
    Abstract: A microprocessor, a method for enhanced precision sum-of-products calculation and a video decoding device are provided, in which at least one general-purpose-register is arranged to provide a number of destination bits to a multiply unit, and a control unit is adapted to provide at least a multiply-high instruction and a multiply-high-and-accumulate instruction to the multiply unit. The multiply unit is arranged to receive at least first and second source operands having an associated number of source bits, a sum of source bits exceeding the number of destination bits, connected to a register-extension cache comprising at least one cache entry arranged to store a number of precision-enhancement bits, and adapted to store a destination portion of a result operand in the general-purpose-register and a precision enhancement portion in the cache entry. The result operand is generated by a multiply-high operation or by a multiply-high-and-accumulate operation, depending on the received instructions.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: October 13, 2015
    Assignee: RACORS GmbH
    Inventor: Martin Raubuch
  • Patent number: 9152382
    Abstract: In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Brian J. Hickmann, Dennis R. Bradford, Thomas D. Fletcher
  • Patent number: 9122517
    Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller
  • Patent number: 9077382
    Abstract: According to one embodiment, a Reed-Solomon decoder comprises an analyzer and a calculator. The analyzer analyzes a data frame and calculates a size of a last code word located at an end of a data portion, using information included in a header portion. The calculator calculates correction coefficients, using the size of the last code word, for correcting coefficients of an error locator polynomial and coefficients of an error value polynomial for the last code word in accordance with a difference between a base size of Reed-Solomon code words and the size of the last code word, before error detection for a code word located immediately before the last code word in the data portion begins.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Koichiro Ban
  • Patent number: 9063870
    Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: June 23, 2015
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Kumara Tharmalingam
  • Patent number: 9032009
    Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semicondutor, Inc.
    Inventors: Rohit Goyal, Amit Kumar Dey
  • Publication number: 20150095396
    Abstract: Methods and systems for multiplying varying cast numbers are described herein. By using information related to the inputs to be multiplied, a single multiplier module may be used to multiply many different type cast numbers. These systems and methods may reduce hardware costs and complexity, reduce size of the circuitry, and/or reduce the complexity of the logic, among many other benefits. These systems and methods may be used with in industrial controllers in and industrial environment.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventor: Christopher K. Radtke
  • Patent number: 8918446
    Abstract: Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 23, 2014
    Assignee: Intel Corporation
    Inventors: Brent R. Boswell, Thierry Pons, Tom Aviram
  • Patent number: 8886696
    Abstract: Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: November 11, 2014
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 8788562
    Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 22, 2014
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Kumara Tharmalingam
  • Publication number: 20140164457
    Abstract: An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.
    Type: Application
    Filed: December 7, 2013
    Publication date: June 12, 2014
    Applicant: Wave Semiconductor, Inc.
    Inventors: Samit Chaudhuri, Radoslav Danilak
  • Publication number: 20140136588
    Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na?1 multiplied with the second operand bits 0 to nb?2, selectively inverting the single bit products of the signed second operand bits 0 to na?2 multiplied with the signed second operand bit nb?1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb?1, na?1 and na+nb?1 for receiving a final product.
    Type: Application
    Filed: January 15, 2014
    Publication date: May 15, 2014
    Inventor: Christian Wiencke
  • Publication number: 20140101220
    Abstract: A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. By using the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2n)m).
    Type: Application
    Filed: May 25, 2012
    Publication date: April 10, 2014
    Inventors: Shaohua Tang, Haibo Yi
  • Publication number: 20140067897
    Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 6, 2014
    Applicant: CALYPTO DESIGN SYSTEMS, INC.
    Inventor: Michael L. Case
  • Patent number: 8667046
    Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: March 4, 2014
    Assignee: Ecole Polytechnique Federale de Lausanne/Service des Relations Industrielles
    Inventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi Parandeh-Afshar
  • Patent number: 8639738
    Abstract: A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: January 28, 2014
    Assignee: National Chiao Tung University
    Inventors: Yen-Chin Liao, Hsie-Chia Chang
  • Publication number: 20130304787
    Abstract: A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.
    Type: Application
    Filed: March 20, 2013
    Publication date: November 14, 2013
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Herve Le-Gall
  • Patent number: 8577172
    Abstract: The invention provides a reconfigurable module allowing morphological operations to be carried out for image processing. The module includes an operational block having five inputs, three outputs, three adders/subtracters and four logic blocks. The logic blocks provide various routings between the three adders/subtracters to enable the outputs to deliver the result of basic operations carried out on the five inputs. The reconfigurable module has a reduced number of components while at the same time allowing various morphological operations to be performed whose parameters can be modified. Furthermore, the reconfigurable module is serially combined to carry out more complex morphological operations. The invention also provides a method for implementing the reconfigurable module allowing an integral image, an eroded image, an expanded image, a distance image or projections along the rows and columns of the original image to be determined starting from an original image.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: November 5, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Mickael Guibert, Renaud Schmit
  • Patent number: 8566384
    Abstract: Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. The represented polynomial is subjected to a state transition function as each event is detected, such that the series of binary values is altered to represent a new equivalent class polynomial congruent with a second of the plurality of elements of a multiplicative group. The series of binary values is decoded to determine a number of detected events recorded by the counter.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 22, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventor: David Steven Schuman
  • Patent number: 8495125
    Abstract: A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: July 23, 2013
    Assignee: Microchip Technology Incorporated
    Inventors: Michael I. Catherwood, Settu Duraisamy
  • Patent number: 8468192
    Abstract: The number of multipliers of a particular size that are required to perform a multiplication larger than that size is reduced. In the example of a 36-bit-by-36-bit multiplication, the number of 18-bit-by-18-bit multipliers required may be reduced from four to three. This may be achieved by using recursive decomposition techniques. As discussed in more detail below, if for each of two 36-bit numbers, the “digits” of each respective 36-bit number are added together, and then the two sums are multiplied, the resulting term can be combined additively with the product of the least-significant group of bits of the two 36-bit numbers and the product of the most-significant group of bits of the two 36-bit numbers to provide the desired product. A specialized processing block includes structures to facilitate the recursive decomposition technique.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: June 18, 2013
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 8468193
    Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?yi)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: June 18, 2013
    Assignee: S.A.R.L. Daniel Torno
    Inventor: Daniel Torno
  • Publication number: 20130144927
    Abstract: A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Srikanth Arekapudi, Sudherssen Kalaiselvan
  • Publication number: 20130138711
    Abstract: A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Inventor: Junji Sugisawa