Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as a instance specific version (where at least some portion of the hardware has to be redesigned if the multipliers change) or a non-instance specific version (where the CFMM circuitry can work with arbitrary multipliers without having to redesign the hardware). Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. The CFMM circuitry may include a multiplier circuit that effectively multiplies the common factor by predetermined fixed constants to generate partial products and may further include shifting and add/subtract circuits for processing and combining the partial products to generate corresponding final output products.

Abstract: A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.

Abstract: The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU.

Abstract: A multiplier including a processor that generates at least one N by M array of partial products. The processor includes a first section that performs a first operation that generates an N by M array of partial products representing low order bits, and a second section that performs a second operation that generates an N by M array of partial products representing high order bits. The multiplier also includes a compressor that compresses the N by M array of partial products representing low order bits after the first operation and generates a plurality of carry bits that are utilized in the second operation.

Abstract: A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data source or destination.

Abstract: An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two.

Abstract: In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process.

Abstract: An improved parallel-serial multiplier and accumulator for multiplying a digital multiplicand and a multiplier resulting in a product that is added to an accumulator input. The parallel-serial multiplier and accumulator includes a parallel-serial multiplier and a digit serial adder. The parallel-serial multiplier includes a recoder for receiving the digital multiplier and outputting an ordered sequence of recoded words, a partial product generator for generating partial products that are dependent upon the digital multiplicand and upon each of the ordered sequence of recoded words, and an adder for adding the partial products to provide the product. The adder outputs a digit serial word that contains the least significant bits of an intermediate sum of the partial products as the partial products are being added. The digit serial adder includes a carry save adder that receives the product and the accumulator input to produce the output sum.

Abstract: A two-bit Booth multiplier circuit performs two-bit multiplication iterations using a single adder while retaining the same data path width and the multiplicand multiples of a single-bit Booth multiplier circuit. The two-bit Booth multiplier circuit halves the number of multiplier iterations of a single-bit multiplier. A multiplier circuit includes an adder having a first input terminal, a second input terminal, and an output terminal and a plurality of shift registers. The registers include a multiplicand register having an output terminal connected to the first input terminal of the adder, a temporary shift register having an output terminal connected to the second input terminal of the adder and having an input terminal connected to the output terminal of the adder, and a multiplier shift register having an input terminal connected to the output terminal of the adder and the multiplier shift register and having an output terminal.

Abstract: In a modified Booth's algorithm only one shift unit is required for multiplication of the partial products. This is based on the known coding prescriptions of the Booth's algorithm, which respectively determines from 3 bits of the multiplier how the partial products are to be produced. From the respective 3 bits of the multiplier of the current iteration and of the preceding iteration, it is determined whether the partial product used for the next iteration has to be multiplied by 1/2, 1/4 or 1/8. For this purpose, a coding table and a multiplier that operates according to this principle are provided.